HCMS-2919

HCMS-2919 AVAGO | Alldatasheet

Document overview

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Technical content

Features

• Easy to Use
• Interfaces Directly with Microprocessors
• 0.15" and 0.20" Character Height in 8 Character Package
• Rugged X- and Y-Stackable Package
• Serial Input
• Convenient Brightness Controls
• Wave Solderable
• Low Power CMOS Technology
• TTL Compatible

Applications

• Telecommunications Equipment
• Portable Data Entry Devices
• Computer Peripherals
• Medical Equipment
• Test Equipment
• Business Machines
• Avionics
• Industrial Controls

Description

These products are high performance, easy to use dot matrix displays driven by on-board CMOS IC. Each display can be directly interfaced with a microprocessor, thus eliminating the need for cumbersome interface components. The serial IC interface allows higher character count information displays with a minimum of data lines. The 5x7 pixel format allows the user great freedom to generate user- defined characters. These displays are stackable in the x- and y-directions, making them ideal for high character count displays

Recommend Operating Conditions Over Temperature Range (-40°C to +85°C) Notes: For further description, see Appendix B, Electrical Considerations, “VLOGIC and VLED Considerations”. Absolute Maximum Ratings Notes: For operation in high ambient temperatures, see Appendix A, Thermal Considerations. 8 Digit 0.15" Character Height HCMS-2919 8 Digit 0.20" Character Height HCMS-2976 Logic Supply Voltage, V LOGIC to GND LOGIC -0.3V to 7.0V LED Supply Voltage, V LED to GND LED -0.3V to 5.5V Input Voltage, Any Pin to GND -0.3V to V LOGIC +0.3V Free Air Operating T emperature Range TA -40°C to +85 °C Relative Humidity (non-condensing) 85% Storage Temperature, TS -55°C to 100 °C Maximum Solder T emperature Solder Dipping W ave Soldering 260°C for 5 sec 250°C for 3 sec ESD Protection @ 1.5 k Ω, 100pF (each pin) Class 1, 0-1999V A=25°C 2.4 W Parameter Symbol Min. Max. Units Logic Supply Voltage [1] VLOGIC 3.0 5.5 V LED Supply Voltage [1] VLED 4.5 5.5 V GNDLED to GND LOGIC - -0.3 +0.3 V

Electrical Characteristics Over Operating Temperature Range (-40°C to +85°C) Notes: 1. In SLEEP mode, the internal oscillator and reference current for LED drivers are off. 2. Average peak pixel current is measured at the maximum drive current set by Control Register 0. Individual pixels may exceed t his value. Notes: 1. Refers to the initial case temperature of the device immediately prior to measurement. 2. Measured with all LEDs illuminated in a digit. 3. Dominant wavelength, ld, is derived from the CIE Chromaticity diagram and represents the single wavelength which defines the perceived LED color. Optical Characteristics at 25 ± 1 °C [1] VLED = 5.5V, 100% Peak Current, 100% Pulse Width Parameter Symbol TA = 25°C, VLOGIC = 5.0V -40°C< TA<85°C 3.0V<VLOGIC<5.5V Units Test ConditionsTyp Max Typ Max Input Leakage Current II +15 -5.0 +100 µA VIN = 0 TO V LOGIC ILOGIC OPERATING ILOGIC (OPT) 0.8 5 10 mA V IN = V LOGIC ILOGIC SLEEP [1] ILOGIC (SLP) 10 30 50 µA VIN = V LOGIC ILED BLANK ILED (BL) 4.0 8.0 8.0 mA BL = 0 V ILED SLEEP [1] ILED (SLP) 15.0 50 100 µA Peak Pixel Current [2] IPIXEL 14.0 20 23 mA V LED = 5.5 V All pixels ON, Average value per pixel HIGH level input voltage Vih 2.0 V 4.5V<V LOGIC<5.5V 0.8 VLOGIC 3.0V<VLOGIC<4.5V LOW level input voltage Vil 0.8 V 4.5V<V LOGIC<5.5V 0.2 VLOGIC 3.0V<VLOGIC<4.5V HIGH level output voltage Voh 2.0 V V LOGIC = 4.5V, Ioh = -40µA 0.8 VLOGIC 3.0V<VLOGIC<4.5V LOW level output voltage Vol 0.4 V V LOGIC = 4.5V, Ioh = -40µA 0.2 VLOGIC 3.0V<VLOGIC<4.5V Thermal Resistance R θJ-P 70 °C/W IC junction to pin Display Color Luminous Intensity per LED [2] Character Average (µcd) Peak Wavelength λPeak (nm) Typ. Dominant Wavelength λd [3] (nm) Typ.Min Typical Blue 29 170 428 460

RESET (RST) Sets Control Register bits to logic low. The Dot Register contents are unaffected by the Reset pin. (logic low = reset; logic high = normal operation) DATA IN (DIN) Serial Data input for Dot or Control Register data. Data is entered on the rising edge of the Clock input. DATA OUT (DOUT) Serial Data out put for Dot or Control Register data. This pin is used for cascading multiple displays. CLOCK (CLK) Clock input for writing Dot or Control Register data. When Chip Enable is logic low, data is entered on the rising Clock edge. REGISTER SELECT (RS) Selects Dot Register (RS = logic low) or Control Register (RS = logic high) as the destination for serial data entry. The logic level of RS is latched on the falling edge of the Chip Enable input. CHIP ENABLE (CE) This input must be a logic low to write data to the display. When CE returns to logic high and CLK is logic low, data is latched to either the LED output drivers or a Control Register. OSCILLATOR SELECT Selects either an internal or external display oscillator source. (SEL) (logic low = External Display Oscillator; logic high = Internal Display Oscillator). OSCILLATOR (OSC) Output for the Internal Display Oscillator (SEL = logic high) or input for an External Display Oscillator (SEL = logic low). BLANK (BL) Blanks the display when logic high. May be modulated for brightness control. GNDLED Ground for LED drivers GNDLOGIC Ground for logic. VLED Positive supply for LED drivers VLOGIC Positive supply for logic.

AC Timing Characteristics Over Temperature Range (-40 to +85°C) Notes: 1. Timing specifications increase 0.3ns per pf of capacitive loading above 15pF. 2. This parameter is valid for Simultaneous Mode data entry of the Control Register. Timing Diagram Ref. Number Description Symbol 4.5V<V LOGIC<5.5V V LOGIC = 3V UnitsMin Max Min Max

1 Register Select Setup Time to Chip Enable t rss 10 10 ns

2 Register Select Hold Time to Chip Enable t rsh 10 10 ns

3 Rising Clock Edge to Falling Chip Enable Edge t clkce 20 20 ns

4 Chip Enable Setup Time to Rising Clock Edge t ces 35 55 ns

5 Chip Enable Hold Time to Rising Clock Edge t ceh 20 20 ns

6 Data Setup Time to Rising Clock Edge t ds 10 10 ns

7 Data Hold Time after Rising Clock Edge t dh 10 10 ns

8 Rising Clock Edge to DOUT [1] tdout 10 40 10 65 ns

9 Propagation Delay DIN to DOUT

Simultaneous Mode for one IC [1,2] tdoutp 18 30 ns

10 CE Falling Edge to DOUT Valid t cedo 25 45 ns

11 Clock High Time t clkh 80 100 ns

12 Clock Low Time t clkl 80 100 ns

Reset Low Time t rstl 50 50 ns Clock Frequency F cyc 54 M H z Internal Display Oscillator Frequency F inosc 80 210 80 210 kHz Internal Refresh Frequency F rf 150 410 150 410 Hz External Display Oscillator Frequency Prescaler = 1 Prescaler = 8 F exosc 51.2 410 1000 8000 51.2 410 1000 8000 kHz kHz Display Overview The HCMS-29xx blue LED displays are driven by on- board CMOS ICs. The LEDs are configured as 5x7 font characters and are driven in groups of 4 characters per IC. Each IC consists of a 160-bit shift register (the Dot Register), two 7-bit Control Words, and refresh circuitry. The Dot Register contents are mapped on a one-to- one basis to the display. Thus, an individual Dot Register bit uniquely controls a single LED. 8-character displays have two ICs that are cascaded. The Data Out line of the first IC is internally connected to the Data In line of the second IC forming a 320-bit Dot Register. The display’s other control and power lines are connected directly to both ICs. Reset Reset initializes the Control Register (sets all Control Register bits to logic low) and places the display in the sleep mode. The Reset pin shoud be connected to the system power on reset circuit. The Dot Registers are not cleared upon power-on or by Reset. After power- on, the Dot Register contents are random; however, Reset will put the display in sleep mode, thereby blanking the LEDs. The Control Register and the Control Words are cleared to all zeros by Reset. To operate the display after being Reset, load the Dot Register with logic lows. Then load Control Word 0 with the desired brightness level and set the sleep mode bit to logic high.

Table 1. Register Truth Table Figure 3. Write Cycle Timing Diagram to the procedure shown in Table 1 and Figure 3. corresponding LED on; a logic low turns the LED off. 8-digit display), CE is brought to logic high.

1. Bit D 0 of Control Word 1 must have been preciously set to Low

for serial mode or High for simultaneous mode.

1. Selection of Control Word 1 or Control Word 0 is set by D 7 of the
2. Control Word data is loaded Most Significant Bit (D
3. DATA IS COPIED TO THE CONTROL REGISTER OR THE DOT LATCH AND LED OUTPUTS WHEN CE IS HIGH AND CLK IS LOW.

displayed. Column 0 controls the left-most column. or not pixels in Column 0 are turned-on or turned off. will appear to scroll from right to left. peak pixel current brightness control, and sleep mode. Figure 4. Pixel Map Figure 5. Block diagram

40 BIT

Figure 3. First, RS is brought to logic high and then CE control word configures the displays. Table 2. Control Shift Register selects normal operation or sleep mode. the Internal Display Oscillator and the LED pixel drivers. and Control Words are retained during sleep mode. external oscillator prescale select (see Table 2).

Serial/Simultaneous Data Output D 0 Bit D0 of control word 1 is used to switch the mode of DOUT between serial and simultaneous data entry during Control Register writes. The default mode (logic low) is the serial D OUT mode. In serial mode, D OUT is connected to the last bit D 7 of the Control Shift Register. Storing logic high to bit D 0 changes D OUT to simultaneous mode, which affects the Control Register only. In simultaneous mode, DOUT is logically connected to D IN. This arrangement allows multiple ICs to have their Control Registers written to simultaneously. For example, for n ICs in the serial mode, n * 8 clock pulses to load the same data in all Control Registers. The propagation delay from the first IC to the last is n * t DOUTP. External Oscillator Prescaler Bit D1 Bit D1 of Control Word 1 is used to scale the frequency of an external Display Oscillator. When this bit is logic low, the external Display Oscillator directly sets the internal display clock rate. When this bit is a logic high, the external oscillator is divided by 8. This scaled frequency then sets the internal display clock rate. It takes 512 cycles of the display clock (or 8 x 512 = 4096 cycles of an external clock with the divide by 8 prescaler) to completely refresh the display once. Using the prescaler bit allows the designer to use a higher external oscillator frequency without extra circuitry. This bit has no affect on the internal Display Oscillator Frequency. Bits D2-D6 These bits must always be programmed to logic low. Cascaded ICs Figure 6 shows how two ICs are connected within an HCMS-29XX display. The first IC controls the four left- most characters and the second IC controls the four right-most characters. The Dot Registers are connected in series to form a 320-bit dot shift register. The location of pixel 0 has not changed. However, Dot Shift Register bit 0 of IC2 becomes bit 160 of the 320-bit dot shift register. The Control Registers of the two ICs are independent of each other. This means that to adjust the display brightness the same control word must be entered into both ICs, unless the Control Registers are set to simultaneous mode. Longer character string systems can be built by cascading multiple displays together. This is accomplished by creating a five line bus. This bus consists of CE, RS, BL, Reset, and CLK. The display pins are connected to the corresponding bus line. Thus, all CE pins are connected to the CE bus line. Similarly, bus lines for RS, BL, Reset, and CLK are created. Then D IN is connected to the right-most display. D OUT from this display is connected to the next display. The left-most display receives its D IN from the D OUT of the display to its right. DOUT from the left-most display is not used. Each display may be set to use its internal oscillator, or the displays may be synchronized by setting up one display as the master and the others as slaves. The slaves are set to receive their oscillator input from the master’s oscillator output.

Figure 6. Cascaded ICs.

Appendix A. Thermal Considerations The display IC has a maximum junction temperature of 150°C. The IC junction temperature can be calculated with Equation 1 below. A typical value for R θ JA is 100°C/W. This value is typical for a display mounted in a socket and covered with a plastic filter. The socket is soldered to a .062 in. thick PCB with .020 inch wide, one ounce copper traces. PD can be calculated as Equation 2 below. Figure 7 shows how to derate the power of one IC versus ambient temperature. Operation at high ambient temperatures may require the power per IC to be reduced. The power consumption can be reduced by changing either the N, I PIXEL , Osc cyc or V LED. Changing V LOGIC has very little impact on the power consumption. Figure 7. Maximum power dissipation per IC versus ambient temperature. Appendix B. Electrical Considerations Current Calculations The peak and average display current requirements have a significant impact on power supply selection. The maximum peak current is calculated with Equation 3 below. The average current required by the display can be calculated with Equation 4 below. The power supply has to be able to supply I PEAK transients and supply I LED (AVG) continuously. The range on V LED allows noise on this supply without significantly changing the display brightness. P MAX MAXIMUM POWER DISSIPATION PER IC - W D TA - AMBIENT TEMPERATURE - C 0.7 0.6 0.5 0.4 0.3 0.2 0.1 60555045403530 0.8 0.9 1.0 1.1 1.2 8580757065 90 1.3 RΘ = 100 C/WJ-A Equation 1: TJMAX = T A + P D * RθJA Where: TJMAX = maximum IC junction temperature TA = ambient temperature surrounding the display RθJA = thermal resistance from the IC junction to ambient PD = power dissipated by the IC Equation 2: PD = (N * I PIXEL * Duty Factor * V LED ) + ILOGIC * V LOGIC Where: PD = total power dissipation N = number of pixels on (maximum 4 char * 5 * 7 = 140) IPIXEL = peak pixel current. Duty Factor = 1/8 * Osccyc/64 Osc cyc = number of ON oscillator cycles per row ILOGIC = IC logic current VLOGIC = logic supply voltage Equation 3: IPEAK = M * 20 * I PIXEL Where: IPEAK = maximum instantaneous peak current for the display M = number of ICs in the system 20 = maximum number of LEDs on per IC IPIXEL = peak current for one LED Equation 4: ILED (AVG) = N * I PIXEL * 1/8 * (oscillator cycles)/64 (see Variable Definitions above)

in antistatic tubes or in conductive material. During assembly, a grounded conductive work area should be used and assembly personnel should wear conductive wrist straps. Lab coats made of synthetic material should be avoided since they are prone to static buildup. Input current latchup is caused when the CMOS inputs are subjected to either a voltage below ground (V IN < ground) or to a voltage higher than V LOGIC (V IN > V LOGIC) and when a high current is forced into the input. To prevent input current latchup and ESD damage, unused inputs should be connected to either ground or V LOGIC. Voltages should not be applied to the inputs until V LOGIC has been applied to the display. Appendix C. Oscillator The oscillator provides the internal refresh circuitry with a signal that is used to synchronize the columns and rows. This ensures that the right data is in the dot drivers for that row. This signal can be supplied from either an external source or the internal source. A display refresh rate of 100 Hz or faster ensures flicker- free operation. Thus for an external oscillator the frequency should be greater than or equal to 512 x 100 Hz = 51.2 kHz. Operation above 1 MHz without the prescaler or 8 MHz with the prescaler may cause noticeable pixel to pixel mismatch. Appendix D. Refresh Circuitry This display driver consists of 20 one-of-eight column decoders and 20 constant current sources, 1 one-of- eight row decoder and eight row sinks, a pulse width modulation control block, a peak current control block, and the circuit to refresh the LEDs. The refresh counters and oscillator are used to synchronize the columns and rows. The 160 bits are organized as 20 columns by 8 rows. The IC illuminates the display by sequentially turning ON each of the 8 row-drivers. To refresh the display once takes 512 oscillator cycles. Because there are eight row drivers, each row driver is selected for 64 (512/8) oscillator cycles. Four cycles are used to briefly blank the display before the following row is switched on. Thus, each row is ON for 60 oscillator cycles out of a possible 64. This corresponds to the maximum LED on time. VLOGIC and VLED Considerations The display uses two independent electrical systems. One system is used to power the display’s logic and the other to power the display’s LEDs. These two systems keep the logic supply clean. Separate electrical systems allow the voltage applied to V LED and V LOGIC to be varied independently. Thus, VLED can vary from 0 to 5.5V without affecting either the Dot or the Control Registers. V LED can be varied between 4.0 to 5.5 V without any noticeable variation in light output. However, operating V LED below 4.5 V may cause objectionable mismatch between the pixels and is not recommended. Dimming the display by pulse width modulating V LED is also not recommended. VLOGIC can vary from 3.0 to 5.5 V without affecting either the displayed message or the display intensity. However, operation below 4.5 V will change the timing and logic levels and operation below 3 V may cause the Dot and Control Registers to be altered The logic ground is internally connected to the LED ground by a substrate diode. This diode becomes forward biased and conducts when the logic ground is 0.4 V greater than the LED ground. The LED ground and the logic ground should be connected to a common ground, which can withstand the current introduced by the switching LED drivers. When separate ground connections are used, the LED ground can vary from -0.3 V to +0.3 V with respect to the logic ground. Voltages below -0.3 V can cause all the dots to be ON. Voltage above +0.3 V can cause dimming and dot mismatch. Using a decoupling capacitor between the power supply and ground will help prevent any supply noise in the frequency range greater than that of the functioning display from interfering with the display’s internal circuitry. The value of the capacitor depends on the series resistance from the ground back to the power supply and the range of frequencies that need to be suppressed. It is also advantageous to use the largest ground plane possible. Electrostatic Discharge The inputs to the ICs are protected against static discharge and input current latchup. However, for best results, standard CMOS handling precautions should be used. Before use, the HCMS-29XX should be stored

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries. Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved. the duty factor. Both values are set in Control Word 0. Figure 8. Relative luminous intensity versus ambient