HC351

HC311 ALTERA | Alldatasheet

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© December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 Section I. HardCopy III Device Datasheet This section provides the datasheet for the HardCopy® III device family. This section includes the following chapter: ■ Chapter 1, DC and Switching Characteristics of HardCopy III Devices

Revision History

Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook.

i–2 Section I: HardCopy III Device Datasheet HardCopy III Device Handbook, Volume 3 © December 2008 Altera Corporation

© December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 1. DC and Switching Characteristics of HardCopy III Devices

Electrical Characteristics

This chapter provides information about the absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for HardCopy ® III devices. HardCopy III devices are offered in both commercial and industrial grades. Operating Conditions When HardCopy III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability , you must consider the operating requirements described in this chapter. HardCopy III devices are not speed binned like Stratix ® III devices because HardCopy III devices are designed and built to function at a target frequency based on timing constraints, and operate at either commercial or industrial temperatures. Absolute Maximum Ratings Absolute maximum ratings define the maximum operating conditions for HardCopy III devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied by these conditions. Conditions beyond those listed in Table 1–1 can cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time can have adverse effects on the device. Table 1–1. HardCopy III Device Absolute Maximum Ratings – Preliminary (Part 1 of 2) (Note 1) Symbol Parameter Minimum Maximum Unit VCCL Core voltage power supply –0.5 1.35 V VCC I/O registers power supply –0.5 1.35 V VCCD_ PLL PLL digital power supply –0.5 1.35 V VCCA_PLL PLL analog power supply –0.5 3.75 V VCCPT (2) Power supply for the temperature sensing diode –0.5 3.75 V VCCPGM Configuration pins power supply –0.5 3.9 V VCCPD I/O pre-driver power supply –0.5 3.9 V VCCIO I/O power supply –0.5 3.9 V VC C_C LKI N Differential clock input power supply (top and bottom I/O banks only) –0.5 3.75 V VCCBAT (3) Battery back-up power supply for design security volatile key register —— V VI DC input voltage –0.5 4.0 V TJ Operating junction temperature –55 125 °C IOUT DC output current, per pin –25 40 mA HIII53001-2.0

1–2 Chapter 1: DC and Switching Characteristics of HardCopy III Devices HardCopy III Device Handbook, Volume 3 © December 2008 Altera Corporation Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage shown in Table 1–2 and undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. Table 1–2 lists the maximum allowed input overshoot voltage. The maximum allowed overshoot duration is specified as the percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. TSTG Storage temperature (no bias) –65 150 °C Notes to Table 1–1: (1) Supply voltage specifications apply to voltage readi ngs taken at the device pins and not the power supply. (2) In Stratix III devices, this power supply is also used for programmable power technology. (3) In HardCopy III devices, this power supply is not used. Table 1–1. HardCopy III Device Absolute Maximum Ratings – Preliminary (Part 2 of 2) (Note 1) Symbol Parameter Minimum Maximum Unit Table 1–2. Maximum Allowed Overshoot During Transitions – Preliminary Symbol Parameter Condition Overshoot Duration as % of High Time Unit Vi (AC) AC Input Voltage 41 0 0 . 0 0 0 % 4.05 79.330 % 4.1 46.270 % 4.15 27.030 % 4.2 15.800 % 4.25 9.240 % 4.3 5.410 % 4.35 3.160 % 4.4 1.850 % 4.45 1.080 % 4.5 0.630 % 4.55 0.370 % 4.6 0.220 % 4.65 0.130 % 4.7 0.074 % 4.75 0.043 % 4.8 0.025 % 4.85 0.015 %

1–4 Chapter 1: DC and Switching Characteristics of HardCopy III Devices HardCopy III Device Handbook, Volume 3 © December 2008 Altera Corporation DC Characteristics This section lists the input pin capacitances, on-chip termination tolerance, and hot socketing specifications. Supply Current Standby current is the current the device draws after the device enters user mode with no inputs/outputs toggling and no activity in the device. Since these currents vary largely with the resources used, use the Excel-based Early Power Estimator (EPE) to get supply current estimates for your design. VCCPD (3) I/O pre-driver power supply, 3.0 V — 2.85 3.0 3.15 V I/O pre-driver power supply, 2.5 V — 2.375 2.5 2.625 V VCCIO I/O power supply, 3.0 V — 2.85 3.0 3.15 V I/O power supply, 2.5 V — 2.375 2.5 2.625 V I/O power supply, 1.8 V — 1.71 1.8 1.89 V I/O power supply, 1.5 V — 1.425 1.5 1.575 V I/O power supply, 1.2 V — 1.14 1.2 1.26 V V C C_C LKI N Differential clock input power supply (top and bottom I/O banks only) — 2.375 2.5 2.625 V V CCBAT (4) Battery back-up power supply for design security volatile key register —— — — V V I DC input voltage — –0.3 — 3.6 V VO Output voltage — 0 — V CCIO V TJ Operating junction temperature For commercial use 0— 8 5 ° C For industrial use –40 — 100 °C t RAMP Power supply ramp time Normal POR (PORSEL=0) 50 µs — 300 ms — Fast POR (PORSEL=1) 50 µs — 12 ms — Notes to Table 1–3: (2) In Stratix III devices, this power supply is also used for programmable power technology. (3) V (4) In HardCopy III devices, this power supply is not used. Table 1–3. HardCopy III Device Recommended Operating Conditions – Preliminary (Part 2 of 2) Symbol Parameter Conditions Minimum Typical Maximum Unit

Chapter 1: DC and Switching Characteristics of HardCopy III Devices 1–5 © December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 Table 1–4 lists supply current specifications for VCC_CLKIN and VCCPGM. Use the EPE to get supply current estimates for the remaining power supplies. I/O Pin Leakage Current Table 1–5 defines HardCopy III I/O pin leakage current specifications. On-Chip Termination (OCT) Specifications If OCT calibration is enabled, calibration is automatically performed at power up for I/Os connected to the calibration block. Table 1–6 lists the HardCopy III OCT calibration block accuracy specifications. Table 1–4. Supply Current Specifications for VCC_CLKIN and VCCPGM – Preliminary (Note 1) Symbol Parameter Min Max Unit ICLKIN VCC_CLKIN current specifications 0 TBD mA IPGM VCCPGM current specifications 0 TBD mA Note to Table 1–4: (1) Pending silicon characterization. Table 1–5. HardCopy III I/O Pin Leakage Current – Preliminary (Note 1), (2) Symbol Parameter Conditions Min Typ Max Unit II Input pin leakage current V I = VCCIOMAX to 0 V –10 — 10 μA IOZ Tri-stated I/O pin leakage current VO = VCCIOMAX to 0 V –10 — 10 μA Notes To Table 1–5: (1) This value is specified for normal device operation. The value may vary during power up. This applies for all V CCIO (2) The 10 mA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current is observed when the diode is on. Table 1–6. HardCopy III On-Chip Termination Calibration Accuracy Specifications – Preliminary (Part 1 of 2) (Note 1) Symbol Description Conditions Calibration Accuracy UnitCommercial (2) Industrial 25−Ω RS 3.0/2.5 Internal series termination with calibration (25-Ω setting) VCCIO = 3.0/2.5 V TBD — % 50−Ω RS 3.0/2.5 Internal series termination with calibration (50-Ω setting) VCCIO = 3.0/2.5 V TBD — % 50−Ω RT 2.5 Internal parallel termination with calibration (50-Ω setting) VCCIO = 2.5 V TBD — % 25−Ω RS 1.8 Internal series termination with calibration (25-Ω setting) VCCIO = 1.8 V TBD — % 50−Ω RS 1.8 Internal series termination with calibration (50-Ω setting) VCCIO = 1.8 V TBD — % 50−Ω RT 1.8 Internal parallel termination with calibration (50-Ω setting) VCCIO = 1.8 V TBD — % 50−Ω RS 1.5 Internal series termination with calibration (50-Ω setting) VCCIO = 1.5 V TBD — %

1–6 Chapter 1: DC and Switching Characteristics of HardCopy III Devices HardCopy III Device Handbook, Volume 3 © December 2008 Altera Corporation The accuracy listed in Table 1–6 is valid at the time of calibration. If the voltage or temperature changes, the termination resistance value varies. Table 1–7 lists the resistance tolerance for HardCopy III on-chip termination. Table 1–8 lists OCT variation with temperature and voltage after power-up calibration. Use Table 1–8 and Equation 1–1 to determine OCT variation without re-calibration. 1 Note that RCAL is calibrated on-chip termination at power-up. ΔT and ΔV are variations in temperature and voltage (VCCIO) at power-up. 50−Ω RT 1.5 Internal parallel termination with calibration (50-Ω setting) VCCIO = 1.5 V TBD — % 50−Ω RS 1.2 Internal series termination with calibration (50-Ω setting) VCCIO = 1.2 V TBD — % 50−Ω RT 1.2 Internal parallel termination with calibration (50-Ω setting) VCCIO = 1.2 V TBD — % Notes to Table 1–6: (1) OCT calibration accuracy is valid at the time of calibration only. (2) Pending silicon characterization. Table 1–6. HardCopy III On-Chip Termination Calibration Accuracy Specifications – Preliminary (Part 2 of 2) (Note 1) Symbol Description Conditions Calibration Accuracy UnitCommercial (2) Industrial Table 1–7. On-Chip Termination Resistance Tolerance Specification for I/Os – Preliminary (Note 1) Symbol Description Resistance Tolerance UnitCommercial Max Industrial Max ROCT_UNCAL Internal series termination without calibration TBD — % ROCT_CAL Internal series termination with calibration (2) —% Notes to Table 1–7: (1) Pending silicon characterization. (2) For resistance tolerance after power-up calibration, refer to Table 1–8. Equation 1–1. ROCT RCAL 1 dR ⎛⎞=

Chapter 1: DC and Switching Characteristics of HardCopy III Devices 1–7 © December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 Pin Capacitance Table 1–9 shows the HardCopy III device family pin capacitance. Hot Socketing Table 1–10 lists the hot socketing specifications for HardCopy III devices. Table 1–8. On-Chip Termination Variation after Power-up Calibration – Preliminary (Note 1), (2) Symbol Description V CCIO (V) Commercial Typical Unit dR/dV OCT variation with voltage without re-calibration

3.0 TBD %/mV

2.5 TBD %/mV

1.8 TBD %/mV

1.5 TBD %/mV

1.2 TBD %/mV

dR/dT OCT variation with temperature without re-calibration

3.0 TBD %/°C

2.5 TBD %/°C

1.8 TBD %/°C

1.5 TBD %/°C

1.2 TBD %/°C

Note to Table 1–8: (1) Valid for V CCIO range of ± 5% and temperature range of 0° to 85° C. (2) Pending silicon characterization. Table 1–9. HardCopy III Device Capacitance – Preliminary (Note 1) Symbol Parameter Typical Unit CIOTB Input capacitance on top and bottom I/O pins TBD pF CIOLR Input capacitance on left and right I/O pins TBD pF CCLKTB Input capacitance on top and bottom dedicated clock input pins TBD pF CCLKLR Input capacitance on left and right dedicated clock input pins TBD pF COUTFB Input capacitance on dual-purpose clock output and feedback pins TBD pF CCLK1, CCLK3, CCLK8, and CCLK10 Input capacitance for dedicated clock input pins TBD pF Note to Table 1–9: (1) Pending silicon characterization. Table 1–10. HardCopy III Hot Socketing Specifications – Preliminary (Note 1) Symbol Parameter Maximum IIOPIN(DC) DC current per I/O pin 300 μA IIOPIN(AC) AC current per I/O pin 8 mA for ≤ 10 ns Note to Table 1–10: (1) Pending silicon characterization.

1–8 Chapter 1: DC and Switching Characteristics of HardCopy III Devices HardCopy III Device Handbook, Volume 3 © December 2008 Altera Corporation Internal Weak Pull-Up Resistor Table 1–11 lists the weak pull-up resistor values for HardCopy III devices. I/O Standard Specifications Table 1–12 through Table 1–17 list input voltage sensitivities (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for all I/O standards supported by HardCopy III devices. Refer to Table 1–33 on page 1–21 for an explanation of terms used in Table 1–12 through Table 1–17. VOL and VOH values are valid at the corresponding IOL and IOH, respectively. Table 1–11. HardCopy III Internal Weak Pull-Up Resistor – Preliminary (Note 1), (2) Symbol Parameter Conditions Min Typ Max Unit RPU Value of I/O pin pull-up resistor before and during user mode, if the pull-up resistor option is enabled V CCIO = 3.0 V ± 5% (3) —2 5 — k Ω VCCIO = 2.5 V ± 5% (3) —2 5 — k Ω VCCIO = 1.8 V ± 5% (3) —2 5 — k Ω VCCIO = 1.5 V ± 5% (3) —2 5 — k Ω VCCIO = 1.2 V ± 5% (3) —2 5 — k Ω Notes to Table 1–11: (1) Pending silicon characterization. (2) All I/O pins have an option to enable weak pull-up except test and JTAG pins. (3) Pin pull-up resistance values may be lower if an external source drives the pin higher than V CCIO. Table 1–12. Single-Ended I/O Standards Specifications — Preliminary I/O Standard VCCIO (V) V IL (V) V IH (V) V OL (V) V OH (V) IOL (mA) I OH (mA)Min Typ Max Min Max Min Max Max Min 3.0-V LVCMOS 0.2 0.1 –0.1 2.5V LVTTL/ LVCMOS 1.8V LVTTL/ LVCMOS V CCIO 0.65 × VCCIO VCCIO + 0.3

0.45 V CCIO –

0.45 2– 2

1.5 V LVTTL/

0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO 2– 2 1.2V LVTTL/ LVCMOS VCCIO 0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO 2– 2 3.0-V PCI 2.85 3 3.15 — 0.3 × VCCIO 0.5 × VCCIO 3.6 0.1 × VCCIO 0.9 × VCCIO 1.5 –0.5 3.0-V PCI-X 2.85 3 3.15 — 0.35 × VCCIO 0.5 × VCCIO — 0.1 × VCCIO 0.9 × VCCIO 1.5 –0.5

Chapter 1: DC and Switching Characteristics of HardCopy III Devices 1–9 © December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 Refer to Figure 1–6 in the row “Single-Ended V oltage Referenced I/O Standard” in Table 1–33 for an example of a voltage referenced receiver input waveform and explanation of terms used in Table 1–13. Table 1–13. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications – Preliminary I/O Standard VCCIO (V) V REF (V) V TT (V) Min Typ Max Min Typ Max Min Typ Max SSTL-2 CLASS I, II 2.375 2.5 2.625 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO VREF – 0.04 VREF VREF + 0.04 0.04 VREF VREF + 0.04 SSTL-15 CLASS I, II 1.425 1.5 1.575 0.47 × VCCIO 0.5 × VCCIO 0.53 × VCCIO 0.47 × VCCIO VREF 0.53 × VCCIO HSTL-12 CLASS I, II 1.14 1.2 1.26 0.47 × VCCIO 0.5 × VCCIO 0.53 × VCCIO —V CCIO /2 — Table 1–14. Single-Ended SSTL and HSTL I/O Standards Signal Specifications – Preliminary (Part 1 of 2) I/O Standard VIL (D C) (V) V IH(DC) (V) V IL(AC) (V) V IH(AC) (V) V OL (V) V OH (V) IOL (mA) I OH (mA)Min Max Min Max Max Min Max Min SSTL-2 CLASS I –0.3 V REF – 0.15 VREF + 0.15 VCCIO + 0.3 VREF – 0.31 VREF + 0.31 VTT – 0.57 VTT + 0.57 8.1 –8.1 SSTL-2 CLASS II –0.3 V REF – 0.15 VREF + 0.15 VCCIO + 0.3 VREF – 0.31 VREF + 0.31 VTT – 0.76 VTT + 0.76 16.2 –16.2 SSTL-18 CLASS I –0.3 V REF – 0.125 VREF + 0.125 VCCIO + 0.3 VREF – 0.25 VREF + 0.25 VTT – 0.475 VTT + 0.475 6.7 –6.7 SSTL-18 CLASS II –0.3 V REF – 0.125 VREF + 0.125 VCCIO + 0.3 VREF – 0.25 VREF + 0.25

0.28 V CCIO –

0.28 13.4 –13.4 SSTL-15 CLASS I –0.3 V REF – 0.1 VREF + 0.1 VCCIO + 0.3 VREF – 0.175 VREF + 0.175 0.2 × VCCIO 0.8 × VCCIO 8– 8 SSTL-15 CLASS II –0.3 V REF – 0.1 VREF + 0.1 VCCIO + 0.3 VREF – 0.175 VREF + 0.175 0.2 × VCCIO 0.8 × VCCIO 16 –16 HSTL-18 CLASS I –0.3 V REF – 0.1 VREF + 0.1 VCCIO + 0.3 VREF – 0.2 VREF + 0.2

0.4 V CCIO –

0.4 8– 8 HSTL-18 CLASS II –0.3 V REF – 0.1 VREF + 0.1 VCCIO + 0.3 VREF – 0.2 VREF + 0.2 0.4 16 –16 HSTL-15 CLASS I –0.3 V REF – 0.1 VREF + 0.1 VCCIO + 0.3 VREF – 0.2 VREF + 0.2 0.4 8– 8 HSTL-15 CLASS II –0.3 V REF – 0.1 VREF + 0.1 VCCIO + 0.3 VREF – 0.2 VREF + 0.2 0.4 16 –16

1–10 Chapter 1: DC and Switching Characteristics of HardCopy III Devices HardCopy III Device Handbook, Volume 3 © December 2008 Altera Corporation Refer to Figure 1–2 in the row “Differential I/O Standards” in Table 1–33 for receiver input and transmitter output waveforms, and for all differential I/O standards (LVDS, mini-L VDS, RSDS). V CC_CLKIN is the power supply for differential column clock input pins. VCCPD is the power supply for row I/Os and all other column I/Os. HSTL-12 CLASS I –0.15 V REF – 0.08 VREF + 0.08 VCCIO + 0.15 VREF – 0.15 VREF + 0.15 0.25 × VCCIO 0.75 × VCCIO 8– 8 HSTL-12 CLASS II –0.15 V REF – 0.08 VREF + 0.08 VCCIO + 0.15 VREF – 0.15 VREF + 0.15 0.25 × VCCIO 0.75 × VCCIO 16 –16 Table 1–14. Single-Ended SSTL and HSTL I/O Standards Signal Specifications – Preliminary (Part 2 of 2) I/O Standard VIL (D C) (V) V IH(DC) (V) V IL(AC) (V) V IH(AC) (V) V OL (V) V OH (V) IOL (mA) I OH (mA)Min Max Min Max Max Min Max Min Table 1–15. Differential SSTL I/O Standard Specifications – Preliminary I/O Standard VCCIO (V) V SWING (DC) (V) V X (AC) (V) V SWING (AC) (V) V OX (AC) (V) Min Typ Max Min Max Min Typ Max Min Max Min Typ Max SSTL-2 CLASS I, CLASS II 2.375 2.5 2.625 0.3 VCC IO + 0.6 VCCIO/2 – 0.2 — VCC IO/2 + 0.2

0.6 VCCIO

+ 0.6 VCCIO/2 – 0.15 — VCC IO/2 + 0.15 SSTL-18 CLASS I, CLASS II 1.71 1.8 1.89 0.3 VCC IO + 0.6 VCCIO/2 0.175 — VCC IO/2 0.175

0.5 VCCIO

+ 0.6 VCCIO/2 0.125 — VCC IO/2 0.125 SSTL-15 CLASS I, CLASS II VCCIO/2 —0 . 4—— VCCIO/2 — Table 1–16. Differential HSTL I/O Standards Specifications – Preliminary I/O Standard VCCIO (V) V DIF(DC) (V) V X( AC) (V) V CM( DC) (V) V DI F(AC) (V) Min Typ Max Min Max Min Typ Max Min Typ Max Min Max HSTL-18 CLASS I, II HSTL-15 CLASS I, II HSTL-12 CLASS I, II 1.14 1.2 1.26 0.16 V CCIO + 0.3 — 0.5 × VCCIO — 0.4 × VCCIO 0.5 × VCCIO 0.6 × VCCIO

0.3 V CCIO +

0.48 Table 1–17. Differential I/O Standard Specifications – Preliminary (Part 1 of 2) I/O Standard VCCIO (V) V ID (mV) V ICM (DC) (V) V OD (V) (1) VOCM (V) (1) Min T yp Max Min Condition Max Min Condition Max Min T yp Max Min Typ Max 2.5V LVDS (Row I/O) (2) Dmax ≤ 700 Mbps 1.8 (2) Dmax > 700 Mbps 1.55

Chapter 1: DC and Switching Characteristics of HardCopy III Devices 1–11 © December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 Power Consumption Altera offers two ways to estimate power for a design: the Excel-based Early Power Estimator and the Quartus® II PowerPlay Power Analyzer feature. Use the interactive Excel-based Early Power Estimator prior to designing in order to get a magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after the place-and-route is complete. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates. See Table 1–4 on page 1–5 for supply current estimates for V CCPGM and VCC_CLKIN . Use the EPE and PowerPlay Power Analyzer for current estimates of the remaining power supplies. f For more information about power estimation tools, refer to the Power Play Early Power Estimator User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II Device Handbook. 2.5V LVDS (Column I/O) (2) Dmax ≤ 700 Mbps 1.8 (2) Dmax > 700 Mbps 1.55 RSDS (Row I/O) RSDS (Column I/O) Mini-LVDS (Row I/O) Mini-LVDS (Column I/O) LVPECL (3) 2.375 (4) 2.5 (4) 2.625 (4) 300 — — 0.6 Dmax ≤ 700 Mbps 1.8 Mbps 1.6 Notes to Table 1–17: (1) R L range: 90 ≤ R L ≤ 110 Ω . (2) For data rate: D max > 700 Mbps, the minimum input voltage is 1.0 V, the maximum input voltage is 1.6 V. For Dmax ≤ 700 Mbps, the minimum input voltage is 0 V, the maximum input voltage is 1.85 V. (3) Column and Row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins. Differential c lock inputs in column I/O use VCC_CLKIN which should be powered by 2.5 V. Differential clock inputs in row I/Os are powered by VCCPD. (4) Power supply for column I/O LVPECL differential clock input buffer is V CC_CLKIN. (5) For data rate D max > 700 Mbps, the minimum input voltage is 0.85 V, and the maximum input voltage is 1.75 V. For data rate Dmax ≤ 700 Mbps, the minimum input voltage is 0.45 V, and the maximum input voltage is 1.95 V. Table 1–17. Differential I/O Standard Specifications – Preliminary (Part 2 of 2) I/O Standard VCCIO (V) V ID (mV) V ICM (DC) (V) V OD (V) (1) VOCM (V) (1) Min T yp Max Min Condition Max Min Condition Max Min T yp Max Min Typ Max

1–12 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Switching Characteristics HardCopy III Device Handbook, Volume 3 © December 2008 Altera Corporation Switching Characteristics This section provides performance characteristics of HardCopy III core and periphery blocks for commercial grade devices. HardCopy III devices are designed to meet, at minimum, the –3 speed grade of the Stratix III devices. Silicon characterization determines the actual performance of the HardCopy III devices. These characteristics can be designated as Preliminary or Final, as defined below. ■ Preliminary—Preliminary characteristics are created using simulation results, process data, and other known parameters. ■ Final—Final numbers are based on actual silicon characterization and testing. These numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. Core Performance Specifications This sections describes the clock tree, phase-locked loop (PLL), digital signal processing (DSP), TriMatrix, configuration, and JTAG specifications. Clock Tree Specifications Table 1–18 lists clock tree performance specifications for the logic array, DSP blocks, and TriMatrix Memory blocks for HardCopy III devices. Table 1–18. HardCopy III Clock Tree Performance – Preliminary (Note 1) Device Commercial Grade (MHz) Unit HC311 500 MHz HC321 500 MHz HC322 500 MHz HC331 500 MHz HC332 500 MHz HC351 500 MHz HC352 500 MHz HC361 500 MHz HC362 500 MHz HC372 500 MHz Note to Table 1–18: (1) Pending silicon characterization.

Chapter 1: DC and Switching Characteristics of HardCopy III Devices 1–13 Switching Characteristics © December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 PLL Specifications Table 1–19 describes the HardCopy III PLL specifications when operating in both the commercial junction temperature range (0° to 85° C) and the industrial junction temperature range (–40° to 100°C). Refer to Figure 1–4 in the “PLL Specifications” row in Table 1–33 for a PLL block diagram. Table 1–19. HardCopy III PLL Specifications – Preliminary (Part 1 of 2) (Note 1) Symbol Parameter Min Typ Max Unit fIN Input clock frequency 5 — 717 (2) MHz fINPFD Input frequency to the PFD 5 — 325 MHz fVCO PLL VCO operating range 600 — 1300 MHz tEINDUTY Input clock or external feedback clock input duty cycle 40 — 60 % fOUT Output frequency for internal global or regional clock — — 717 (3) MHz fOUT_EXT Output frequency for external clock output — — 717 (3) MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 % tFCOMP External feedback clock compensation time — — 10 ns tCONFIGPLL Time required to reconfigure PLL scan chain — — — scanclk cycles tCONFIGPHASE Time required to reconfigure phase shift — — — scanclk cycles fSCANCLK scanclk frequency — — 100 MHz tLOCK Time required to lock from end of device power up (4) —— — m s tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) —— — m s fCLBW PLL closed-loop low bandwidth — — — MHz PLL closed-loop medium bandwidth — — — MHz PLL closed-loop high bandwidth (5) —— — M H z t PLL_PSERR Accuracy of PLL phase shift — — — ps tARESET Minimum pulse width on areset signal 10 — — ns tINCCJ (4) Input clock cycle to cycle jitter (FREF ≥ 100 MHz) — — — UI (p–p) Input clock cycle to cycle jitter (FREF < 100 MHz) — — — ps (p–p) tOUTPJ_DC (6) Period jitter for dedicated clock output (FOUT ≥ 100 MHz) — — — ps (p–p) Period jitter for dedicate clock output (FOUT < 100 MHz) — — — mUI (p–p) tOUTCCJ_DC (6) Cycle to cycle jitter for dedicated clock output (FOUT ≥ 100 MHz) — — — ps (p–p) Cycle to cycle jitter for dedicated clock output (FOUT < 100 MHz) — — — mUI (p–p) tOUTPJ_IO (6) Period jitter for clock output on regular I/O (FOUT ≥ 100 MHz) — — — ps (p–p) Period jitter for clock output on regular I/O (FOUT < 100 MHz) — — — mUI (p–p) tOUTCCJ_IO (6) Cycle to cycle jitter for clock output on regular I/O (FOUT ≥

100 MHz)

—— — p s ( p – p ) Cycle to cycle jitter for clock output on regular I/O (FOUT < —— — m U I ( p – p )

1–14 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Switching Characteristics HardCopy III Device Handbook, Volume 3 © December 2008 Altera Corporation DSP Block Specifications Table 1–20 describes the HardCopy III DSP performance specifications. fDRIFT Frequency drift after PFDENA is disabled for duration of 100 ms — — — % Notes to Table 1–19: (1) Pending silicon characterization. (2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. (3) This specification is limited by the lower of the two: I/O f MAX or fOUT of the PLL. (4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps. (5) High bandwidth PLL settings are not supported in external feedback mode. (6) Peak-to-peak jitter with a probability level of 10 –12(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. Table 1–19. HardCopy III PLL Specifications – Preliminary (Part 2 of 2) (Note 1) Symbol Parameter Min Typ Max Unit Table 1–20. HardCopy III DSP Block Performance Specifications – Preliminary (Note 1), (2) Mode Number of Multipliers Max Unit 9 × 9-bit multiplier (a, c, e, g) (3) 13 6 5 M H z 9 × 9-bit multiplier (b, d, f, h) (3) 14 1 0 M H z 12 × 12-bit multiplier (a, e) (4) 13 6 5 M H z 12 × 12-bit multiplier (b, d, f, h) (4) 14 1 0 M H z 18 × 18-bit multiplier 1 495 MHz 36 × 36-bit multiplier 1 365 MHz Double mode 1 365 MHz 18 × 18-bit multiply adder 2 405 MHz 18 × 18-bit multiply adder 4 405 MHz 18 × 18-bit multiply adder with loop back (5) 24 0 5 M H z 18 × 18-bit multiply accumulator 4 390 MHz 18 × 18-bit multiply adder with chainout 4 390 MHz Input Cascade Independent output of 4 18 × 18 bit multiplier 4 455 MHz 36-bit shift (32 bit data) 1 390 MHz Notes to Table 1–20: (1) Maximum is for fully pipelined block with round and saturation disabled. (2) Pending silicon characterization. (3) The DSP block implements eight independent 9 × 9-bit multipliers using a, b, c, and d for the top half of the DSP block and e, f, g, and h for the bottom DSP half block multipliers. (4) The DSP block implements six independent 12 × 12-bit multipliers using a, b, and d for the top half of the DSP half block and e, f, and h for the bottom DSP half block multipliers. (5) Maximum for non-pipelined block with loopback input registers disabled with round and saturation disabled.

Chapter 1: DC and Switching Characteristics of HardCopy III Devices 1–15 Switching Characteristics © December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 TriMatrix Memory Block Specifications Table 1–21 describes the HardCopy III TriMatrix memory block specifications. Table 1–21. HardCopy III TriMatrix Memory Block Performance Specifications – Preliminary (Part 1 of 2) (Note 1) Memory Block Type Mode TriMatrix Memory Max Unit MLAB Single port 16 × 10 1 500 MHz Simple dual-port 16 × 20 single clock 1 500 MHz ROM 64 × 10 1 500 MHz ROM 32 × 20 1 500 MHz M9K Single-port 8K × 1 1 465 MHz Single-port 4K × 2 or 2K × 4 1 485 MHz Single-port 1K × 9, 512 × 18, or 256 × 36 1 475 MHz Simple dual-port, 8K × 1 single clock 1 460 MHz Simple dual-port, 4K × 2 or 2K × 4, single clock 1 480 MHz Simple dual-port, 1K × 9, 512 × 18, or 256 × 36, single clock 1 475 MHz Simple dual-port, 8K × 1, 4K × 2, or 2K × 4 single clock, with the read-during-write option set to “Old Data” 13 1 2 M H z Simple dual-port, 1K × 9, 512 × 18, or 256 × 36, single clock, with the read-during-write option set to “Old Data” 13 1 2 M H z True dual-port, 8K × 1 single clock 1 440 MHz True dual-port, 4K × 2 or 2K × 4, single clock 1 480 MHz True dual-port, 1K × 9 or 512 × 18, single clock 1 460 MHz True dual-port, 8K × 1, 4K × 2, or 2K × 4, single clock, with the read-during-write option set to “Old Data” 12 9 5 M H z True dual-port, 1K × 9 or 512 × 18, single clock, with the read-during-write option set to “Old Data” 12 8 5 M H z ROM 1P, 8K × 1, 4K × 2, or 2K × 4, single clock, with the read-during-write option set to “Old Data” 14 8 5 M H z ROM 1P, 1K × 9, 512 × 18, single clock, with the read-during-write option set to “Old Data” 14 8 5 M H z ROM 2P, 8K × 1, 4K × 2, or 2K × 4 1 485 MHz ROM 2P, 1K × 9, or 512 × 18 1 485 MHz Min Pulse Width (Clock High Time) — 800 ps

1–16 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Switching Characteristics HardCopy III Device Handbook, Volume 3 © December 2008 Altera Corporation JTAG Specifications Table 1–22 shows the JTAG timing parameters and values for HardCopy III devices. Refer to Figure 1–3 in the “HIGH-SPEED I/O Block” row in Table 1–33 for JTAG timing requirements. Periphery Performance This section describes the periphery performance, including high-speed I/O, external memory interface, and OCT calibration block specifications. M144K True dual-port 16K × 9 or 8K × 18, dual clock 1 300 MHz True dual-port 4K × 36 dual clock 1 430 MHz Simple dual-port 16K × 9 or 8K × 18, dual clock 1 300 MHz Simple dual-port 4K × 36 or 2K × 72, dual clock 1 470 MHz ROM 1 Port 1 500 MHz ROM 2 Port 1 450 MHz Single-port 16K × 9 or 8K × 18 1 330 MHz Single-port 4K × 36 1 500 MHz True dual-port 16K × 9, 8K × 18, or 4K × 36, dual clock with the read-during-write option set to “Old Data” 12 7 0 M H z Simple dual-port 16K × 9, 8K × 18, 4K × 36, or 2K × 72, dual clock with the read-during-write option set to “Old Data” 12 9 2 M H z Simple dual-port 2K × 64 dual clock (with ECC) 1 210 MHz Min Pulse Width (Clock High Time) — 1000 ps Note to Table 1–21: (1) Pending silicon characterization. Table 1–21. HardCopy III TriMatrix Memory Block Performance Specifications – Preliminary (Part 2 of 2) (Note 1) Memory Block Type Mode TriMatrix Memory Max Unit Table 1–22. HardCopy III JTAG Timing Parameters and Values – Preliminary Symbol Parameter Min Max Unit tJCP TCK clock period 30 — ns tJCH TCK clock high time 14 — ns tJCL TCK clock low time 14 — ns tJPSU (TDI) JTAG port setup time for TDI 1 — ns tJPSU (TMS) JTAG port setup time for TMS 3 — ns tJPH JTAG port hold time 5 — ns tJPCO JTAG port clock to output — 11 ns tJPZX JTAG port high impedance to valid output — 14 ns tJPXZ JTAG port valid output to high impedance — 14 ns

Chapter 1: DC and Switching Characteristics of HardCopy III Devices 1–17 Switching Characteristics © December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 High-Speed I/O Specifications Refer to Table 1–33 for definitions of high-speed timing specifications. Table 1–23 shows the high-speed I/O timing for HardCopy III devices. Table 1–23. High Speed I/O Specifications – Preliminary (Note 1), (2), (3) Symbol Conditions Min Typ Max Unit fHSCLK (input clock frequency) Clock boost factor W = 2 to 32 (4) 5— 6 2 5 M H z Clock boost factor W = 1 (SERDES bypassed) 5 — 600 MHz Clock boost factor W = 1 (SERDES used) 150 — 717 MHz Dedicate LVDS-f HSDR (data rate) SERDES factor J = 3 to 10 150 — 1250 Mbps SERDES factor J = 2, uses DDR registers — — TBD (5) Mbps SERDES factor J = 1, uses SDR register — — TBD (5) Mbps Dedicated LVDS-fHS DRDPA (data rate) — 150 — 1250 Mbps LVDS_E_3R-fHSDR — — — 340 Mbps LVDS_E_1R-fHSDR (data rate) — — — 200 Mbps Transmitter tX jitter Total jitter for data rate, 600 Mbps - 1.25 Gbps — — 160 ps Total jitter for data rate, < 600 Mbps — — 0.1 UI Dedicated LVDS Output tRISE and tFALL All differential I/O standards — — 200 ps tDUTY TX output clock duty cycle 45 50 55 % TCCS All differential I/O standards — — 100 ps DPA mode DPA run length — — — (5) UI Soft CDR mode Soft CDR jitter tolerance — — — (5) ps Soft CDR run length — — — (5) UI Soft-CDR PPM tolerance — — — (5) PPM Non DPA mode Sampling window All differential I/O standards — — (5) ps Notes to Table 1–23: (1) When J = 3 to 10, the serializer/deserializer (SERDES) block is used. (2) When J = 1 or 2, the SERDES block is bypassed. (3) The minimum specification is dependent on the clock source (PLL and clock pin, for example) and the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not have a minimum toggle rate. (4) The input clock frequency and the W factor must satisfy the following Left and Right PLL output frequency specification: 150 MHz input clock frequency × W ≤ 1250 MHz. (5) Pending silicon characterization.

1–18 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Switching Characteristics HardCopy III Device Handbook, Volume 3 © December 2008 Altera Corporation External Memory Interface Specifications Table 1–25 through Table 1–30 list the external memory interface specifications for the HardCopy III device family . Use these tables to perform memory interface timing analysis. Table 1–24. DPA Lock Time Specifications – Preliminary (Note 1) Standard Training Pattern Transition Density Min Typ Max Unit SPI-4 00000000001111111111 10% TBD — — Number of repetitions Parallel Rapid I/O 00001111 25% TBD — — Number of repetitions 10010000 50% TBD — — Number of repetitions Miscellaneous 10101010 100% TBD — — Number of repetitions 01010101 100% TBD — — Number of repetitions Note to Table 1–24: (1) Pending silicon characterization. Table 1–25. HardCopy III Maximum Clock Rate Support for External Memory Interfaces with Half-Rate Controller – Preliminary (Note 1) Memory Standards (MHz) Top and Bottom I/O Banks Left and Right I/O Banks DDR3 SDRAM TBD TBD DDR2 SDRAM TBD TBD DDR SDRAM TBD TBD QDRII+ SRAM TBD TBD QDRII SRAM TBD TBD RLDRAM II TBD TBD Note to Table 1–25: (1) Pending silicon characterization. Table 1–26. HardCopy III Maximum Clock Rate Support for External Memory Interfaces with Full-Rate Controller – Preliminary (Note 1) Memory Standards (MHz) Top and Bottom I/O Banks Left and Right I/O Banks DDR2 SDRAM TBD TBD DDR SDRAM TBD TBD Note to Table 1–26: (1) Pending silicon characterization.

Chapter 1: DC and Switching Characteristics of HardCopy III Devices 1–19 Switching Characteristics © December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 External Memory I/O Timing Specifications Table 1–27 and Table 1–28 list HardCopy III device timing uncertainties on the read and write data paths. Use these specifications to determine timing margins for source synchronous paths between the HardCopy III FPGA and the external memory device. Refer to Figure 1–5 in the “SW (sampling window)” row in Table 1–33. Table 1–27. Sampling Window (SW), Read Side – Preliminary (Note 1) Location (2) Memory Type Sampling Window (ps) Setup Hold VIO DDR3 TBD TBD VIO DDR2 TBD TBD VIO DDR1 TBD TBD VIO QDRII / II + TBD TBD VIO RLDRAM II TBD TBD HIO DDR3 TBD TBD HIO DDR2 TBD TBD HIO DDR1 TBD TBD HIO QDRII / II + TBD TBD HIO RLDRAM TBD TBD Notes to Table 1–27: (1) Pending silicon characterization. (2) VIO (vertical I/O) refers to I/Os in the top and bottom banks; HIO (horizontal I/O) refers to I/Os in the left and right banks. Table 1–28. Transmitter Channel-to-Channel Skew (TCCS), Write Side – Preliminary (Note 1) Location (2) Memory Type TCCS (ps) Lead Lag VIO DDR3 TBD TBD VIO DDR2 TBD TBD VIO DDR1 TBD TBD VIO QDRII / II + TBD TBD VIO RLDRAM II TBD TBD HIO DDR3 TBD TBD HIO DDR2 TBD TBD HIO DDR1 TBD TBD HIO QDRII / II + TBD TBD HIO RLDRAM II TBD TBD Notes to Table 1–28: (1) Pending silicon characterization. (2) VIO (vertical I/O) refers to I/Os in the top and bottom banks; HIO (horizontal I/O) refers to I/Os in the left and right banks.

1–20 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Switching Characteristics HardCopy III Device Handbook, Volume 3 © December 2008 Altera Corporation DLL and DQS Logic Block Specifications Table 1–29 describes the delay-locked loop (DLL) frequency range specifications for HardCopy III devices. Table 1–30 describes the DQS phase offset delay per setting for HardCopy III devices. OCT Calibration Block Specifications Table 1–31 shows the on-chip termination calibration block specifications for HardCopy III devices. Table 1–29. HardCopy III DLL Frequency Range Specifications – Preliminary (Note 1) Frequency Mode Frequency Range (MHz) Resolution (Degrees) 0T B D 2 2 . 5 1T B D 3 0 2T B D 3 6 3T B D 4 5 4T B D 3 0 5T B D 3 6 6T B D 4 5 Note to Table 1–29: (1) Pending silicon characterization. Table 1–30. Average DQS Phase Offset Delay per Setting – Preliminary (Note 1), (2), (3), (4) Min Typ Max Unit 71 1 1 5 p s Notes to Table 1–30: (1) The valid settings for phase offset are –64 to +63 for frequency modes 0 to 3 and –32 to +31 for frequency modes 4 to 6. (2) The typical value equals the average of the minimum and maximum values. (3) The delay settings are linear with a cumulative delay variation of ±20ps for all speed grades. (4) Pending silicon characterization. Table 1–31. On-Chip Termination Calibration Block Specification – Preliminary Symbol Description Min Typical Max Unit OCTUSRCLK Clock required by OCT calibration blocks — — 20 MHz tOCTCAL Number of OCTUSRCLK clock cycles required for OCT RS and RT calibration — 1000 — cycles tOCTSHIFT Number of OCTUSRCLK clock cycles required for OCT code to shift out per OCT calibration block — 28 — cycles tRS_RT Time required to dynamically switch from RS to RT —2 . 5 — n s

Chapter 1: DC and Switching Characteristics of HardCopy III Devices 1–21 I/O Timing Model © December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 Duty Cycle Distortion (DCD) Specifications Table 1–32 lists the worst case DCD for HardCopy III devices. Detailed information on duty cycle distortion are published after characterization. I/O Timing Model The I/O timing specifications for HardCopy III devices will be available in a future revision of the DC and Switching Characteristics chapter in volume 3 of the HardCopy III Device Handbook. Glossary Table 1–33 shows the glossary for this chapter. Table 1–32. Duty Cycle Distortion on HardCopy III I/O Pins – Preliminary (Note 1), (2) Symbol Min Max Unit Output Duty Cycle 45 55 % Notes to Table 1–32: (1) Preliminary DCD specification applies to clock outputs from PLLs, global clock tree, IOE driving dedicated, and general purpose I/O pins. (2) Detailed DCD specifications pending silicon characterization. Table 1–33. Glossary Table Letter Subject Definitions A —— B —— C —— D Differential I/O Standards Figure 1–2. Receiver Input Waveforms Transmitter Output Waveforms E —— F fHSCLK HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency. fHSDR HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA. fHSDRDPA HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA. G —— H —— Single-Ended Waveform Differential Waveform Positive Channel (p) = VIH Negative Channel (n) = VIL Ground VID VID VID p − n = 0 V VCM Single-Ended Waveform Differential Waveform Positive Channel (p) = VOH Negative Channel (n) = VOL Ground VOD VOD VOD p − n = 0 V VCM

1–24 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Referenced Documents HardCopy III Device Handbook, Volume 3 © December 2008 Altera Corporation Referenced Documents This chapter references the following documents: ■ Power Play Early Power Estimator User Guide ■ PowerPlay Power Analysis chapter in volume 3 of the Quartus II Device Handbook Document Revision History Table 1–34 shows the revision history for this document. V VCM(DC) DC common mode input voltage. VICM Input common mode voltage: The common mode of the differential signal at the receiver. VID Input differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. VDIF(AC) AC differential input voltage: Minimum AC input differential voltage required for switching. VDIF(DC) DC differential input voltage: Minimum DC input differential voltage required for switching. VIH Voltage input high: The minimum positive voltage applied to the input that will be accepted by the device as a logic high. VIH(AC) High-level AC input voltage VIH(DC) High-level DC input voltage VIL Voltage input low: The maximum positive voltage applied to the input that will be accepted by the device as a logic low. VIL(AC) Low-level AC input voltage VIL(DC) Low-level DC input voltage VOCM Output common mode voltage: The common mode of the differential signal at the transmitter. VOD Output differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. W W HIGH-SPEED I/O BLOCK: Clock boost factor X —— Y —— Z —— Table 1–33. Glossary Table Letter Subject Definitions Table 1–34. Document Revision History Date and Document Version Changes Made Summary of Changes December 2008, v2.0 ■ Updated Table 1–3. ■ Updated Table 1–19. ■ Updated Table 1–23. ■ Made minor editorial changes. May 2008, v1.0 Initial release. —