HB56UW873E-5F

HB56UW873E-F ELPIDA | Alldatasheet

Document overview

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Technical content

Features

• 168-pin socket type package (Dual lead out)  Lead pitch: 1.27 mm
• Single 3.3 V supply: 3.3V ± 0.3V
• High speed  Access time: tRAC = 50/60 ns (max)  Access time: tCAC = 18/20 ns (max)
• Low power dissipation  Active mode: 4.41 W/3.76 W (max)  Standby mode (TTL): 100.8 mW (max)
• Buffered input except RAS and DQ
• 4 byte interleave enabled, dual address input (A0/B0)
• EDO page mode capability
• 4,096 refresh cycle: 64 ms

• 2 variations of refresh  RAS-only refresh  CAS-before-RAS refresh

Ordering Information

Type No. Access time Package Contact pad HB56UW873E-5F HB56UW873E-6F 50 ns 60 ns 168-pin dual lead out socket type Gold Pin Arrangement 1 pin 10 pin 11 pin 40 pin 41 pin 84 pin 85 pin 94 pin 95 pin 124 pin 125 pin 168 pin Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1V SS 43 V SS 85 V SS 127 V SS

2 DQ0 44 OE2 86 DQ36 128 NC

3 DQ1 45 RE2 87 DQ37 129 NC

4 DQ2 46 CE4 88 DQ38 130 NC

5 DQ3 47 NC 89 DQ39 131 NC

6V CC 48 WE2 90 V CC 132 PDE

7 DQ4 49 V CC 91 DQ40 133 V CC

8 DQ5 50 NC 92 DQ41 134 NC

9 DQ6 51 NC 93 DQ42 135 NC

10 DQ7 52 DQ18 94 DQ43 136 DQ54

11 DQ8 53 DQ19 95 DQ44 137 DQ55

12 V SS 54 V SS 96 V SS 138 V SS

13 DQ9 55 DQ20 97 DQ45 139 DQ56

14 DQ10 56 DQ21 98 DQ46 140 DQ57

15 DQ11 57 DQ22 99 DQ47 141 DQ58

16 DQ12 58 DQ23 100 DQ48 142 DQ59

17 DQ13 59 V CC 101 DQ49 143 V CC

Pin Arrangement (cont) Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

18 V CC 60 DQ24 102 V CC 144 DQ60

19 DQ14 61 NC 103 DQ50 145 NC

20 DQ15 62 NC 104 DQ51 146 NC

21 DQ16 63 NC 105 DQ52 147 NC

22 DQ17 64 NC 106 DQ53 148 NC

23 V SS 65 DQ25 107 V SS 149 DQ61

24 NC 66 DQ26 108 NC 150 DQ62

25 NC 67 DQ27 109 NC 151 DQ63

26 V CC 68 V SS 110 V CC 152 V SS

27 WE0 69 DQ28 111 NC 153 DQ64

28 CE0 70 DQ29 112 NC 154 DQ65

29 NC 71 DQ30 113 NC 155 DQ66

30 RE0 72 DQ31 114 NC 156 DQ67

31 OE0 73 V CC 115 NC 157 V CC

32 V SS 74 DQ32 116 V SS 158 DQ68

33 A0 75 DQ33 117 A1 159 DQ69

34 A2 76 DQ34 118 A3 160 DQ70

35 A4 77 DQ35 119 A5 161 DQ71

36 A6 78 V SS 120 A7 162 V SS

37 A8 79 PD1 121 A9 163 PD2

38 A10 80 PD3 122 A11 164 PD4

39 NC 81 PD5 123 NC 165 PD6

40 V CC 82 PD7 124 V CC 166 PD8

41 NC 83 ID0 (V SS ) 125 NC 167 ID1 (V SS )

42 NC 84 V CC 126 B0 168 V CC

A0 to A11, B0 Address input (D0 to D8) : A0 to A11, B0 Row address (D0 to D8) : A0 to A11, B0 Column address (D0 to D8) : A0 to A10, B0 Refresh address (D0 to D8) : A0 to A11, B0 DQ0 to DQ71 Data-in/Data-out RE0, RE2 Row address strobe (RAS) CE0, CE4 Column address strobe (CAS) WE0, WE2 Read/Write enable OE0, OE2 Output enable VCC Power supply VSS Ground PD1 to PD8 Presence detect ID0, ID1 ID bit PDE Presence detect enable NC No connection Presence Detect Pin Assignment PDE = Low PDE = High Pin name Pin No. 50 ns 60 ns All PD1 79 1 1 High-Z PD2 163 0 0 High-Z PD3 80 1 1 High-Z PD4 164 1 1 High-Z PD5 81 1 1 High-Z PD6 165 0 1 High-Z PD7 82 0 1 High-Z PD8 166 0 0 High-Z 1 : High level (driver output) 0 : Low level (driver output)

D0 to D8, 16-bit line driver D0 to D8,16-bit line driver 0.22 µF × 11 pcs PD1 to PD8 V CC VSS VCC VCC VCC VCC VSS VCC VSS VSS PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 * D0 to D8 : HM5165805 : 16-bit line driver

Parameter Symbol Value Unit Terminal voltage on any pin relative to VSS VT –0.5 to +4.6 V Power supply voltage relative to VSS VCC –0.5 to +4.6 V Short circuit output current Iout 50 mA Power dissipation Pt 10 W Storage temperature range Tstg –55 to +125 °C DC Operating Conditions Parameter Symbol Min Typ Max Unit Notes Supply voltage V CC 3.0 3.3 3.6 V 1, 2 VSS 000 V 2 Input high voltage V IH 2.0 — V CC + 0.3 V 1 Input low voltage V IL –0.3 — 0.8 V 1 Ambient temperature range Ta 0 — 70 °C Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.

Parameter Symbol Min Max Min Max Unit Test conditions Notes Operating current I CC1 — 1225 — 1045 mA t RC = min 1, 2 Standby current I CC2 — 28 — 28 mA TTL interface RAS, CAS = VIH Dout = High-Z — 14.5 — 14.5 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z RAS-only refresh current ICC3 — 1225 — 1045 mA t RC = min 2 Standby current I CC5 — 55 — 55 mA RAS = VIH, CAS = VIL Dout = enable CAS-before-RAS refresh current ICC6 — 1225 — 1045 mA t RC = min EDO page mode current ICC7 — 1000 — 910 mA RAS = VIL , CAS cycle, tHPC = tHPC min 1, 3 Input leakage current ILI –5 5 –5 5 µA 0 V ≤ Vin ≤ VCC + 0.3 V Output leakage current ILO –5 5 –5 5 µA 0 V ≤ Vout ≤ VCC Dout = disable Output high voltage VOH 2.4 V CC 2.4 V CC V High Iout = –2 mA Output low voltage V OL 0 0.4 0 0.4 V Low Iout = 2 mA Notes: 1. ICC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, tHPC . Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) C I1 —2 0p F 1 Input capacitance (CAS, WE, OE)C I2 —2 0p F 1 Input capacitance (RAS)C I3 —5 5p F 1 I/O capacitance (DQ) C I/O — 20 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.

AC Characteristics (Ta = 0 to 70°C, VCC = 3.3 V ±0.3 V, VSS = 0 V)*1, *2, *19 Test Conditions

• Input rise and fall times: 2 ns
• Input levels: VIL = 0 V, VIH = 3.0 V
• Input timing reference levels: 0.8 V, 2.0 V
• Output timing reference levels: 0.8 V, 2.0 V
• Output load: 1 TTL gate + CL (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Notes Random read or write cycle time t RC 84 — 104 — ns RAS precharge time t RP 30 — 40 — ns CAS precharge time t CP 8 — 10 — ns RAS pulse width t RAS 50 10000 60 10000 ns CAS pulse width t CAS 8 10000 10 10000 ns Row address setup time t ASR 5— 5— n s Row address hold time t RAH 8 — 10 — ns Column address setup time t ASC 0— 0— n s Column address hold time t CAH 8 — 10 — ns RAS to CAS delay time t RCD 12 32 14 40 ns 3 RAS to column address delay time tRAD 10 20 12 25 ns 4 RAS hold time t RSH 18 — 20 — ns CAS hold time t CSH 38 — 40 — ns CAS to RAS precharge time t CRP 10 — 10 — ns OE to Din delay time t OED 18 — 20 — ns 5 OE delay time from Din t DZO 0— 0— n s 6 CAS delay time from Din t DZC 0— 0— n s 6 Transition time (rise and fall) t T 2 50 2 50 ns 7

Parameter Symbol Min Max Min Max Unit Notes Access time from RAS tRAC — 50 — 60 ns 8, 9 Access time from CAS tCAC — 18 — 20 ns 9, 10, 17 Access time from address t AA — 30 — 35 ns 9, 11, 17 Access time from OE tOEA — 18 — 20 ns 9 Read command setup time t RCS 0— 0— n s Read command hold time to CAS tRCH 0— 0— n s 1 2 Read command hold time from RAS tRCHR 50 — 60 — ns Read command hold time to RAS tRRH 0— 0— n s 1 2 Column address to RAS lead time t RAL 30 — 35 — ns Column address to CAS lead time t CAL 15 — 18 — ns CAS to output in low-Z t CLZ 2— 2— n s Output data hold time t OH 3— 3— n s 2 1 Output data hold time from OE tOHO 3— 3— n s Output buffer turn-off time t OFF — 18 — 20 ns 13, 21 Output buffer turn-off to OE tOEZ — 18 — 20 ns 13 CAS to Din delay time t CDD 18 — 20 — ns 5 Output data hold time from RAS tOHR 3— 3— n s 2 1 Output buffer turn-off to RAS tOFR — 13 — 15 ns 13, 21 Output buffer turn-off to WE tWEZ — 18 — 20 ns 13 WE to Din delay time t WED 18 — 20 — ns RAS to Din delay time t RDD 13 — 15 — ns Write Cycle 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Notes Write command setup time t WCS 0— 0— n s 1 4 Write command hold time t WCH 8 — 10 — ns Write command pulse width t WP 8 — 10 — ns Write command to RAS lead time t RWL 18 — 20 — ns Write command to CAS lead time t CWL 8 — 10 — ns Data-in setup time t DS 0— 0— n s 1 5 Data-in hold time t DH 13 — 15 — ns 15

Parameter Symbol Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 116 — 140 — ns RAS to WE delay time t RWD 72 — 84 — ns 14 CAS to WE delay time t CWD 30 — 34 — ns 14 Column address to WE delay time t AWD 42 — 49 — ns 14 OE hold time from WE tOEH 13 — 15 — ns Refresh Cycle 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Notes CAS setup time (CBR refresh cycle) tCSR 10 — 10 — ns CAS hold time (CBR refresh cycle) tCHR 8 — 10 — ns WE setup time (CBR refresh cycle) tWRP 5— 5— n s WE hold time (CBR refresh cycle) tWRH 8 — 10 — ns RAS precharge to CAS hold time t RPC 5— 5— n s EDO Page Mode Cycle 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Notes EDO page mode cycle time t HPC 20 — 25 — ns 20 EDO page mode RAS pulse width t RASP — 100000 — 100000 ns 16 Access time from CAS precharge t CPA — 33 — 40 ns 9, 17 RAS hold time from CAS precharge t CPRH 33 — 40 — ns Output data hold time from CAS low t DOH 3 — 3 — ns 9, 22 CAS hold time referred OE tCOL 8 — 10 — ns CAS to OE setup time t COP 5— 5— n s Read command hold time from CAS precharge tRCHC 28 — 35 — ns Write pulse width during CAS precharge tWPE 8 — 10 — ns OE precharge time t OEP 8 — 10 — ns

EDO Page Mode Read-Modify-Write Cycle 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Notes EDO page mode read- modify-write cycle time tHPRWC 57 — 68 — ns WE delay time from CAS precharge t CPW 45 — 54 — ns 14 Refresh Parameter Symbol Max Unit Notes Refresh period t REF 64 ms 4096 cycles Notes: 1. AC measurements assume tT = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, than the access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either tOED or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. tWCS , tRWD , tCWD , tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t DS and tDH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. tRASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among tAA , tCAC and tCPA . 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device.

1. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC /VSS line noise, which causes to degrade VIH min/VIL max level. 20. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified tHPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between tOHR and tOH and between tOFR and tOFF . 22. tDOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing reference level. 23. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied V IH or VIL.

Timing Waveform *23 Read Cycle /;/; RAS Address WE Dout OE Din tRC Row Column tRCS tRCH tCDD tDZC High-Z Dout tDZO tOED tRAC tOEA tAA tCAC tCLZ tOH tOFF tOHO tOEZ CAS tRDD tWED tOFR tOHR tWEZ tRAS tCAS tRP tCSH tRCD tRSH tCRP tT tRAD tRAL tCAL tASR tASC tCAH tRCHR tRRH tRAH

tWCS WCS (min) High-Z* t CAS

Delayed Write Cycle*18 Address CAS RAS WE Din OE Dout tRC tRAS tRP tCSH tRCD tRSH tCAS tCRP tT ColumnRow tASR tRAH tASC tCAH tRCS tCWL tRWL tWP tDZC tDS tDH tDZO tOED tOEH tOEP tCLZ tOEZ High-Z Invalid Dout Din High-Z

Read-Modify-Write Cycle*18 Address RAS Din Dout OE WE tRWC tRAS tRP tCRPtCAStRCD tT tRAD tASR tRAH tASC tCAH ColumnRow tRCS tCWD tCWL tAWD tRWD tRWL tWP tDZC tDH tDS DinHigh-Z tDZO tOED tOEH tOEA tCAC tAA tRAC tOHO tOEZ tCLZ Dout High-Z CAS tOEP

CAS-Before-RAS Refresh Cycle RAS CAS WE Address Dout High-Z tOFF tOFR tWRP tWRH tWRP tWRH tCP tRPC tCSR tCHR tCP tRPC tCSR tCHR tCRP tRPtRAS tRCtRC tRPtRAStRP tT

EDO Page Mode Read Cycle (1) Din OE Dout WE Address RAS CAS tCPtCP tCP tT tRCH tRRH tDZC tCDD tRDD High-Z tOFR tOEZ tOHO tOFF tOH tOHR t tCOL t tCPA tAA tCAC tCAC tOEA tAA tRAC tAA tCAC tCPA t tOEZ tOEA tOEZ tAA tCAC t tRASP COP tRP tCAStCAStCAS tCAL tCSH tHPC tHPC CRPt tASR tRAH Column 1 Column 2 Column 3 Column 4 t tCAH tASC tCAH tCAHtASC tCAHtASC tWED tRAL Row Dout 2 Dout 2 Dout 4Dout 1 tCAS tRCS t tRCS Dout 3 tOHO t tCPRHtHPC tOEA tWEZ DZO tOED OHO DOH RCH tWPE tRCHR tCAL tCALtCAL tRSH tRCHC CPA ASC tOEP tOEP

EDO Page Mode Read Cycle (2) /;/; Din OE WE Address tDZC tCDD tRDD High-Z tOFR tOEZ tOHO tOFF tOH tOHR t tCOL t tCPA tAA tCACtCAC tOEA tAA tRAC tAA tDOH t tOEZ t tOEZ tAA tCAC t COP tASR tRAH t tCAH tASC tCAH tCAHtASC tCAHtASC tWED tRAL Dout 2 Dout 4Dout 1 tRCS tOHO tOEA DZO tOED tDOH tCAC tRCHC CPA ASC RAS CAS tCPtCP tCP tT tRCH tRRH tRASP tRP tCAStCAStCAS tCSH tHPC tHPCtHPC CRPt tCAS tCAL tCAL tCAL tCAL tRSH Dout Dout 3Dout 2 OHO OEA tCPA Column 2Column 1Row Column 3 Column 4 tOEP tOEP

EDO Page Mode Early Write Cycle * tWCS WCS (min) RAS Address WE Din Dout tRASP tRP tT tCSH tHPC tRSH tCRPtCAStCPtCAStCPtCAStRCD tASR tRAH tASC tCAH tASC tCAH tASC tCAH tWCHtWCStWCHtWCStWCHtWCS tDHtDS tDHtDS tDHtDS Din 1 Din 2 Din N High-Z* t Row Column 1 Column 2 Column N CAS

EDO Page Mode Delayed Write Cycle*18 /;/; WE Din OE Dout Address RAS tRASP tRP tCRP tRSH tCAS tHPC tCAStCAS tCSH tRCD tT tCP tCP tASC tCAH tASC tCAH tASC tCAH tRAD tASR tRAH tRCS tRCS tRCS tRWL tCWLtCWLtCWL tWPtWPtWP tDZC tDS tDZC tDS tDStDZC tDHtDHtDH tDZO tOED tDZOtOED tDZO tOED tOEH tOEH tOEH tOEZ tCLZtCLZ tOEZ tCLZ tOEZ Invalid Dout Invalid Dout Invalid Dout Din Din Din N Column NColumn 2Column 1Row High-Z CAS tOEP tOEPtOEP

EDO Page Mode Read-Modify-Write Cycle *18 /;/; WE Din OE Dout Address RAS tRASP tCRPtCP tHPRWCtT tRCD tCAS tCP tCAS tCAS tRAD tASR tASC tASC tASC tRAH tCAH tCAH tCAH tCWLtCPWtCWLtCPWtCWLtRWD tAWD tAWD tAWD tCWDtRCStCWD tRCStCWD tRCS tWP tWP tWP tDStDZCtDStDZCtDStDZC tDHtDHtDH tDZO tDZO tDZO tOEH tOEP tOEP tOEP tOEH tOEH tAA tRAC tOEZtCLZ Dout NDout 2Dout 1 Din Din Din N Column NColumn 2Column 1 tRP Row tRWL tOHO tOEA tCAC tOEZtCLZ tOHO tOEA tCAC tCPA tOEZtCLZ tOHO tOEA tCAC tCPA High-Z tOED tOED tOED AAt AAt tRSH CAS

EDO Page Mode Mix Cycle (1)*20 OE Dout WE Address RAS CAS tCPtCP tCPtT tRCH tRRH tCDD tRDD High-Z tOFR tOEZ tOHO tOFF tOH tCPA tAA tCAC tAA tCAC tCPA tOEZ tAA tOEA t tRASP tRP tCAStCAStCAS CRPt tASR tRAH Column 1 Column 2 Column 3 Column 4 tASC tCAH tASC tCAH tCAH tCAH tRAL tCAL Row Dout 2 Dout 4 CPA tCAS tWCS Dout 3 t t tWP tCWL tWCH tWED tWEZ tDS tDH tDS tDH Din 3Din 1 tOEA tOED tOEP tCAC tASC tCPW tAWD OHO tCAL tRCS tRCS tCSH tRCD tRSH DOH ASCt Din

EDO Page Mode Mix Cycle (2)*20 Din OE Dout WE Address RAS CAS tCPtCP tCPtT tRCH tRRH tCDD tRDD High-Z tOFR tOEZ tOHO tOFF tOH tCPA tAA tCAC tAA tCAC tOEZ t tOEA t tRASP tRP tCAStCAStCAS tCSH CRPt tASR tRAH Column 1 Column 2 Column 3 Column 4 tASC tCAH tASC tCAH tCAHtASC tCAH tRAL tRCS Row Dout 1 Dout 4 CPA tCAS tCWL Dout 3 tOHO tWED tWEZ tDS tDH tDS t Din 3Din 2 tOEA t tCAC tCPW tRCHtRCS tWCH tRAC tOED tCOL tOEA tOHO tOEZ t DH OED tRCS tCAL tCAL tRCD tRCHR tWCS tRSH tWP tASC AA tOEP tOEP COP

6.35 0.250 3.175 0.125 Detail B and CDetail A 0.25 max 2.54 min 0.010 max 0.100 min 3.125 ± 0.125 0.123 ± 0.005 1.27 0.050 3.00 133.35 0.118 5.250 127.35 5.014 3.00 0.118 8.89 11.43 36.83 54.61 0.350 0.450 2.1501.450 ABC 1 84 Front side Back side 1.27 ± 0.10 4.00 min 0.157 min 0.050 ±0.004 4.00 max 0.157 max 4.00 0.157 17.78 0.700 25.40 1.000 168 2 – φ 3.00 2 – φ 0.118 1.00 ± 0.05 0.039 ± 0.002 2.00 ± 0.10 0.079 ± 0.004 Component area (Front) Component area (Back) Unit: mm inch

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