PD488588

PD488588 ELPIDA | Alldatasheet

Document overview

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Technical content

Datasheet sections

Features

• Highest sustained bandwidth per DRAM device — 1.6 GB/s sustained data transfer rate — Separate control and data buses for maximized efficiency — Separate row and column control buses for easy scheduling and highest performance — 32 banks: four transactions can take place simultaneously at full bandwidth data rates
• Low latency features — Write buffer to reduce read latency — 3 precharge mechanisms for controller flexibility — Interleaved transactions
• Advanced power management: — Multiple low power states allows flexibility in power consumption versus time to active state — Power-down self-refresh
• Overdrive current mode
• Organization: 2K bytes pages and 32 banks, x 18
• Uses Rambus Signaling Level (RSL) for up to 800MHz operation
• Package : 80-ball FBGA (

Data Sheet E0039N30 (Ver. 3.0) 2 µµµµPD488588

Ordering Information

Organization* words × bits × Internal Banks Clock frequency MHz (max.) /RAS access time (ns) Package µ PD488588FF-C60-53-DH1 512K x 18 x 32s 600 53 80-ball FBGA ( µ BGA) µ PD488588FF-C71-45-DH1 711 45 (17.16 × 10.2) µ PD488588FF-C80-45-DH1 800 45 Note: The “32s” designation indicates that this RDRAM core is composed of 32 banks which use a “split” bank architecture

Data Sheet E0039N30 (Ver. 3.0) 3 µµµµPD488588 Pin Configuration 80-ball FBGA (µµµµ BGA) (17.16 ×××× 10.2) Top View

10 O O O O

8 O O O O O O O O O O O O O O O O O O

7 O O O O O O O O O O O O O O O O O O

4 O O O O O O O O O O O O O O O O O O

3 O O O O O O O O O O O O O O O O O O

1 O O O O

A B C D E F G H J K L M N P R S T U

10 VDD GND GND VDD

8 GND VDD CMD VDD GND GNDa GNDa VDD V DD GND GND VDD V DD GND GND VCMOS VDD GND

7 VDD DQA8 DQA7 DQA5 DQA3 DQA1 CTMN CTM ROW2 ROW0 COL3 COL1 DQB1 DQB3 DQB5 DQB7 DQB8 VDD

4 GND GND DQA6 DQA4 DQA2 DQA0 CFM CFMN ROW1 COL4 COL2 COL0 DQB0 DQB2 DQB4 DQB6 GND GND

3 VDD GND SCK VCMOS GND VDD GND VDD a VREF GND VDD GND GND VDD SIO0 SIO1 GND VDD

1 VDD G N D G N D VDD

A B C D E F G H J K L M N P R S T U Note Some signals can be applied because this pin is not connected to the inside of the chip.

Data Sheet E0039N30 (Ver. 3.0) 4 µµµµPD488588 Pin Description Signal Input / Output Type #pins Description SIO0, SIO1 Input / Output CMOS Note1 2 Serial input/output. Pins for reading from and writing to the control registers using a serial access protocol. Also used for power management. CMD Input CMOS Note1 1 Command input. Pins used in conjunction with SIO0 and SIO1 for reading from and writing to the control registers. Also used for power management. SCK Input CMOS Note1 1 Serial clock input. Clock source used for reading from and writing to the control registers. VDD 18 Supply voltage for the RDRAM core and interface logic. VDDa 1 Supply voltage for the RDRAM analog circuitry. VCMOS 2 Supply voltage for CMOS input/output pins. GND 22 Ground reference for RDRAM core and interface. GND a 2 Ground reference for RDRAM analog circuitry. DQA8..DQA0 Input / Output RSL Note2 9 Data byte A. Nine pins which carry a byte of read or write data between the Channel and the RDRAM. CFM Input RSL Note2 1 Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. CFMN Input RSL Note2 1 Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. VREF 1 Logic threshold reference voltage for RSL signals. CTMN Input RSL Note2 1 Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. CTM Input RSL Note2 1 Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. ROW2..ROW0 Input RSL Note2 3 Row access control. Three pins containing control and address information for row accesses. COL4..COL0 Input RSL Note2 5 Column access control. Five pins containing control and address information for column accesses. DQB8..DQB0 Input / Output RSL Note2 9 Data byte B. Nine pins which carry a byte of read or write data between the Channel and the RDRAM. Total pin count per package 80 Notes 1. All CMOS signals are high-true ; a high voltage is a logic one and a low voltage is logic zero. 2. All RSL signals are low-true ; a low voltage is a logic one and a high voltage is logic zero.

Data Sheet E0039N30 (Ver. 3.0) 5 µµµµPD488588 Block Diagram 11 5 5 9 ROP AV DR BR R CM B M ACOP S DC BCXOP M DX BX Packet Decode Control Registers DEVIDREFR PRER PREX PREC RD, WR ACT DM ROWR ROWA Packet Decode COLMCOLCCOLX 1:8 Demux RCLK RQ7..RQ5 or ROW2..ROW0 SCK, CMD SIO0, SIO1 1:8 Demux RCLK RQ4..RQ0 or COL4..COL0 TCLK CTMDQB8..DQB0 DQA8..DQA0CTMN RCLK CFM CFMN Power Modes RCLKTCLK 1:8 Demux Write Buffer 8:1 Mux TCLK 8:1 Mux RCLK 1:8 Demux Write Buffer Write Buffer Bank 0 Bank 1 Bank 2 Bank 13 Bank 14 Bank 15 Bank 16 Bank 17 Bank 18 Bank 29 Bank 30 Bank 31 SAmp 9 9 72 72 Internal DQA Data PathInternal DQB Data Path Sense Amp 64x72 64x72 DRAM Core 512x128x144 Column Decode & Mask MatchMatch Match XOP Decode Mux Row Decode 9 9 Mux Mux SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp 64x72 6 5 5 5 5 5 7 8 8

Data Sheet E0039N30 (Ver. 3.0) 7 µµµµPD488588

Data Sheet E0039N30 (Ver. 3.0) 8 µµµµPD488588 1. General Description The figure on page 5 is a block diagram of the µ PD488588. It consists of two major blocks : a “core” block built from banks and sense amps similar to those found in other types of DRAM, and a Direct Rambus interface block which permits an external controller to access this core at up to 1.6 GB/s. Control Registers: The CMD, SCK, SIO0, and SIO1 pins appear in the upper center of the block diagram. They are used to write and read a block of control registers. These registers supply the RDRAM configuration information to a controller and they select the operating modes of the device. The nine bit REFR value is used for tracking the last refreshed row. Most importantly, the five bits DEVID specifies the device address of the RDRAM on the Channel. Clocking: The CTM and CTMN pins (Clock-To-Master) generate TCLK (Transmit Clock), the internal clock used to transmit read data. The CFM and CFMN pins (Clock-From-Master) generate RCLK (Receive Clock), the internal clock signal used to receive write data and to receive the ROW and COL pins. DQA, DQB Pins: These 18 pins carry read (Q) and write (D) data across the Channel. They are multiplexed / de- multiplexed from / to two 72-bit data paths (running at one-eighth the data frequency) inside the RDRAM. Banks: The 32 Mbyte core of the RDRAM is divided into 32 one-Mbyte banks, each organized as 512 rows, with each row containing 128 dualocts (2K bytes), and each dualoct containing 16 bytes. A dualoct is the smallest unit of data that can be addressed. Sense Amps: The RDRAM contains 34 sense amps. Each sense amp consists of 1,024 bytes of fast storage (512 for DQA and 512 for DQB) and can hold one-half of one row of one bank of the RDRAM. The sense amp may hold any of the 512 half-rows of an associated bank. However, each sense amp is shared between two adjacent banks of the RDRAM (except for numbers 0, 15, 30, and 31). This introduces the restriction that adjacent banks may not be simultaneously accessed. RQ Pins: These pins carry control and address information. They are broken into two groups. RQ7..RQ5 are also and are used primarily for controlling column accesses. ROW Pins: The principle use of these three pins is to manage the transfer of data between the banks and the sense amps of the RDRAM. These pins are de-multiplexed into a 24-bit ROWA (row-activate) or ROWR (row-operation) packet. COL Pins: The principle use of these five pins is to manage the transfer of data between the DQA/DQB pins and the sense amps of the RDRAM. These pins are de-multiplexed into a 23-bit COLC (column-operation) packet and either a 17-bit COLM (mask) packet or a 17-bit COLX (extended-operation) packet. ACT Command: An ACT (activate) command from an ROWA packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 512 byte sense amps for DQA and two for DQB). PRER Command: A PRER (precharge) command from an ROWR packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be activated.

Data Sheet E0039N30 (Ver. 3.0) 9 µµµµPD488588 RD Command: The RD (read) command causes one of the 128 dualocts of one of the sense amps to be transmitted on the DQA/DQB pins of the Channel. WR Command: The WR (write) command causes a dualoct received from the DQA/DQB data pins of the Channel to be loaded into the write buffer. There is also space in the write buffer for the BC bank address and C column address information. The data in the write buffer is automatically retired (written with optional bytemask) to one of the 128 dualocts of one of the sense amps during a subsequent COP command. A retire can take place during a RD, WR, or NOCOP to another device, or during a WR or NOCOP to the same device. The write buffer will not retire during a RD to the same device. The write buffer reduces the delay needed for the internal DQA/DQB data path turn- around. PREC Precharge: The PREC, RDA and WRA commands are similar to NOCOP, RD and WR, except that a precharge operation is performed at the end of the column operation. These commands provide a second mechanism for performing precharge. PREX Precharge: After a RD command, or after a WR command with no byte masking (M=0), a COLX packet may be used to specify an extended operation (XOP). The most important XOP command is PREX. This command provides a third mechanism for performing precharge.

Data Sheet E0039N30 (Ver. 3.0) 11 µµµµPD488588 Figure 2-1 Packet Formats CTM/CFM COL4 COL3 COL2 COL1 COL0 T8 T9 T10 T11 T12 T13 T14 T15 T8 T9 T10 T11 T0 T1 T2 T3 T0 T1 T2 T3 MA7 MA5 MA3 MA1 M=1 MA6 MA4 MA2 MA0 MB7 MB4 MB1 MB6 MB3 MB0 MB5 MB2 CTM/CFM ROW2 DR4T DR2 BR0 BR3 RsvR R8 R5 ROW1 DR4F DR1 BR1 BR4 RsvR R7 R4 R1 ROW0 DR3 DR0 BR2 RsvB AV=1 R6 R3 R0 ACT a0 PREX d0MSK (b1) PRER c0 WR b1 CTM/CFM COL4 DC4 S=1 COL3 DC3 C5 C3 COL2 DC2 COP1 RsvB BC2 C2 DC1 COP0 BC4 BC1 C1 DC0 COP2 COP3 BC3 BC0 C0 COL1 COL0 CTM/CFM ROW2 ROW1 ROW0 CTM/CFM COL4 COL3 COL2 COL1 COL0 ROP2DR4T DR2 BR0 BR3 ROP10 ROP8 ROP5 DR4F DR1 BR1 BR4 ROP9 ROP7 ROP4 ROP1 DR3 DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0 DX4 XOP4 RsvB BX1 M=0 DX3 XOP3 BX4 BX0 DX2 XOP2 BX3 DX1 XOP1 BX2 DX0 XOP0 T0 T4 T8 T12T1 T5 T9 T13T2 T6 T10 T14T3 T7 T11 T15 ROWA Packet COLM Packet COLC Packet COLX Packet ROWR Packet CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 tPACKET S=1 S=1 Notes 1. The COLM is associated with a previous COLC, and is aligned with the present COLC, indicated by the Start bit (S=1) position. 2. The COLX is aligned with the present COLC, indicates by the Start bit (S=1) position. Note1 Note2

Data Sheet E0039N30 (Ver. 3.0) 12 µµµµPD488588 3. Field Encoding Summary Table 3-1 shows how the six device address bits are decoded for the ROWA and ROWR packets. The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is asserted, the device is not selected. Note that a broadcast operation is indicated when both bits are set. Broadcast operation would typically be used for refresh and power management commands. If the device is selected, the DM (DeviceMatch) signal is asserted and an ACT or ROP command is performed. Table 3-1 Device Field Encodings for ROWA Packet and ROWR Packet DR4T DR4F Device Selection Device Match signal (DM) 1 1 All devices (broadcast) DM is set to 1 0 1 One device selected DM is set to 1 if {DEVID4..DEVID0} == {0, DR3..DR0} else DM is set to 0 1 0 One device selected DM is set to 1 if {DEVID4..DEVID0} == {1, DR3..DR0} else DM is set to 0 0 0 No packet present DM is set to 0 Table 3-2 shows the encodings of the remaining fields of the ROWA and ROWR packets. An ROWA packet is specified by asserting the AV bit. This causes the specified row of the specified bank of this device to be loaded into the associated sense amps. An ROWR packet is specified when AV is not asserted. An 11 bit opcode field encodes a command for one of the banks of this device. The PRER command causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activated. The REFA (refresh-activate) command is similar to the ACT command, except the row address comes from an internal register REFR, and REFR is incremented at the largest bank address. The REFP (refresh-precharge) command is identical to a PRER command. The NAPR, NAPRC, PDNR, ATTN, and RLXR commands are used for managing the power dissipation of the RDRAM and are described in more detail in “23. Power State Management”. The TCEN and TCAL commands are used to adjust the output driver slew rate and they are described in more detail in “25. Current and Temperature Control”. Table 3-2 ROWA Packet and ROWR Packet Field Encodings DM AV ROP10..ROP0 Field Name Command Description Note1 10 9 8 7 6 5 4 3 2 : 0 1 1 Row address ACT Activate row R8..R0 of bank BR4..BR0 of device and move device to ATTN Note2 1 0 1 1 0 0 0 x Note3 x x 000 PRER Precharge bank BR4..BR0 of this device. Increment REFR if BR4..BR0=11111 (see Figure 24-1). 1 0 1 0 1 0 1 0 0 x 000 REFP Precharge bank BR4..BR0 of this device after REFA (see Figure 24-1). 1 0 x x 0 0 0 0 1 x 000 PDNR Move this device into the powerdown (PDN) power state (see figure 23-3). 1 0 x x 0 0 0 1 0 x 000 NAPR Move this device into the nap (NAP) power state (see Figure 23-3). 1 0 x x 0 0 0 1 1 x 000 NAPRC Move this device into the nap (NAP) power state conditionally. 1 0 x x x x x x x 0 000 ATTN Note2 Move this device into the attention (ATTN) power state (see Figure 23-1). 1 0 x x x x x x x 1 000 RLXR Move this device into the standby (STBY) power state (see Figure 23-2). 1 0 0 0 0 0 0 0 0 x 001 TCAL Temperature calibrate this device (see figure 25-2). 1 0 0 0 0 0 0 0 0 x 010 TCEN Temperature calibrate/enable this device (see Figure 25-2). 1 0 0 0 0 0 0 0 0 0 000 NOROP No operation. Notes 1. The DM (Device Match signal) value is determined by the DR4T, DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table 3-1. 2. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1). 3. An “x” entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000).

Data Sheet E0039N30 (Ver. 3.0) 13 µµµµPD488588 Table 3-3 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations (moving data from the write buffer to a sense amp) happen automatically. See Figure 15-1 for a more detailed description. The COLC packet can also specify a PREC command, which precharges a bank and its associated sense amps. The RDA/WRA commands are equivalent to a combining RD/WR with a PREC. RLXC (relax) performs a power mode transition. See 23. Power State Management. Table 3-3 COLC Packet Field Encodings S DC4..DC0 (select device) Note1 COP3..0 Name Command Description 0 - - - - - - - - - — No operation. 1 /= (DEVID4..0) - - - - - — Retire write buffer of this device. 1 == (DEVID4..0) x000 Note2 NOCOP Retire write buffer of this device. 1 == (DEVID4..0) x001 WR Retire write buffer of this device, then write column C6..C0 of bank BC4..BC0 to write buffer. 1 == (DEVID4..0) x010 RSRV Reserved, no operation. 1 == (DEVID4..0) x100 PREC Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure 12-2). 1 == (DEVID4..0) x101 WRA Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired. 1 == (DEVID4..0) x110 RSRV Reserved, no operation. 1 == (DEVID4..0) 1xxx RLXC Move this device into the st andby (STBY) power state (see Figure 23-2). Notes 1. “/=” means not equal, “==” means equal. 2. An “x” entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value(1001). Table 3-4 shows the COLM and COLX field encodings. The M bit is asserted to specify a COLM packet with two 8 bit bytemask fields MA and MB. If the M bit is not asserted, an COLX is specified. It has device and bank address fields, and an opcode field. The primary use of the COLX packet is to permit an independent PREX (precharge) command to be specified without consuming control bandwidth on the ROW pins. It is also used for the CAL (calibrate) and SAM (sample) current control commands (see 25. Current and Temperature Control), and for the RLXX power mode command (see 23. Power State Management). Table 3-4 COLM Packet and COLX Packet Field Encodings M DX4..DX0 (select device) XOP4..0 Name Command Description 1 - - - - - MSK MB/MA bytemasks used by WR/WRA. 0 /= (DEVID4..0) - — No operation. 0 == (DEVID4..0) 00000 NOXOP No operation. 0 == (DEVID4..0) 1xxx0 Note PREX Precharge bank BX4..BX0 of this device (see Figure 12-2). 0 == (DEVID4..0) x10x0 CAL Calibrate (drive) I OL current for this device (see Figure 25-1). 0 == (DEVID4..0) x11x0 CAL / SAM Calibrate (drive) and Sample (update) IOL current for this device (see Figure 25-1). 0 == (DEVID4..0) xxx10 RLXX Move this device into the standby (STBY) power state (see Figure 23-2). 0 == (DEVID4..0) xxxx1 RSRV Reserved, no operation. Note An “x” entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010).

Data Sheet E0039N30 (Ver. 3.0) 15 µµµµPD488588 Figure 5-1 Mapping between COLM Packet and D Packet for WR Command CTM/CFM COL4 COL3 COL2 COL1 COL0 T17 T18 T19 T20 MA7 MA5 MA3 MA1 M=1 MA6 MA4 MA2 MA0 MB7 MB4 MB1 MB6 MB3 MB0 MB5 MB2 CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T0 T4 T8 T12T1 T5 T9 T13T2 T6 T10 T14T3 T7 T11 T15 T16 T20 T24 T28T17 T21 T25 T29T18 T22 T26 T30T19 T23 T27 T31 T32 T36 T40 T44T33 T37 T41 T45T34 T38 T42 T46T35 T39 T43 T47 MSK (a1) retire (a1)WR a1 D (a1) ACT b0ACT a0 Transaction a: WR a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a3 = {Da,Ba} tRTR T19 T20 T21 T22 CTM/CFM DQB8 DQB7 DQB1 DQB0 DB71DB8 DB17 DB26 DB35 DB45 DB53 DB62 DB7 DB16 DB25 DB34 DB44 DB52 DB61 DB70 DB1 DB10 DB19 DB28 DB37 DB46 DB55 DB64 DB0 DB9 DB18 DB27 DB36 DB45 DB54 DB63 COLM Packet PRER a2 DQA8 DQA7 DQA1 DQA0 D Packet MB0 DA71DA8 DA17 DA26 DA35 DA45 DA53 DA62 DA7 DA16 DA25 DA34 DA44 DA52 DA61 DA70 DA1 DA10 DA19 DA28 DA37 DA46 DA55 DA64 DA0 DA9 DA18 DA27 DA36 DA45 DA54 DA63 MA0 MB1 MA1 MB2 MA2 MB3 MA3 MB4 MA4 MB5 MA5 MB6 MA6 MB7 MA7 tCWD Each bit of the MB7..MB0 field controls writing (=1) or no writing (=0) of the indicated DB bits when the M bit of the COLM packet is one. Each bit of the MA7..MA0 field controls writing (=1) or no writing (=0) of the indicated DA bits when the M bit of the COLM packet is one. When M=1, the MA and MB fields control writing of individual data bytes. When M=0, all data bytes are written unconditionally.

Data Sheet E0039N30 (Ver. 3.0) 17 µµµµPD488588 Table 6-1 ROW-to-ROW Packet Interaction - Rules Case # ROPa Da Ba Ra ROPb Db Bb Rb t RRDELAY Example RR1 ACT Da Ba Ra ACT /= Da xxxx x..x t PACKET Figure 10-2 RR2 ACT Da Ba Ra ACT == Da /= {Ba, Ba+1, Ba-1} x..x t RR Figure 10-2 RR3 ACT Da Ba Ra ACT == Da == {Ba+1, Ba-1} x..x t RC - illegal unless PRER to Ba / Ba+1 / Ba-1 Figure 10-1 RR4 ACT Da Ba Ra ACT == Da == {Ba} x..x t RC - illegal unless PRER to Ba / Ba+1 / Ba-1 Figure 10-1 RR5 ACT Da Ba Ra PRER /= Da xxxx x..x t PACKET Figure 10-2 RR6 ACT Da Ba Ra PRER == Da /= {Ba, Ba+1, Ba-1} x..x t PACKET Figure 10-2 RR7 ACT Da Ba Ra PRER == Da == {Ba+1, Ba-1} x..x t RAS Figure 10-1 RR8 ACT Da Ba Ra PRER == Da == {Ba} x..x t RAS Figure 13-1 RR9 PRER Da Ba Ra ACT /= Da xxxx x..x t PACKET Figure 10-3 RR10 PRER Da Ba Ra ACT == Da /= {Ba, Ba+-1, Ba+-2} x..x t PACKET Figure 10-3 RR10a PRER Da Ba Ra ACT == Da == {Ba+2} x..x t PACKET /tRP if Ba+1 is precharged/activated. RR10b PRER Da Ba Ra ACT == Da == {Ba-2} x..x t PACKET /tRP if Ba-1 is precharged/activated. RR11 PRER Da Ba Ra ACT == Da == {Ba+1, Ba-1} x..x t RP Figure 10-1 RR12 PRER Da Ba Ra ACT == Da == {Ba} x..x t RP Figure 10-1 RR13 PRER Da Ba Ra PRER /= Da xxxx x..x t PACKET Figure 10-3 RR14 PRER Da Ba Ra PRER == Da /= {Ba, Ba+1, Ba-1} x..x t PP Figure 10-3 RR15 PRER Da Ba Ra PRER == Da == {Ba+1, Ba-1} x..x t PP Figure 10-3 RR16 PRER Da Ba Ra PRER == Da == {Ba} x..x t PP Figure 10-3

Data Sheet E0039N30 (Ver. 3.0) 24 µµµµPD488588 Figure 12-2 Offsets for Alternate Precharge Mechanisms CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T0 T4 T8 T12T1 T5 T9 T13T2 T6 T10 T14T3 T7 T11 T15 T16 T20 T24 T28T17 T21 T25 T29T18 T22 T26 T30T19 T23 T27 T31 T32 T36 T40 T44T33 T37 T41 T45T34 T38 T42 T46T35 T39 T43 T47 CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T0 T4 T8 T12T1 T5 T9 T13T2 T6 T10 T14T3 T7 T11 T15 T16 T20 T24 T28T17 T21 T25 T29T18 T22 T26 T30T19 T23 T27 T31 T32 T36 T40 T44T33 T37 T41 T45T34 T38 T42 T46T35 T39 T43 T47 CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T0 T4 T8 T12T1 T5 T9 T13T2 T6 T10 T14T3 T7 T11 T15 T16 T20 T24 T28T17 T21 T25 T29T18 T22 T26 T30T19 T23 T27 T31 T32 T36 T40 T44T33 T37 T41 T45T34 T38 T42 T46T35 T39 T43 T47 RD a1 ACT a0 RD a2 Q (a2)Q (a1) ACT b0 MSK (a2)MSK (a1) retire (a1) tOFFP WR a1 D (a2)D (a1) ACT b0ACT a0 Transaction a: RD a0 = {Da,Ba,Ra} a5 = {Da,Ba} COLC Packet: RDA Precharge Offset COLC Packet: WDA Precharge Offset Transaction a: WR a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} a5 = {Da,Ba} COLX Packet: PREX Precharge Offset RD a3 Q (a4)Q (a3) RDA a4 PRER a5 The RDA precharge is equivalent to a PRER command here tOFFP PRER a5 The WRA precharge (triggered by the automatic retire) is equivalent to a PRER command here WRA a2 retire (a2) tRTR a3 = {Da,Ba,Ca3} a4 = {Da,Ba,Ca4} a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} RD a1 ACT a0 RD a2 Q (a2)Q (a1) ACT b0 tOFFP Transaction a: RD a0 = {Da,Ba,Ra} a5 = {Da,Ba} RD a3 Q (a4)Q (a3) PRER a5 The PREX precharge command is equivalent to a PRER command here a3 = {Da,Ba,Ca3} a4 = {Da,Ba,Ca4} a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} RD a4 PREX a5

Data Sheet E0039N30 (Ver. 3.0) 32 µµµµPD488588 19. Control Register Transactions The RDRAM has two CMOS input pins SCK and CMD and two CMOS input/output pins SIO0 and SIO1. These provide serial access to a set of control registers in the RDRAM. These control registers provide configuration information to the controller during the initialization process. They also allow an application to select the appropriate operating mode of the RDRAM. SCK (serial clock) and CMD (command) are driven by the controller to all RDRAMs in parallel. SIO0 and SIO1 are connected (in a daisy chain fashion) from one RDRAM to the next. In normal operation, the data on SIO0 is repeated on SIO1, which connects to SIO0 of the next RDRAM (the data is repeated from SIO1 to SIO0 for a read data packet). The controller connects to SIO0 of the first RDRAM. Write and read transactions are each composed of four packets, as shown in Figure 19-1 and Figure 19-2. Each packet consists of 16 bits, as summarized in Table 20-1 and Table 20-2. The packet bits are sampled on the falling edge of SCK. A transaction begins with a SRQ (Serial Request) packet. This packet is framed with a 11110000 pattern on the CMD input (note that the CMD bits are sampled on both the falling edge and the rising edge of SCK). The SRQ packet contains the SOP3..SOP0 (Serial Opcode) field, which selects the transaction type. The SDEV5..SDEV0 (Serial Device address) selects one of the 32 RDRAMs. If SBC (Serial Broadcast) is set, then all RDRAMs are selected. The SA (Serial Address) packet contains a 12 bit address for selecting a control register. A write transaction has a SD (Serial Data) packet next. This contains 16 bits of data that is written into the selected control register. A SINT (Serial Interval) packet is last, providing some delay for any side-effects to take place. A read transaction has a SINT packet, then a SD packet. This provides delay for the selected RDRAM to access the control register. The SD read data packet travels in the opposite direction (towards the controller) from the other packet types. The SCK cycle time will accommodate the total delay. Figure 19-1 Serial Write (SWR) Transaction to Control Register SRQ - SWR command 1111 00000000...00000000 SRQ - SWR command 0000 SA SA SD SD SINT SINT SCK CMD SIO0 SIO1 T

4 T36T20 T52 T68

Figure 19-2 Serial Read (SRD) Transaction Control Register SRQ - SRD command 1111 00000000...00000000 SRQ - SRD command 0000 SA SA SINT SINT SD SD SCK CMD SIO 0 SIO 1 T4 T36T20 T52 T68 First 3 packets are repeated from SIO0 to SIO1 1111 next transaction addressed RDRAM devices 0/SD15..SD0/0 on SIO0 controller drives 0 on SIO0 non addressed RDRAMs pass 0/SD15..SD0/0 from SIO1 to SIO0

Data Sheet E0039N30 (Ver. 3.0) 33 µµµµPD488588 20. Control Register Packets Table 20-1 summarizes the formats of the four packet types for control register transactions. Table 20-2 summarizes the fields that are used within the packets. Figure 20-1 shows the transaction format for the SETR, CLRR, and SETF commands. These transactions consist of a single SRQ packet, rather than four packets like the SWR and SRD commands. The same framing sequence on the CMD input is used, however. These commands are used during initialization prior to any control register read or write transactions. Table 20-1 Control Register Packet Formats SCK Cycle SIO0 or SIO1 for SRQ SIO0 or SIO1 for SA SIO0 or SIO1 for SINT SIO0 or SIO1 for SD SCK Cycle SIO0 or SIO1 for SRQ SIO0 or SIO1 for SA SIO0 or SIO1 for SINT SIO0 or SIO1 for SD 0 rsrv rsrv 0 SD15 8 SOP1 SA7 0 SD7 1 rsrv rsrv 0 SD14 9 SOP0 SA6 0 SD6 2 rsrv rsrv 0 SD13 10 SBC SA5 0 SD5 3 rsrv rsrv 0 SD12 11 SDEV4 SA4 0 SD4 4 rsrv SA11 0 SD11 12 SDEV3 SA3 0 SD3

5 SDEV5 SA10 0 SD10 13 SDEV2 SA2 0 SD2

6 SOP3 SA9 0 SD9 14 SDEV1 SA1 0 SD1

7 SOP2 SA8 0 SD8 15 SDEV0 SA0 0 SD0

Table 20-2 Field Description for Control Register Packets Field Description rsrv Reserved. Should be driven as “0” by controller. 0010 - SETR. Set Reset bit, all control registers assume their reset values. Note 16 tSCYCLE delay until CLRR command. 0100 - SETF. Set fast (normal) clock mode. 4 t SCYCLE delay until next command. 1011 - CLRR. Clear Reset bit, all control registers retain their reset values. Note 4 tSCYCLE delay until next command. 1111 - NOP. No serial operation. 0011, 0101 – 1010, 1100 – 1110 – RSRV. Reserved encodings. which the transaction is directed. SBC Serial broadcast. When set, RDRAMs ignore {SDEV5..SDEV0} for RDRAM selection. SA11..SA0 Serial address. Selects which control register of the selected RDRAM is read or written. SD15..SD0 Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM. Note The SETR and CLRR commands must always be applied in two successive transactions to RDRAMs; i.e. they may not be used in isolation. This is called “SETR/CLRR Reset ”. Figure 20-1 SETR, CLRR, SETF Transaction SCK CMD SIO0 T20 SRQ packet - SETR/CLRR/SETF 1111 00000000...00000000 SRQ packet - SETR/CLRR/SETF 0000 SIO1 The packet is repeated from SIO0 to SIO1

Data Sheet E0039N30 (Ver. 3.0) 34 µµµµPD488588 21. Initialization Figure 21-1 SIO Pin Reset Sequence SCK CMD SIO0 T16 0000000000000000 00000000...00000000 0000000000000000SIO1 The packet is repeated from SIO0 to SIO1 00001100 Initialization refers to the process that a controller must go through after power is applied to the system or the system is reset. The controller prepares the RDRAM sub-system for normal Channel operation by (primarily) using a sequence of control register transactions on the serial CMOS pins. The following steps outline the sequence seen by the various memory subsystem components (including the RDRAM components) during initialization. This sequence is available in the form of reference code. Contact Rambus Inc. for more information.

1.0 Start Clocks

This step calculates the proper clock frequencies for PClk (controller logic), SynClk (RAC block), RefClk (DRCG component), CTM (RDRAM component), and SCK (SIO block).

2.0 RAC Initialization

This step causes the INIT block to generate a sequence of pulses which resets the RAC, performs RAC maintainance operations, and measures timing intervals in order to ensure clock stability.

3.0 RDRAM Initialization

This stage performs most of the steps needed to initialize the RDRAMs. The rest are performed in stages 5.0, 3.1/3.2 SIO Reset After a delay of t PAUSE from step 1.0, this reset operation is performed before any SIO control register read or write transactions. It clears six registers (TEST34, CCA, CCB, SKIP, TEST78, and TEST79) and places the INIT register into a special state (all bits cleared except SKP and SDEVID fields are set to ones).

3.3 Write TEST77 Register

The TEST77 register must be explicitly written with zeros before any other registers are read or written.

3.4 Write TCYCLE Register

The TCYCLE register is written with the cycle time t CYCLE of the CTM clock (for Channel and RDRAMs) in units of 64ps. The tCYCLE value is determined in stage 1.0.

3.5 Write SDEVID Register

The SDEVID (serial device identification) register of the RDRAM is written with a unique address value so that directed SIO read and write transactions can be performed. This address value increases from 0 to 31 according to the distance an RDRAM is from the ASIC component on the SIO bus (the closest RDRAM is address 0).

Data Sheet E0039N30 (Ver. 3.0) 35 µµµµPD488588

3.6 Write DEVID Register

The DEVID (device identification) register of the RDRAM is written with a unique address value so that directed memory read and write transactions can be performed. This address value increases from 0 to 31. The DEVID value is not necessarily the same as the SDEVID value. RDRAMs are sorted into regions of the same core configuration (number of bank, row, and column address bits and core type).

3.7 Write PDNX, PDNXA Registers

The PDNX and PDNXA registers are written with values that are used to measure the timing intervals connected with an exit from the PDN (powerdown) power state.

3.8 Write NAPX Register

The NAPX register is written with values that are used to measure the timing intervals connected with an exit from the NAP power state.

3.9 Write TPARM Register

The TPARM register is written with values which determine the time interval between a COL packet with a memory read command and the Q packet with the read data on the Channel. The values written set the RDRAM to the minimum value permitted for the system. This will be adjusted later in stage 6.0.

3.10 Write TCDLY1 Register

The TCDLY1 register is written with values which determine the time interval between a COL packet with a memory read command and the Q packet with the read data on the Channel. The values written set the RDRAM to the minimum value permitted for the system. This will be adjusted later in stage 6.0.

3.11 Write TFRM Register

The TFRM register is written with a value that is related to the t RCD parameter for the system. The tRCD parameter is the time interval between a ROW packet with an activate command and the COL packet with a read or write command.

3.12 SETR/CLRR

First write the following registers with the indicated values: TEST78 0004 TEST34 0040 16 Next, the RDRAM is given a SETR command and a CLRR command through the SIO block. This sequence performs a second reset operation on the RDRAMs. Then the TEST34 and TEST78 registers are rewritten with zero, in that order.

3.13 Write CCA and CCB Registers

These registers are written with a value halfway between their minimum and maximum values. This shortens the time needed for the RDRAMs to reach their steady-state current control values in stage 5.0.

3.14 Powerdown Exit

The RDRAM is in the PDN power state at this point. A broadcast PDNExit command is performed by the SIO block to place the RDRAMs in the RLX (relax) power state in which they are ready to receive ROW packets.

3.15 SETF

The RDRAM is given a SETF command through the SIO block. One of the operations performed by this step is to generate a value for the AS (autoskip) bit in the SKIP register and fix the RDRAM to a particular read domain.

Data Sheet E0039N30 (Ver. 3.0) 36 µµµµPD488588

4.0 Controller Configuration

This stage initializes the controller block. Each step of this stage will set a field of the ConfigRMC[63:0] bus to the appropriate value. Other controller implementations will have similar initialization requirements, and this stage may be used as a guide.

4.1 Initial Read Data Offset

The ConfigRMC bus is written with a value which determines the time interval between a COL packet with a memory read command and the Q packet with the read data on the Channel. The value written sets RMC.d1 to the minimum value permitted for the system. This will be adjusted later in stage 6.0.

4.2 Configure Row/Column Timing

This step determines the values of the t RAS,MIN , tRP,MIN , tRC,MIN , tRCD,MIN , tRR,MIN , and tPP,MIN RDRAM timing parameters that are present in the system. The ConfigRMC bus is written with values that will be compatible with all RDRAM devices that are present.

4.3 Set Refresh Interval

This step determines the values of the t REF,MAX RDRAM timing parameter that are present in the system. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present.

4.4 Set Current Control Interval

This step determines the values of the t CCTRL,MAX RDRAM timing parameter that are present in the system. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present.

4.5 Set Slew Rate Control Interval

This step determines the values of the t TEMP,MAX RDRAM timing parameter that are present in the system. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present.

4.6 Set Bank/Row/Col Address Bits

This step determines the number of RDRAM bank, row, and column address bits that are present in the system. It also determines the RDRAM core types (independent, doubled, or split) that are present. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present.

5.0 RDRAM Current Control

This step causes the INIT block to generate a sequence of pulses which performs RDRAM maintenance operations.

6.0 RDRAM Core, Read Domain Initialization

This stage completes the RDRAM initialization

6.1 RDRAM Core Initialization

A sequence of 192 memory refresh transactions is performed in order to place the cores of all RDRAMs into the proper operating state.

6.2 RDRAM Read Domain Initialization

A memory write and memory read transaction is performed to the RDRAM to determine which read domain the RDRAM occupies. The programmed delay of the RDRAM is then adjusted so the total RDRAM read delay (propagation delay plus programmed delay) is constant. The TPARM and TCDLY1 registers of the RDRAM is rewritten with the appropriate read delay values. The ConfigRMC bus is also rewritten with an updated value.

Data Sheet E0039N30 (Ver. 3.0) 37 µµµµPD488588

7.0 Other RDRAM Register Fields

This stage rewrites the INIT register with the final values of the LSR, NSR, and PSR fields. In essence, the controller must read all the read-only configuration registers of all RDRAMs (or it must read the SPD device present on each RIMM), it must process this information, and then it must write all the read-write registers to place the RDRAMs into the proper operating mode. Initialization Note : 1. During the initialization process, it is necessary for the controller to perform 128 current control operations (3xCAL, 1xCAL/SAM) and one temperature calibrate operation (TCEN/TCAL) after reset or after powerdown (PDN) exit. 2. The behavior of µPD488588 at initialization is as follows. It is distinguished by the "S28IECO" bit in the SPD. S28IECO=1: Upon powerup, the device enters PDN state. The serial operations SETR, CLRR, and SETF require a SDEVID match. See the document detailing the reference initialization procedure for more information on how to handle this in a system. 3. After the step of equalizing the total read delay of the RDRAM has been completed (i.e. after the TCDLY0 and TCDLY1 fields have been written for the final time), a single final memory read transaction should be made to the RDRAM in order to ensure that the output pipeline stages have been cleared. 4. The SETF command (in the serial SRQ packet) should only be issued once during the Initialization process, as should the SETR and CLRR commands. 5. The CLRR command (in the serial SRQ packet) leaves some of the contents of the memory core in an indeterminate state.

Data Sheet E0039N30 (Ver. 3.0) 38 µµµµPD488588 22. Control Register Summary Table 22-1 summarizes the RDRAM control registers. Detail is provided for each control register in Figure 22-1. Read-only bits which are shaded gray are unused and return zero. Read-write bits which are shaded gray are reserved and should always be written with zero. The RIMM SPD Application Note (DL-0054) of Rambus Inc. describes additional read-only configuration registers which are present on Direct RIMMs. The state of the register fields are potentially affected by the IO Reset operation or the SETR/CLRR operation. This is indicated in the text accompanying each register diagram. Table 22-1 Control Register Summary (1/2) SA11..SA0 Register Field read-write/ read-only Description 02116 INIT SDEVID read-write, 6 bits Serial device ID. Device address for control register read/write. PSX read-write, 1 bit Power select exit. PDN/NAP exit with device addr on DQA5..0. SRP read-write, 1 bit SIO repeater. Used to initialize RDRAM. NSR read-write, 1 bit NAP self-refresh. Enables self-refresh in NAP mode. PSR read-write, 1 bit PDN self-refresh. Enables self-refresh in PDN mode. LSR read-write, 1 bit Low power self-refresh. Enables low power self-refresh. TEN read-write, 1 bit Temperature sensing enable. TSQ read-write, 1 bit Temperature sensing output. DIS read-write, 1 bit RDRAM disable. IDM read-write, 1 bit Interleaved Device Mode enable. 02216 TEST34 TEST34 read-write, 16 bits Test register. Do not read or write after SIO reset. 02316 CNFGA REFBIT read-only, 3 bits Refresh bank bits. Used for multi-bank refresh. DBL read-only, 1 bit Double. Specifies doubled-bank architecture. MVER read-only, 6 bits Manufacturer version. Manufacturer identification number. PVER read-only, 6 bits Protocol version. Specifies version of Direct protocol supported. 02416 CNFGB BYT read-only, 1 bit Byte. Specifies an 8-bit or 9-bit byte size. DEVTYP read-only, 3 bits Device type. Device can be RDRAM or some other device category. SPT read-only, 1 bit Split-core. Each core half is an individual dependent core. CORG read-only, 6 bits Core organization. Bank, row, column address field sizes. SVER read-only, 6 bits Stepping version. Mask version number. 04016 DEVID DEVID read-write, 5 bits Device ID. Device address for memory read/write. 04116 REFB REFB read-write, 4 bits Refresh bank. Next bank to be refreshed by self-refresh. 04216 REFR REFR read-write, 9 bits Refresh row. Next row to be refreshed by REFA, self-refresh. 04316 CCA CCA read-write, 7 bits Current control A. Controls I OL output current for DQA. ASYMA read-write, 2 bits Asymmetry control. Controls asymmetry of V OL /VOH swing for DQA. 04416 CCB CCB read-write, 7 bits Current control B. Controls I OL output current for DQB. ASYMB read-write, 2 bits Asymmetry control. Controls asymmetry of V OL /VOH swing for DQB. 04516 NAPX NAPXA read-write, 5 bits NAP exit. Specifies length of NAP exit phase A. NAPX read-write, 5 bits NAP exit. Specifies length of NAP exit phase A + phase B. DQS read-write, 1 bit DQ select. Selects CMD framing for NAP/PDN exit. 04616 PDNXA PDNXA read-write, 13 bits PDN exit. Specifies length of PDN exit phase A.

Data Sheet E0039N30 (Ver. 3.0) 39 µµµµPD488588 Table 22-1 Control Register Summary (2/2) SA11..SA0 Register Field read-write/ read-only Description 04716 PDNX PDNX read-write, 13 bits PDN exit. Specifies length of PDN exit phase A + phase B. 04816 TPARM TCAS read-write, 2 bits t CAS-C core parameter. Determines tOFFP datasheet parameter. TCLS read-write, 2 bits t CLS-C core parameter. Determines tCAC and tOFFP parameters. TCDLY0 read-write, 3 bits t CDLY0-C core parameter. Programmable delay for read data. 04916 TFRM TFRM read-write, 4 bits t FRM-C core parameter. Determines ROW - COL packet framing interval. 04a16 TCDLY1 TCDLY1 read-write, 3 bits tCDLY-1 core parameter. Programmable delay for read data. 04c16 TCYCLE TCYCLE read-write, 14 bits t CYCLE datasheet parameter. Specifies cycle time in 64ps units. 04b16 SKIP AS read-only, 1 bit Autoskip value established by the SETF command. MSE read-write, 1 bit Manual skip enable. Allows the MS value to override the AS value. MS read-write, 1 bit Manual skip value. 04d16- TEST77 TEST77 read-write, 16 bits Test register. Write with zero after SIO reset. 04e16- TEST78 TEST78 read-write, 16 bits Test register. Do not read or write after SIO reset. 04f16- TEST79 TEST79 read-write, 16 bits Test register. Do not read or write after SIO reset. 08016-Off16 reserved reserved vendor-specific Vendor-specific test registers. Do not read or write after SIO reset.

Data Sheet E0039N30 (Ver. 3.0) 40 µµµµPD488588 Figure 22-1 Control Registers (1/7) Control Register : INIT Address : 02116 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDM SDE VID5 DIS TSQ TEN LSR PSR NSR SRP PSX 0 SDEVID4..0 Read/write register. Reset values are undefined except as affected by SIO Reset as noted below. SETR/CLRR Reset does not affect this register. Field Description Reset value read/write transactions. This determines which RDRAM is selected for the register read or write operation. 3f16 DIS RDRAM disable. DIS=1 causes RDRAM to ignore NAP/PDN exit sequence, DIS=0 permit normal operation. This mechanism disables an RDRAM. TSQ Temperature Sensing Output. TSQ=1 when a temperature trip point has been exceeded, TSQ=0 when it has not. TSQ is available during a current control operation (see Figure 25-1). TEN Temperature Sensing Enable. TEN=1 enables temperature sensing circuitry, permitting the TSQ bit to be read to determine if a thermal trip point has been exceeded. LSR Low Power Self-Refresh. This function is not supported. LSR value must be 0. 0 PSR PDN Self-Refresh. PSR=1 enables self-refresh in PDN mode. PSR can’t be set while in PDN mode. 0 NSR NAP Self-Refresh. NSR=1 enables self-refresh in NAP mode. NSR can’t be set while in NAP mode. 0 SRP SIO Repeater. Controls value on SIO1; SIO1=SIO0 if SRP=1, SIO1=1 if SRP=0. 1 PSX Power Exit Select. PDN and NAP are exited with (=0) or without (=1) a device address on the DQA5..0 pins. compared to DEVID4..0 to select a device. Control Register : CNFGA Address : 02316 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read only register. Field Description PVER5..0 Protocol Version. Specifies the Direct Protocol version used by this device: 0 – Reserved 1 – Version 1 protocol. 2 – Version 1 plus Interleaved Device Mode. 3 to 63 – Reserved MVER5..0 Manufacturer Version. Specifies the manufacturer identification number. DBL Doubled-Bank. DBL=1 means the device uses a doubled-bank architecture with adjacent-bank dependency. DBL=0 means no dependency. REFBIT2..0 Refresh Bank Bits. Specifies the number of bank address bits used by REFA and REFP commands. Permits multi-bank refresh in future RDRAMs. Caution In RDRAMs with protocol version 1 PVER[5:0] =000001, the range of the PDNX field (PDNX[2:0] in the PDNX register) may not be large enough to specify the location of the restricted interval in Figure 23-3. In this case, the effective t S4 parameter must increase and no row or column packets may overlap the restricted interval. See Figure 23-3 and Timing conditions table.

Data Sheet E0039N30 (Ver. 3.0) 41 µµµµPD488588 Figure 22-1 Control Registers (2/7) Control Register : CNFGB Address : 02416 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read only register. Field Description SVER5..0 Stepping version. Specifies the mask version number of this device. CORG4..0 Core organization. This field specifies the number of bank (5 bits), row (9 bits), and column (7 bits) address bits. SPT Split-core. SPT=1 means the core is split, SPT=0 means it is not. DEVTYP2..0 Device type. DEVTYP=000 means that this device is an RDRAM. BYT Byte width. B=1 means the device reads and writes 9-bit memory bytes.B=0 means 8 bits. Control Register : TEST34 Address : 02216 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/write register. Reset values of TEST34 is zero (from SIO Reset). This register are used for testing purposes. It must not be read or written after SIO Reset. Control Register : DEVID Address : 04016 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 DEVID4..0 Read/write register. Reset value is undefined. Field Description memory read or write transactions. This determines which RDRAM is selected for the memory read or write transaction.

Data Sheet E0039N30 (Ver. 3.0) 42 µµµµPD488588 Figure 22-1 Control Registers (3/7) Control Register : REFB Address : 04116 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 REFB4..0 Read/write register. Field Description Reset value is incremented after each self-refresh activate and precharge operation pair. Control Register : REFR Address : 04216 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 REFR8..0 Read/write register. Field Description Reset value incremented when REFB4..0=11111 for self-refresh. Control Register : CCA Address : 04316 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 ASYM A0 CCA6..0 Read/write register. Field Description Reset value ASYMA0 control the asymmetry of the VOL /VOH voltage swing about the VREF reference voltage for the DQA8..0 pins. ASYMA0 ODF 0 0.00 1 0.12 ASYMA0 Where ODF is the Over Drive Factor (the extra IOL current sunk by an RSL output when ASYMA0 is set). Control Register : CCB Address : 04416 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 ASYM B0 CCB6..0 Read/write register. Field Description Reset value ASYMB0 control the asymmetry of the VOL /VOH voltage swing about the VREF reference voltage for the DQB8..0 pins. ASYMB0 ODF 0 0.00 1 0.12 ASYMB0 Where ODF is the Over Drive Factor (the extra IOL current sunk by an RSL output when ASYMB0 is set).

Data Sheet E0039N30 (Ver. 3.0) 43 µµµµPD488588 Figure 22-1 Control Registers (4/7) Control Register : NAPX Address : 04516 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 DQS NAPX4..0 NAPXA4..0 Read/write register. Reset value is undefined. Note tSCYCLE is tCYCLE1 (SCK cycle time). Field Description DQS DQ Select. This field specifies the number of SCK cycles (0 ≥ 0.5 cycles, 1 ≥ 1.5 cycles) between the CMD pin framing sequence and the device selection on DQ5..0. see Figure 23-4. This field must be written with a ”1” for this RDRAM. NAPX4..0 Nap Exit Phase A plus B. This field specifies the number of SCK cycles during the first plus second phases for exiting NAP mode. It must satisfy: NAPX•t SCYCLE ≥ NAPXA •tSCYCLE +tNAPXB ,MAX Do not set this field to zero. NAPXA4..0 Nap Exit Phase A. This field specifies the number of SCK cycles during the first phase for exiting NAP mode. It must satisfy: NAPXA•t SCYCLE ≥ tNAPXA ,MAX Do not set this field to zero. Control Register : PDNXA Address : 04616 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 PDNXA12..0 Read/write register. Reset value is undefined. Field Description PDNXA4..0 PDN Exit Phase A. This field specifies the number of (64•SCK cycle) units during the first phase for exiting PDN mode. It must satisfy: PDNXA•64•t SCYCLE ≥ tPDNXA ,MAX Do not set this field to zero. Note – only PDNXA4..0 are implemented. Note – t SCYCLE is tCYCLE1 (SCK cycle time). Control Register : PDNX Address : 04716 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 PDNX12..0 Read/write register. Reset value is undefined. Field Description PDNX2..0 PDN Exit Phase A puls B. This field specifies the number of (256•SCK cycle) units during the first plus second phases for exiting PDN mode. It should satisfy: PDNX•256•t SCYCLE ≥ PDNXA •64•tSCYCLE +tPDNXB ,MAX It this equation can’t be satisfied, then the maximum PDNX value should be written, and the tS4 / tH4 timing window will be modified (see Figure 23-4). Do not set this field to zero. Note – only PDNX2..0 are implemented. Note – t SCYCLE is tCYCLE1 (SCK cycle time).

Data Sheet E0039N30 (Ver. 3.0) 44 µµµµPD488588 Figure 22-1 Control Registers (5/7) Control Register : TPARM Address : 04816 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 TCDLY0 TCLS TCAL Read/write register. Reset value is undefined. Field Description TCDLY0 Specifies the tCDLY0-C core parameter in tCYCLE units. This adds a programmable delay to Q (read data) packets, permitting round trip read delay to all device to be equalized. This field may be written with the values “010” (2•tCYCLE ) through “101” (5•tCYCLE ). TCLS1..0 Specifies the tCLS-C core parameter in tCYCLE units. Should be “10” (2•tCYCLE ). TCAS1..0 Specifies the tCAS-C core parameter in tCYCLE units. This should be “10” (2•tCYCLE ). The equations relating the core parameters to the datasheet parameters follow: t CAS-C =2•tC Y C L E t CLS-C =2•tC Y C L E t CPS-C =1•tCYCLE Not programmable t OFFP =tCPS-C + tCAS-C + tCLS-C - 1•tCYCLE =4 •tCYCLE t RCD =tRCD-C + 1•tCYCLE – tCLS-C =t RCD-C - 1•tCYCLE t CAC =3•tCYCLE + tCLS-C + tCDLY0-C + tCDLY1-C (see table below programming ranges) TCDLY0 tCDLY0-C TCDLY1 tCDLY1-C tCAC @t CYCLE =3.30 ns tCAC @t CYCLE =2.50 ns 010 2 •tCYCLE 000 0 •tCYCLE 7•tCYCLE not allowed 011 3 •tCYCLE 000 0 •tCYCLE 8•tCYCLE 8•tCYCLE 011 3 •tCYCLE 001 1 •tCYCLE 9•tCYCLE 9•tCYCLE 011 3 •tCYCLE 010 2 •tCYCLE 10•tCYCLE 10•tCYCLE 100 4 •tCYCLE 010 2 •tCYCLE 11•tCYCLE 11•tCYCLE 101 5 •tCYCLE 010 2 •tCYCLE 12•tCYCLE 12•tCYCLE Control Register : TFRM Address : 04916 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 TFRM3..0 Read/write register. Reset value is undefined. Field Description TFRM3..0 Specifies the position of the framing point in tCYCLE units. This value must be greater than or equal to the tFRM,MIN parameter. This is the minimum offset between a ROW packet (which places a device at ATTN) and the first COL packet (directed to that device) which must be framed. This field may be written with the value “0111” (7•t CYCLE ) through “1010” (10•tCYCLE ). TFRM is usually set to the value which matches the largest tRCD,MIN parameter (modulo 4•tCYCLE ) that is present in an RDRAM in the memory system. Thus, if an RDRAM with tRCD,MIN =11•tCYCLE were present, then TFRM would be programmed to 7•tCYCLE .

Data Sheet E0039N30 (Ver. 3.0) 45 µµµµPD488588 Figure 22-1 Control Registers (6/7) Control Register : TCDLY1 Address : 04a16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCDLY1 Read/write register. Reset value is undefined. Field Description TCDLY1 Specifies the value of the tCDLY1-C core parameter in tCYCLE units. This adds a programmable delay to Q (read data) packets, permitting round trip read to delay all devices to be equalized. This field may be written with the values “000” (0•tCYCLE ) through “010” (2•tCYCLE ). Refer to TPARM Register for more details. Control Register : SKIP Address : 04b16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 AS MSE MS 0 0 0 0 0 0 0 0 0 0 Read/write register (except AS field). Reset value is zero (SIO Reset). Field Description MS Manual skip (MS must be 1 when MSE=1). > During initialization, the RDRAMs at the furthest point in the fifth read domain may have selected the AS=0 value, placing them at the closest point in a sixth read domain. Setting the MSE/MS fields to 1/1 overrides the autoskip value and returns them to the furthest point of the fifth read domain. MSE Manual skip enable (0=auto, 1=manual ). AS Autoskip. Read-only value determined by autoskip circuit and stored when SETF serial command is received by RDRAM during initialization. In Figure34-1, AS=1 corresponds to the early Q(a1) packet and AS=0 to the Q(a1) packet one t CYCLE later for the four uncertain cases. Control Register : TCYCLE Address : 04c16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 TCYCLE13..0 Read/write register. Reset value is undefined. Field Description TCYCLE13..0 Specifies the value of the tCYCLE datasheet parameter in 64ps units. For the tCYCLE,MIN of 2.50 ns (2500ps), this field should be written with the value “0002716” (39•64ps).

Data Sheet E0039N30 (Ver. 3.0) 46 µµµµPD488588 Figure 22-1 Control Registers (7/7) Control Register : TEST77 Address : 04d16 Control Register : TEST78 Address : 04e16 Control Register : TEST79 Address : 04f16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/write register. Field Description Reset value TEST77 It must be written with zero after SIO reset. These registers must only be used for testing purposes.  TEST78 Do not read or written after SIO reset. 0 TEST79 Do not read or written after SIO reset. 0

Data Sheet E0039N30 (Ver. 3.0) 47 µµµµPD488588 23. Power State Management Table 23-1 summarizes the power states available to a Direct RDRAM. In general, the lowest power states have the longest operational latencies. For example, the relative power levels of PDN state and STBY state have a ratio of about 1:110, and the relative access latencies to get read data have a ratio of about 250:1. PDN state is the lowest power state available. The information in the RDRAM core is usually maintained with self- refresh; an internal timer automatically refreshes all rows of all banks. PDN has a relatively long exit latency because the TCLK/RCLK block must resynchronize itself to the external clock signal. NAP state is another low-power state in which either self-refresh or REFA-refresh are used to maintain the core. See 24. Refresh for a description of the two refresh mechanisms. NAP has a shorter exit latency than PDN because the TCLK/RCLK block maintains its synchronization state relative to the external clock signal at the time of NAP entry. This imposes a limit (t NLIMIT) on how long an RDRAM may remain in NAP state before briefly returning to STBY or ATTN to update this synchronization state. Table 23-1 Power State Summary Power State Description Blocks consuming power Power state Description Blocks consuming power PDN Powerdown state. Self-refresh NAP Nap state. Similar to PDN except lower wake-up latency. Self-refresh or REFA-refresh TCLK/RCLK-Nap STBY Standby state. Ready for ROW packets. REFA-refresh TCLK/RCLK ROW demux receiver ATTN Attention state. Ready for ROW and COL packets. REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver ATTNR Attention read state. Ready for ROW and COL packets. Sending Q (read data) packets. REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver DQ mux transmitter Core power ATTNW Attention write state. Ready for ROW and COL packets. Ready for D (write data) packets. REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver DQ demux receiver Core power

Data Sheet E0039N30 (Ver. 3.0) 52 µµµµPD488588 24. Refresh RDRAMs, like any other DRAM technology, use volatile storage cells which must be periodically refreshed. This is accomplished with the REFA command. Figure 24-1 shows an example of this. The REFA command in the transaction is typically a broadcast command (DR4T and DR4F are both set in the ROWR packet), so that in all devices bank number Ba is activated with row number REFR, where REFR is a control register in the RDRAM. When the command is broadcast and ATTN is set, the power state of the RDRAMs (ATTN or STBY) will remain unchanged. The controller increments the bank address Ba for the next REFA command. When Ba is equal to its maximum value, the RDRAM automatically increments REFR for the next REFA command. On average, these REFA commands are sent once every t REF / 2 BBIT+RBIT (where BBIT are the number of bank address bits and RBIT are the number of row address bits) so that each row of each bank is refreshed once every tREF interval. The REFA command is equivalent to an ACT command, in terms of the way that it interacts with other packets (see Table 6-1). In the example, an ACT command is sent after t RR to address b0, a different (non-adjacent) bank than the REFA command. A second ACT command can be sent after a time t RC to address c0, the same bank (or an adjacent bank) as the REFA command. Note that a broadcast REFP command is issued a time t RAS after the initial REFA command in order to precharge the refreshed bank in all RDRAMs. After a bank is given a REFA command, no other core operations(activate or precharge) should be issued to it until it receives a REFP. It is also possible to interleave refresh transactions (not shown). In the figure, the ACT b0 command would be replaced by a REFA b0 command. The b0 address would be broadcast to all devices, and would be {Broadcast, Ba+2,REFR}. Note that the bank address should skip by two to avoid adjacent bank interference. A possible bank incrementing pattern would be: {12, 10, 5, 3, 0, 14, 9, 7, 4, 2, 13, 11, 8, 6, 1, 15, 28, 26, 21, 19, 16, 30, 25, 23, 20, 18, 29, 27, 24, 22, 17, 31}. Every time bank 31 is reached, a REFA command would automatically increment the REFR register. A second refresh mechanism is available for use in PDN and NAP power states. This mechanism is called self- refresh mode. When the PDN power state is entered, or when NAP power state is entered with the NSR control register bit set, then self-refresh is automatically started for the RDRAM. Self-refresh uses an internal time base reference in the RDRAM. This causes an activate and precharge to be carried out once in every t REF / 2 BBIT+RBIT interval. The REFB and REFR control registers are used to keep track of the bank and row being refreshed. Before a controller places an RDRAM into self-refresh mode, it should perform REFA/REFP refreshes until the bank address is equal to the maximum value. This ensures that no rows are skipped. Likewise, when a controller returns an RDRAM to REFA/REFP refresh, it should start with the minimum bank address value (zero). Figure 24-2 illustrates the requirement imposed by the t BURST parameter. After PDN or NAP (when self-refresh is enabled) power states are exited, the controller must refresh all banks of the RDRAM once during the interval tBURST after the restricted interval on the ROW and COL buses. This will ensure that regardless of the state of self-refresh during PDN or NAP, the t REF, MAX parameter is met for all banks. During the tBURST interval, the banks may be refreshed in a single burst, or they may be scattered throughout the interval. Note that the first and last banks to be refreshed in the t BURST interval are numbers 12 and 31, in order to match the example refresh sequence.

Data Sheet E0039N30 (Ver. 3.0) 55 µµµµPD488588 26. Electrical Conditions Electrical Conditions Symbol Parameter and Conditions MIN. MAX. Unit Tj Junction temperature under bias  100 °C VDD, VDDa Supply voltage 2.50 – 0.13 2.50 + 0.13 V VDD ,N ,VDDa ,N Supply voltage droop (DC) during NAP interval (tNLIMT ) — 2.0 % VDD ,N ,VDDa ,N Supply voltage ripple (AC) during NAP interval (tNLIMT ) –2.0 +2.0 % VTERM Termination voltage 1.80 – 0.1 1.80 + 0.1 V VREF Reference voltage 1.40 – 0.2 1.40 + 0.2 V VDIL RSL data input - low voltage V REF – 0.5 V REF – 0.2 V VDIH RSL data input - high voltage V REF + 0.2 V REF + 0.5 V VDIS RSL data input swing : V DIS = VDIH – VDIL 0.4 1.0 V ADI RSL data asymmetry : A DI = [(VDIH – VREF ) + (VDIL – VREF )] / VDIS 0 –20 % VX RSL clock input - crossing point of true and complement signals 1.3 1.8 V VCM RSL clock input - common mode V CM = (VCIH + VCIL ) / 2 1.4 1.7 V VCIS, CTM RSL clock input swing : V CIS = VCIH – VCIL (CTM, CTMN pins). 0.35 1.00 V VCIS, CFM RSL clock input swing : V CIS = VCIH – VCIL (CFM, CFMN pins). 0.225 1.00 V VIL, CMOS CMOS input low voltage – 0.3 + (V CMOS / 2– 0.25) V VIH, CMOS CMOS input high voltage V CMOS / 2+0.25 V CMOS + 0.3 V

Data Sheet E0039N30 (Ver. 3.0) 56 µµµµPD488588 27. Timing Conditions Timing Conditions Symbol Parameter MIN. MAX. Unit Figures tCYCLE CTM and CFM cycle times -C60 3.33 3.83 ns Figure 30-1 -C71 2.81 3.83 -C80 2.50 3.83 tCR , tCF CTM and CFM input rise and fall times 0.2 0.5 ns Figure 30-1 tCH , tCL CTM and CFM high and low times 40% 60% t CYCLE Figure 30-1 tTR CTM-CFM differential (MSE/MS=0/0) 0.0 1.0 t CYCLE Figure 22-1 (MSE/MS=1/1) Note1 0.9 1.0 Figure 30-1 tDCW Domain crossing window –0.1 +0.1 t CYCLE Figure 35-1 tDR , tDF DQA/DQB/ROW/COL input rise/fall times 0.2 0.65 ns Figure 31-1 tS, tH DQA/DQB/ROW/COL-to-CFM t CYCLE =2.50ns 0.200 Note4 — ns Figure 31-1 setup/hold time t CYCLE =2.81ns 0.240 Note3,4 t CYCLE =3.33ns 0.275 Note2,4 tDR1 , tDF1 SIO0, SIO1 input rise and fall times — 5.0 ns Figure 33-1 tDR2, tDF2 CMD,SCK input rise and fall times — 2.0 ns Figure 33-1 tCYCLE1 SCK cycle time - Serial control register transactions 1, 000 — ns Figure 33-1 SCK cycle time - Power transitions 10 — ns Figure 33-1 tCH1 , tCL1 SCK high and low times 4.25 — ns Figure 33-1 tS1 CMD setup time to SCK rising or falling edge Note5 1.25 — ns Figure 33-1 tH1 CMD hold time to SCK rising or falling edge Note5 1 — ns Figure 33-1 tS2 SIO0 setup time to SCK falling edge 40 — ns Figure 33-1 tH2 SIO0 hold time to SCK falling edge 40 — ns Figure 33-1 tS3 PDEV setup time on DQA5..0 to SCK rising edge 0 — ns Figure 23-4, 33-2 tH3 PDEV hold time on DQA5..0 to SCK rising edge 5.5 — ns Figure 23-4, 33-2 tS4 ROW2..0, COL4..0 setup time for quiet window Note6 –1 — t CYCLE Figure 23-4 tH4 ROW2..0, COL4..0 hold time for quiet window 5 — t CYCLE Figure 23-4 VIL, CMOS CMOS input low voltage - over / undershoot voltage duration is less than or equal to 5 ns –0.7 +(V CMOS /2–0.6) V VIH, CMOS CMOS input high voltage - over / undershoot voltage duration is less than or equal to 5ns VCMOS /2 + 0.6 V CMOS + 0.7 V tNPQ Quiet on ROW / COL bits during NAP / PDN entry 4 — t CYCLE Figure 23-3 tREADTOCC Offset between read data and CC packets (same device) 12 — t CYCLE Figure 25-1 tCCSAMTOREAD Offset between CC packet and read data (same device) 8 — t CYCLE Figure 25-1 tCE CTM/CFM stable before NAP/PDN exit 2 — t CYCLE Figure 23-4 tCD CTM/CFM stable after NAP/PDN entry 100 — t CYCLE Figure 23-3 tFRM ROW packet to COL packet ATTN framing delay 7 — t CYCLE Figure 23-2 tNLIMIT Maximum time in NAP mode — 10 µs Figure 23-1 tREF Refresh interval — 32 ms Figure 24-1 tCCTRL Current control interval 34 t CYCLE 100 ms — Figure 25-1 tTEMP Temperature control interval — 100 ms Figure 25-2 tTCEN TCE command to TCAL command 150 — t CYCLE Figure 25-2 tTCAL TCAL command to quiet window 2 2 t CYCLE Figure 25-2 tTCQUIET Quiet window (no read data) 140 — t CYCLE Figure 25-2 tPAUSE RDRAM delay (no RSL operations allowed) — 200 µs Figure 22-1 tBURST Interval after PDN or NAP (with self-refresh) exit in which all banks of the RDRAM must be refreshed at least once. — 200 µs Figure 24-2

Data Sheet E0039N30 (Ver. 3.0) 57 µµµµPD488588 Notes 1. MSE/MS are fields of the SKIP register. For this combination (skip override) the t DCW parameter range is effectively 0.0 to 0.0. 2. This parameter also applies to a -C80 or -C71 part when operated with t CYCLE = 3.33 ns. 3. This parameter also applies to a -C80 part when operated with t CYCLE = 2.81ns. 4. t S,MIN and tH,MIN for other tCYCLE values can be interpolated between or extrapolated from the timings at the 3 specified tCYCLE values. 6. Effective hold becomes t H4’=tH4 + [PDNXA • 64 • tSCYCLE + tPDNXB,MAX ] − [PDNX • 256 • tSCYCLE ] if [PDNX • 256 • tSCYCLE ] < [PDNXA • 64 • tSCYCLE + tPDNXB,MAX ]. See Figure 23-4.

Data Sheet E0039N30 (Ver. 3.0) 58 µµµµPD488588 28. Electrical Characteristics

Electrical Characteristics

Symbol Parameter and Conditions MIN. MAX. Unit Θ JC Junction-to-Case thermal resistance — 0.5 °C/Watt IREF V REF current @ VREF,MAX –10 +10 µA IOH RSL output high current @ (0≤VOUT ≤VDD ) –10 +10 µA IALL RSL IOL current @ VOL =0.9 V, VDD,MIN , Tj,MAX Note 30 90 mA ∆IOL RSL I OL current resolution step — 2.0 mA rOUT Dynamic output impedance 150 — Ω II,CMOS CMOS input leakage current @ (0 ≤ VI,CMOS ≤ VCMOS ) –10.0 +10.0 µA VOL,CMOS CMOS output low voltage @ IOL,CMOS = 1.0 mA — 0.3 V VOH,CMOS CMOS output high voltage @ IOH,CMOS = – 0.25 mA V CMOS – 0.3 — V Note This measurement is made in manual current control mode; i.e. with all output device legs sinking current. 29. Timing Characteristics Timing Characteristics Symbol Parameter MIN. MAX. Unit Figure(s) tQ CTM-to-DQA/DQB output time t CYCLE = 2.50 ns –0.260 Note3 +0.260 Note3 ns Figure 32-1 t CYCLE = 2.81 ns –0.300 Note2,3 +0.300 Note2,3 t CYCLE = 3.33 ns –0.350 Note1,3 +0.350 Note1,3 tQR , tQF DQA/DQB output rise and fall times 0.2 0.45 ns Figure 32-1 tQ1 SCK-to-SIO0 delay @ CLOAD,MAX = 20 pF (SD read packet) — 10 ns Figure 34-1 tHR SCK(pos)-to-SIO0 delay @ C LOAD,MAX = 20pF (SD read data hold) 2 — ns Figure 34-1 tQR1 , tQF1 SIO OUT rise/fall @ C LOAD,MAX = 20 pF — 5 ns Figure 34-1 tPROP1 SIO0-to-SIO1 or SIO1-to-SIO0 delay @ C LOAD,MAX = 20 pF — 10 ns Figure 34-1 tNAPXA NAP exit delay - phase A — 50 ns Figure 23-4 tNAPXB NAP exit delay - phase B — 40 ns Figure 23-4 tPDNXA PDN exit delay - phase A — 4 µs Figure 23-4 tPDNXB PDN exit delay - phase B — 9,000 t CYCLE Figure 23-4 tAS ATTN-to-STBY power state delay — 1 t CYCLE Figure 23-2 tSA STBY-to-ATTN power state delay — 0 t CYCLE Figure 23-2 tASN ATTN/STBY-to-NAP power state delay — 8 t CYCLE Figure 23-3 tASP ATTN/STBY-to-PDN power state delay — 8 t CYCLE Figure 23-3 Notes 1. This parameter also applies to a -C80 or -C71 part when operated with t CYCLE =3.33 ns. 2. This parameter also applies to a -C80 part when operated with t CYCLE =2.81 ns. 3. t Q,MIN and tQ,MAX for other tCYCLE values can be interpolated between or extrapolated from the timings at the 3 specified tCYCLE values.

Data Sheet E0039N30 (Ver. 3.0) 63 µµµµPD488588 The SCK clock is also used for sampling data on RSL input in one situation. Figure23-4 shows the PDN and NAP exit sequences. If the PSX field of the INIT register is one (Figure 22-1 control registers (1/7) “INIT Register”), then the PDN and NAP exit sequences are broadcast; i.e. all RDRAMs that are in PDN or NAP will perform the exit sequence. If the PSX field of the INIT register is zero, then the PDN and NAP exit sequences are directed; i.e. only one RDRAM that is in PDN or NAP will perform the exit sequence. The address of that RDRAM is specified on the DQA[5:0] bus in the set hold window t S3/tH3 around the rising edge of SCK. This is shown Figure 33-2. The SCK timing point is measured at the 50 % level, and the DQA [5:0] bus signals are measured at the V REF level. Figure 33-2 CMOS Timing - Device Address for NAP or PDN Exit V IH,CMOS 80% 50% 20% V IL,CMOS SCK PDEV V DIH 80% 20% VDIL DQA[5:0] V tS3 tH3 REF

Data Sheet E0039N30 (Ver. 3.0) 66 µµµµPD488588 36. Timing Parameters Timing Parameters Summary Para- Description MIN. MAX. Units Figures meter -C80 -C71 -C60 -45 -45 -53 tRC Row Cycle time of RDRAM banks - the interval between ROWA packets with ACT commands to the same bank. 28 28 28 — t CYCLE Figure13-1 Figure14-1 tRAS RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT command and next ROWR packet with PRER Note 1 command to the same bank. 20 20 20 Note 2 64µs tCYCLE Figure13-1 Figure14-1 tRP Row Precharge time of RDRAM banks - the interval between ROWR packet with PRER Note 1 command and next ROWA packet with ACT command to the same bank. 8 8 8 — t CYCLE Figure13-1 Figure14-1 tPP Precharge-to-precharge time of RDRAM device - the interval between successive ROWR packets with PRER Note 1 commands to any banks of the same device. 8 8 8 — t CYCLE Figure10-3 tRR RAS-to-RAS time of RDRAM device - the interval between successive ROWA packets with ACT commands to any banks of the same device. 8 8 8 — t CYCLE Figure12-1 tRCD RAS-to-CAS Delay - the interval from ROWA packet with ACT command to COLC packet with RD or WR command. Note - the RAS- to-CAS delay seen by the RDRAM core (t RCD-C ) is equal to tRCD-C = 1 + tRCD because of differences in the row and column paths through the RDRAM interface. 9 7 7 — t CYCLE Figure13-1 Figure14-1 tCAC CAS Access delay - the interval from RD command to Q read data. The equation for tCAC is given in the TPARM register in Figure 22-1(5/7). 8 8 8 12 t CYCLE Figure4-1 tCWD CAS Write Delay - interval from WR command to D write data. 6 6 6 6 t CYCLE Figure4-1 tCC CAS-to-CAS time of RDRAM bank - the interval between successive COLC commands. 4 4 4 — t CYCLE Figure13-1 Figure14-1 tPACKET Length of ROWA, ROWR, COLC, COLM or COLX packet. 4 4 4 4 t CYCLE Figure2-1 tRTR Interval from COLC packet with WR command to COLC packet which causes retire, and to COLM packet with bytemask. 8 8 8 — t CYCLE Figure15-1 tOFFP The interval (offset) from COLC packet with RDA command, or from COLC packet with retire command (after WRA automatic precharge), or from COLC packet with PREC command, or from COLX packet with PREX command to the equivalent ROWR packet with PRER. The equation for t OFFP is given in the TPARM register in Figure 22-1(5/7). 4 4 4 4 t CYCLE Figure14-2 tRDP Interval from last COLC packet with RD command to ROWR packet with PRER. 4 4 4 — t CYCLE Figure13-1 tRTP Interval from last COLC packet with automatic retire command to ROWR packet with PRER. 4 4 4 — t CYCLE Figure14-1 Notes 1. Or equivalent PREC or PREX command. See Figure 12-2. 2. This is a constraint imposed by the core, and is therefore in units of ms rather than tCYCLE .

Data Sheet E0039N30 (Ver. 3.0) 67 µµµµPD488588 37. Absolute Maximum Ratings Absolute Maximum Ratings Symbol Parameter MIN. MAX. Unit VI,ABS Voltage applied to any RSL or CMOS pin with respect to GND –0.3 V DD +0.3 V VDD,ABS ,VDDa,ABS Voltage on VDD and VDDa with respect to GND –0.5 V DD +1.0 V TSTORE Storage temperature –50 +100 °C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 38. IDD - Supply Current Profile I DD - Supply Current Profile IDD value RDRAM blocks consuming power @ tCYCLE Note 1 MIN. MAX. Unit IDD,PDN Self-refresh only for INIT.LSR=0  6.0 mA IDD,NAP T/RCLK-Nap  4.2 mA IDD,STBY T/RCLK,ROW-demux 2.50 ns  90 mA 2.81 ns  80 3.33 ns  70 3.83 ns  65 IDD,ATTN T/RCLK, ROW-demux, COL-demux 2.50 ns  135 mA 2.81 ns  125 3.33 ns  115 3.83 ns  105 IDD,ATTN-W T/RCLK, ROW-demux, COL-demux, 2.50 ns  720 mA DQ-demux, 1 •WR-SenseAmp, 4 •ACT-Bank 2.81 ns  670 3.33 ns  620 3.83 ns  570 IDD,ATTN-R T/RCLK, ROW-demux, COL-demux, 2.50 ns  630 mA DQ-mux, 1•RD-SenseAmp, 4•ACT-Bank Note 2 2.81 ns  580 3.33 ns  520 3.83 ns  470 Notes 1. The CMOS interface consumes power in all power states. 2. This does not include the IOL sink current. The RDRAM dissipates IOL •VOL in each output driver when a logic one is driven.

Data Sheet E0039N30 (Ver. 3.0) 69 µµµµPD488588 RSL Pin Parasitics Symbol Parameter and Conditions - RSL pins MIN. MAX. Unit LI RSL effective input inductance – 4.0 nH L12 Mutual inductance between any DQA or DQB RSL signals. – 0.2 nH Mutual inductance between any ROW or COL RSL signals. – 0.6 nH ∆LI Difference in L I value between any RSL pins of a single device. – 1.8 nH C I RSL effective input capacitance Note 800 MHz 2.0 2.4 pF 711 MHz 2.0 2.4 600 MHz 2.0 2.6 C 12 Mutual capacitance between any RSL signals. – 0.1 pF ∆C I Difference in C I value between any RSL pins of a single device. – 0.06 pF R I RSL effective input resistance 4 15 Ω Note This value is a combination of the device IO circuitry and package capacitances. CMOS Pin Parasitics Symbol Parameter and Conditions - CMOS pins MIN. MAX. Unit LI,CMOS CMOS effective input inductance – 8.0 nH C I,CMOS CMOS effective input capacitance (SCK,CMD) Note 1.7 2.1 pF C I,CMOS,SIO CMOS effective input capacitance (SIO1,SIO0) Note – 7.0 pF Note This value is a combination of the device IO circuitry and package capacitances.

Data Sheet E0039N30 (Ver. 3.0) 70 µµµµPD488588 40. Interleaved Device Mode Interleaved Device Mode permits a group of eight RDRAMs on the Channel to collectively respond to acommand. The purpose of this collective response is to limit the number of bits in each dualoct data packet which are read from or written to a single RDRAM device. This capability permits a memory controller to implement hardware for fault detection and correction that can tolerate the complete internal failure of one RDRAM device on a Channel. The IDM bit of the INIT control register enables this fault tolerant operating mode. When it is set, the RDRAM will using an example system with eight RDRAMs. The DEVID4..0 registers of these RDRAMs are initial-ized to “00000” through “00111’. However, when the IDM bit is COLC packets will be executed by groups of eight RDRAMs, with a Channel containing from one to four of these function described below. With IDM set, a directed ACT or PRE command in a ROW packet causes eight RDRAMs to perform the indicated operation. Likewise, when a RD or WR command is specified in a COLC command, the selected group of eight RDRAMs responds. When using IDM, devices must be added to the Channel in groups of eight. An application will typically make the IDM bit setting the same for all RDRAMs on a Channel. The mechanism for indicating a broadcast ROW packet (DR4F and DR4T are both set to one) is not affected by the setting of the IDM bit; i.e. IDM mode does not change the broadcast ROW packet mechanism. directed to a single device. When the IDM bit is set, COLM packets should not be used (the M bit should be set to zero, selecting only COLX packets). This is because the mapping of bytes to RDRAM storage cells is changed by IDM mode. Returning to Figure 40-1, the remaining fields of the ROW and COLC packets are interpreted in the same way fields of the ROW and COLC packets are used to select one of the banks just as when IDM is not set. The R8..0 field selects one dualoct of the selected (BC5..0) bank’s sense amp. The IDM bit affects what is done with this selected dualoct. When IDM is not set, the dualoct is driven onto the Channel by the single selected RDRAM device. When IDM is set, the RDRAM of the eight device group selected by RDRAM register field, the DC2..0 COLC packet field, and the device width (x18). Figure 40-1 shows the mapping that is appropriate for DC2..0=000. Figure 40-2 and Figure 40-3 show the mapping for all eight values of DC2..0. There are eight mappings, which are rotated among the eight devices using the following equation: Pin = 7 - 4 • (DEVID2^DC2) - 2 • (DEVID1^DC1) - 1 • (DEVID0^DC0) (Eq 1) where “^” is the exclusive-or function. “Pin” is the pin number that is driven by the RDRAM with the DEVID2..0 value. For example, Pin=0 means the RDRAM drives DQA0 and DQB0, and so forth. The DQA8 pin is always driven with DQA7, and DQB8 is always driven with DQB6 for x18 devices. For x16 devices, the DQA8 and DQB8 pins are not used. For each of the eight mappings, the eight-RDRAM group supplies a complete dualoct. As the application steps through eight values of DC2..0, all the bits of the eight underlying dualocts will be accessed. Thus, an eight-RDRAM group appears to be a single RDRAM with eight times the normal page size, with the DC2..0 field providing the extra column addressing informa-tion (beyond what C6..0 provides).

Data Sheet E0039N30 (Ver. 3.0) 71 µµµµPD488588 Figure 40-1 ACT, PRE, RD, and WR Commands for Eight RDRAM System with IDM = 1 RDWR ACT senseamp. PRE one bank DQA7 DQB7 DQA8 bank array compare to DEVID4..3 00000 RDRAM 0 DQA0 DQA8 CTM/CFM Channel DEVID 4..0 DR4..3 DC4..3 access device BR5..0 BC5..0 access bank R12..0 access row C6..0 access column DC2..0 =000 form dualoct DQA6 DQB6 DQB8 same as device 0 DQA5 DQB5 DQA4 DQB4 same as device 0 DQA3 DQB3 same as device 0 DQA2 DQB2 same as device 0 DQA1 DQB1 same as device 0 DQA0 DQB0 same as device 0           DQB0 DQB8 same as device 0 RDRAM 1 RDRAM 2 RDRAM 3 RDRAM 4 RDRAM 5 RDRAM 6 RDRAM 7 00001 00010 00011 00100 00101 00110 00111         one bitdualoct (144 bits)row (2C dualocts)bank (2R rows)device (2B banks) notation

Data Sheet E0039N30 (Ver. 3.0) 72 µµµµPD488588 Figure 40-2 Mapping from DEVID2..0 and DC2..0 Fields to DQ Packet with IDM = 1 DQA7 DQB7 DQA8 DQA6 DQB6 DQB8 DQA5 DQB5 DQA4 DQB4 DQA3 DQB3 DQA2 DQB2 DQA1 DQB1 DQA0 DQB0 DQA6 DQB6 DQB8 DQA7 DQB7 DQA8 DQA4 DQB4 DQA5 DQB5 DQA2 DQB2 DQA3 DQB3 DQA0 DQB0 DQA1 DQB1 DQA5 DQB5 DQA4 DQB4 DQA7 DQB7 DQA8 DQA6 DQB6 DQB8 DQA1 DQB1 DQA0 DQB0 DQA3 DQB3 DQA2 DQB2 DQA4 DQB4 DQA5 DQB5 DQA6 DQB6 DQB8 DQA7 DQB7 DQA8 DQA0 DQB0 DQA1 DQB1 DQA2 DQB2 DQA3 DQB3 000 001 010 011 DC2..0 000 001 010 011 100 101 110 111 DEVID2..0 Mapping for previous figure DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 CTM/CFM DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8

Data Sheet E0039N30 (Ver. 3.0) 73 µµµµPD488588 Figure 40-3 Mapping from DEVID2..0 and DC2..0 Fields to DQ Packet with IDM = 1 (continued) DQA3 DQB3 DQA2 DQB2 DQA1 DQB1 DQA0 DQB0 DQA7 DQB7 DQA8 DQA6 DQB6 DQB8 DQA5 DQB5 DQA4 DQB4 DQA2 DQB2 DQA3 DQB3 DQA0 DQB0 DQA1 DQB1 DQA6 DQB6 DQB8 DQA7 DQB7 DQA8 DQA4 DQB4 DQA5 DQB5 DQA1 DQB1 DQA0 DQB0 DQA3 DQB3 DQA2 DQB2 DQA5 DQB5 DQA4 DQB4 DQA7 DQB7 DQA8 DQA6 DQB6 DQB8 DQA0 DQB0 DQA1 DQB1 DQA2 DQB2 DQA3 DQB3 DQA4 DQB4 DQA5 DQB5 DQA6 DQB6 DQB8 DQA7 DQB7 DQA8 100 101 110 111 DC2..0 000 001 010 011 100 101 110 111 DEVID2..0 DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 CTM/CFM DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8

Data Sheet E0039N30 (Ver. 3.0) 74 µµµµPD488588 41. Glossary of Terms ACT Activate command from AV field. D Write data packet on DQ pins. activate To access a roe and place in sense amp. DBL CNFGB register field – doubled-bank. activate To access a row and place in sense amp. DC Device address field in COLC packet. adjacent device An RDRAM on a Channel. Two RDRAM banks which share sense amps (also called doubled banks). DEVID ASYM CCA register field for RSL V OL / VOH . Control register with device address that is matched against DR, DC, and DX fields. ATTN Power state – ready for ROW / COL packets. DM Device match for ROW packet decode. ATTNR Power state – transmitting Q packets. Doubled-bank RDRAM with shared sense amp. ATTNW Power state – receiving D packets. DQ DQA and DQB pins. AV Opcode field in ROW packets. DQA Pins for data byte A. bank DQB Pins for data byte B. A block of 2 RBIT CBIT storage cells in the core of the RDRAM. DQS NAPX register field – PDN/NAP exit. BC Bank address field in CLC packet. DR,DR4T,DR4F BBIT CNFGA register field - # bank address bits. Device address field and packet framing fields in ROW and ROWE packets. broadcast An operation executed by all RDRAMs. dualoct 16 bytes – the smallest addressable datum. BR Bank address field in ROW packets. DX Device address field in COLX packet. bubble field A collection of bits in a packet. Idle cycle(s) on RDRAM pins needed because of a resource constraint. INIT Control register with initialization fields. BYT CNFGB register field – 9 bits per byte. initialization BX Bank address field in COLX packet. Configuring a Channel of RDRAMs so they are ready to respond to transactions. C Column address field in COLC packet. LSR CNFGA register field – low-power self-refresh. CAL Calibrate (I OL ) command in XOP field. M Mask opcode field (COLM/COLX packet). CBIT CNFGB register field - # column address bits. MA Field in COLM packet for masking byte A. CCA Control register – current control A. MB Field in COLM packet for masking byte B. CCB Control register – current control B. MSK Mask command in M field. CFM,CFMN Clock pins for receiving packets. MVER Control register – manufacturer ID. Channel ROW / COL / DQ pins and external wires. NAP Power state – needs SCK/CMD wakeup. CLRR Clear reset command from SOP field. NAPR Nap command in ROP field. CMD CMOS pins for initialization / power control. NAPRC Conditional nap command in ROP field. CNFGA Control register with configuration fields. NAPXA NAPX register field – NAP exit delay A. CNFGB Control register with configuration fields. NAPXB NAPX register field – NAP exit delay B. COL Pins for column-access control. NOCOP No-operation command in COP field. COLC Column operation packet on COL pins. NOROP No-operation command in ROP field. COLM Write mask packet on COL pins. NOXOP No-operation command in XOP field. column NSR INIT register field – NAP self-refresh. Rows in a bank or activated in sense amps have 2 CBTI dualocts column storage. packet A collection of bits carried on the Channel. Command A decoded bit-combination from a field. PDN Power state – needs SCK/CMD wakeup. COLX Extended operation packet on COL pins. PDNR Powerdown command in ROP field. controller PDNXA Control register – PDN exit delay A. A logic-device which drives the ROW / COL / DQ wires for a Channel of RDRAMs. PDNXB Control register – PDN exit delay B. COP Column opcode field in COLC packet. pin efficiency The fraction of non-idle cycles on a pin. core The banks and sense amps of an RDRAM. PRE PREC, PRER, PREX precharge commands. CTM, CTMN Clock pins for transmitting packets. PREC Precharge command in COP field. Current control precharge Prepares sense amp and bank for activate. Periodic operations to update the proper I OL Value of RSL output drivers. PRER Precharge command in ROP field.

Data Sheet E0039N30 (Ver. 3.0) 75 µµµµPD488588 PREX Precharge command in XOP field. SETF Set fast clock command from SOP field. PSX INIT register field – PDN/NAP exit. SETR Set reset command from SOP field. PSR INIT register field – PDN self-refresh. SINT PVER CNFGB register field – protocol version. Serial interval packet for control register read/write transactions. Q Read data packet on DQ pins. SIO0,SIO1 CMOS serial pins for control registers. R Row address field of ROWA packet. SOP Serial opcode field in SRQ. RBIT CNFGB register field - #row address bits. SRD Serial read opcode command from SOP. RD/RDA Read (/precharge) command in COP field. SRP INIT register field – Serial repeat bit. read Operation of accessing sense amp data. SRQ receive Serial request packet for control register read/write transactions. Moving information from the Channel into the RDRAM (a serial stream is demuxed). STBY Power state – ready for ROW packets. REFA Refresh-activate command in ROP field. SVER Control register – stepping version. REFB Control register – next bank (self-refresh). SWR Serial write opcode command from SOP. REFBIT TCAS TCLSCAS register field – t CAS core delay. CNFGA register field – ignore bank bits (for REFA and self-refresh). TCLS TCLSCAS register field – tCLS core delay. REFP Refresh-precharge command in ROP field. TCLSCAS Control register – tCAS and tCLS delay. REFR Control register – next row for REFA. TCYCLE Control register – tCYCLE delay. refresh Periodic operations to restore storage cells. TDAT Control register – tDAC delay. retire TEST77 Control register – for test purposes. The automatic operation that stores write buffer into sense amp after WR command. TEST78 Control register – for test purposes. RLX RLXC, RLXR, RLXX relax commands. TRDLY Control register – tRDLY delay. RLXC Relax command in COP field. transaction ROW, COL, DQ packets for memory access. RLXR Relax command in ROP field. transmit RLXX Relax command in XOP field. Moving information from the RDRAM onto the Channel (parallel word is muxed). ROP Row-opcode field in ROWR packet. WR/WRA Write (/precharge) command in COP field. row 2 CBIT dualocts of cells (bank/sense amp). write Operation of modifying sense amp data. ROW Pins for row-access control XOP Extended opcode field in COLX packet. ROW ROWA or ROWR packets on ROW pins. ROWA Activate packet on ROW pins. ROWR Row operation packet on ROW pins. RQ Alternate name for ROW/COL pins. RSL Rambus Signal levels. SAM Sample (I OL ) command in XOP field. SA Serial address packet for control register transactions w/ SA address field. SBC Serial broadcast field in SRQ. SCK CMOS clock pin. SD Serial data packet for control register transactions w/ SD data field. SDEV Serial device address in SRQ packet. SDEVID INIT register field – Serial device ID. self-refresh Refresh mode for PDN and NAP. sense amp Fast storage that holds copy of bank’s row.

Data Sheet E0039N30 (Ver. 3.0) 76 µµµµPD488588 42. Package Drawing 80-ball FBGA (µµµµ BGA) (17.16 ×××× 10.2) ITEM MILLIMETERS E 10.2 ±0.1 y 0.2 0.1 w 0.2 ZD 1.78 0.08x D 17.16 ±0.10 A 0.96 ±0.10 A1 0.40 ±0.05 0.50±0.05b ZE1 1.1 ECA-TS2-0051-02 ZE2 1.9 eD 0.8 eE 0.8 SD 0.4 SE 1.2 ZD ZE1 11 034 78 UT S R P N M L K J H G F E D C B A A b S INDEX MARK w SA w SB B SE eE SD eD A φ SABx MyS y1 S D E ZE2

Data Sheet E0039N30 (Ver. 3.0) 77 µµµµPD488588 43. Recommended Soldering Conditions Please consult our sales office for soldering conditions of the µPD488588. Type of Surface Mount Device µ PD488588FF-DH1 : 80-ball FBGA (µ BGA) (17.16 × 10.2)

Data Sheet E0039N30 (Ver. 3.0) 78 µµµµPD488588 NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR MOS DEVICES

Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107

µµµµPD488588 M01E0107 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. Rambus, RDRAM and the Rambus logo are registered trademarks of Rambus Inc. µµµµBGA is a registered trademark of Tessera, Inc.