HB52RD328DC-A6F

HB52RD328DC-F ELPIDA | Alldatasheet

Document overview

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• PDF pages: 67

Technical content

Features

• Fully compatible with : JEDEC standard outline 8-byte S.O.DIMM
• 144-pin Zig Zag Dual tabs socket type (dual lead out) ⎯ Outline: 67.60 mm (Length) × 31.75 mm (Height) × 3.80 mm (Thickness) ⎯ Lead pitch: 0.80 mm
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Data bus width: × 64 Non parity
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length : 1/2/4/8/full page

• 2 variations of burst sequence ⎯ Sequential (BL = 1/2/4/8/full page) ⎯ interleave (BL = 1/2/4/8)
• Programmable CE latency : 2/3 (HB52RD328DC-A6F/A6FL) : 3 (HB52RD328DC-B6F/B6FL)
• Byte control by DQMB
• Refresh cycles: 4096 refresh cycles/64 ms
• 2 variations of refresh ⎯ Auto refresh ⎯ Self refresh
• Low self refresh current: HB52RD328DC-A6FL/B6FL (L-version)
• Full page burst length capability ⎯ Sequential burst ⎯ Burst stop capability

Ordering Information

Type No. Frequency CE latency Package Contact pad HB52RD328DC-A6F HB52RD328DC-B6F HB52RD328DC-A6FL HB52RD328DC-B6FL

100 MHz

Small outline DIMM (144-pin) Gold

Pin No. Signal name Pin No. Signal name Pin No. Signal name Pin No. Signal name 1V SS 73 NC 2 V SS 74 CK1

3 DQ0 75 V SS 4 DQ32 76 V SS

5 DQ1 77 NC 6 DQ33 78 NC

7 DQ2 79 NC 8 DQ34 80 NC

9 DQ3 81 V CC 10 DQ35 82 V CC

11 V CC 83 DQ16 12 V CC 84 DQ48

13 DQ4 85 DQ17 14 DQ36 86 DQ49

15 DQ5 87 DQ18 16 DQ37 88 DQ50

17 DQ6 89 DQ19 18 DQ38 90 DQ51

19 DQ7 91 V SS 20 DQ39 92 V SS

21 V SS 93 DQ20 22 V SS 94 DQ52

23 DQMB0 95 DQ21 24 DQMB4 96 DQ53

25 DQMB1 97 DQ22 26 DQMB5 98 DQ54

27 V CC 99 DQ23 28 V CC 100 DQ55

29 A0 101 V CC 30 A3 102 V CC

31 A1 103 A6 32 A4 104 A7

33 A2 105 A8 34 A5 106 A13 (BA0)

35 V SS 107 V SS 36 V SS 108 V SS

37 DQ8 109 A9 38 DQ40 110 A12 (BA1)

39 DQ9 111 A10 (AP) 40 DQ41 112 A11

Pin No. Signal name Pin No. Signal name Pin No. Signal name Pin No. Signal name

41 DQ10 113 V CC 42 DQ42 114 V CC

43 DQ11 115 DQMB2 44 DQ43 116 DQMB6

45 V CC 117 DQMB3 46 V CC 118 DQMB7

47 DQ12 119 V SS 48 DQ44 120 V SS

49 DQ13 121 DQ24 50 DQ45 122 DQ56

51 DQ14 123 DQ25 52 DQ46 124 DQ57

53 DQ15 125 DQ26 54 DQ47 126 DQ58

55 V SS 127 DQ27 56 V SS 128 DQ59

57 NC 129 V CC 58 NC 130 V CC

59 NC 131 DQ28 60 NC 132 DQ60

61 CK0 133 DQ29 62 CKE0 134 DQ61

63 V CC 135 DQ30 64 V CC 136 DQ62

65 RE 137 DQ31 66 CE 138 DQ63

67 W 139 V SS 68 CKE1 140 V SS

69 S0 141 SDA 70 NC 142 SCL

71 S1 143 V CC 72 NC 144 V CC

⎯ Row address A0 to A11 ⎯ Column address A0 to A9 A12/A13 Bank select address BA1, BA0 DQ0 to DQ63 Data-input/output S0/S1 Chip select RE Row address asserted bank enable CE Column address asserted W Write enable DQMB0 to DQMB7 Byte input/output mask CK0/CK1 Clock input CKE0/CKE1 Clock enable SDA Data-input/output for serial PD SCL Clock input for serial PD VCC Power supply VSS Ground NC No connection

Serial PD Matrix*1 Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

0 Number of bytes used by

1 Total SPD memory size 000010000 8 256 byte

2 Memory type 000001000 4 SDRAM

3 Number of row addresses bits 000011000 C 1 2

4 Number of column addresses

000010100 A 1 0

5 Number of banks 000000100 2 2

6 Module data width 010000004 0 6 4

7 Module data width (continued) 000000000 0 0 ( + )

8 Module interface signal levels 000000010 1 LVTTL

9 SDRAM cycle time

(highest CE latency) 10 ns 10100000A 0 C L = 3

10 SDRAM access from Clock

(highest CE latency) 6 ns 011000006 0 C L = 3

11 Module configuration type 000000000 0 Non parity

12 Refresh rate/type 100000008 0 Normal

(15.625 µs) Self refresh

13 SDRAM width 000001000 4 16M × 4

14 Error checking SDRAM width 000000000 0 —

15 SDRAM device attributes:

minimum clock delay for back- to-back random column addresses 000000010 1 1 C L K

16 SDRAM device attributes:

100011118 F 1 , 2 , 4 , 8 , full

17 SDRAM device attributes:

18 SDRAM device attributes:

000001100 6 2 , 3

19 SDRAM device attributes:

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

20 SDRAM device attributes:

21 SDRAM module attributes 000000000 0 Non buffer

22 SDRAM device attributes:

000011100 E V CC ± 10%

23 SDRAM cycle time

(2nd highest CE latency) (-A6F/A6FL) 10 ns 10100000A 0 C L = 2 (-B6F/B6FL) 15 ns 11110000F 0

24 SDRAM access from Clock

(2nd highest CE latency) (-A6F/A6FL) 6 ns 011000006 0 C L = 2 (-B6F/B6FL) 8 ns 100000008 0

25 SDRAM cycle time

(3rd highest CE latency) Undefined 000000000 0

26 SDRAM access from Clock (3rd

highest CE latency) Undefined 000000000 0

27 Minimum row precharge time 000101001 4 2 0 n s

28 Row active to row active min 000101001 4 2 0 n s

29 RE to CE delay min 000101001 4 2 0 n s

30 Minimum RE pulse width 001100103 2 5 0 n s

31 Density of each bank on

32 Address and command signal

001000002 0 2 n s * 7

33 Address and command signal

000100001 0 1 n s * 7

34 Data signal input setup time 001000002 0 2 n s * 7

35 Data signal input hold time 000100001 0 1 n s * 7

36 to 61 Superset information 000000000 0 Future use 62 SPD data revision code 000100101 2 Rev. 1.2A

63 Checksum for bytes 0 to 62

(-A6F/A6FL) 000100111 3 1 9 (-B6F/B6FL) 100000118 3 1 3 1

64 Manuf act ur er’ s J EDEC I D c o d e 000001110 7 HITACHI

65 to 71 Manuf act ur er’ s J EDEC I D c o d e 000000000 0

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 3 (ASCII-8bit code)

73 Manufacturer’s part number 010010004 8 H

74 Manufacturer’s part number 010000104 2 B

75 Manufacturer’s part number 001101013 5 5

76 Manufacturer’s part number 001100103 2 2

77 Manufacturer’s part number 010100105 2 R

78 Manufacturer’s part number 010001004 4 D

79 Manufacturer’s part number 001100113 3 3

80 Manufacturer’s part number 001100103 2 2

81 Manufacturer’s part number 001110003 8 8

82 Manufacturer’s part number 010001004 4 D

83 Manufacturer’s part number 010000114 3 C

84 Manufacturer’s part number 001011012 D —

85 Manufacturer’s part number

(-A6D/A6DL) 010000014 1 A (-B6D/B6DL) 010000104 2 B

86 Manufacturer’s part number 001101103 6 6

87 Manufacturer’s part number 010001104 6 F

88 Manufacturer’s part number

(L-version)

010011004 C L

Manufacturer’s part number 001000002 0 (Space)

89 Manufacturer’s part number 001000002 0 (Space)

90 Manufacturer’s part number 001000002 0 (Space)

(BCD)*4 (BCD)* 95 to 98 Assembly serial number * 6 99 t o 125 Manufacturer specific data ————————— * 5

126 Intel specification frequency 011001006 4 100 MHz

127 Intel specification CE# latency

(-A6FD/A6FDL) 11000111C 7 C L = 2 , 3 (-B6FD/B6FDL) 11000101C 5 C L = 3

Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High” These SPD are based on Intel specification (Rev.1.2A) 2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119. 3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on ASCII code.) 4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is “Binary Coded Decimal”. 5. All bits of 99 through 125 are not defined (“1” or “0”). 6. Bytes 95 through 98 are assembly serial number. 7. These specifications are defined based on component specification, not module.

N0, N1 DQ8 to DQ15 DQMB1 N2, N3 DQ16 to DQ23 DQMB2 N4, N5 DQ24 to DQ31 DQMB3 N6, N7 DQ32 to DQ39 DQMB4 N8, N9 DQ40 to DQ47 DQMB5 N10, N11 DQ48 to DQ55 DQMB6 N12, N13 DQ56 to DQ63 DQMB7 N14, N15 Serial PD SDA SCL SDASCL Notes: 1.SDA pull-up resister is required due to the open-drain/open-collector output. 2.SCL pull-up resistore is recommended because of the normal SCL line inactive "High" state. D0 to D3: HM5264405F U0: 2-kbit EEPROM C0 to C15: 0.1 μF N0 to N15: Network resistors(10 Ω) RAS (D0 to D31) CAS (D0 to D31) A0 to A11 (D0 to D31) BA0 (D0 to D31) BA1 (D0 to D31) CKE (D0 to D15) CKE (D16 to D31) WE (D0 to 31) CLK (D0 to D3, D16 to D19) CLK (D4 to D7, D20 to D23) CLK (D8 to D11, D24 to D27) CLK (D12 to D15, D28 to D31) RE CE A0 to A11 BA0 BA1 CKE0 CK0 CKE1 WE CK1 VSS VCC VCC (D0 to D31) VSS (D0 to D31) C0 to C15 I/O0 to I/O3 DQMB CS D16 I/O0 to I/O3 DQMB CS I/O0 to I/O3 DQMB CS D17 I/O0 to I/O3 DQMB CS D1 I/O0 to I/O3 DQMB CS D18 I/O0 to I/O3 DQMB CS D2 I/O0 to I/O3 DQMB CS D19 I/O0 to I/O3 DQMB CS D3 I/O0 to I/O3 DQMB CS D20 I/O0 to I/O3 DQMB CS D4 I/O0 to I/O3 DQMB CS D21 I/O0 to I/O3 DQMB CS D5 I/O0 to I/O3 DQMB CS D22 I/O0 to I/O3 DQMB CS D6 I/O0 to I/O3 DQMB CS D23 I/O0 to I/O3 DQMB CS D7 I/O0 to I/O3 DQMB CS D24 I/O0 to I/O3 DQMB CS D8 I/O0 to I/O3 DQMB CS D25 I/O0 to I/O3 DQMB CS D9 I/O0 to I/O3 DQMB CS D26 I/O0 to I/O3 DQMB CS D10 I/O0 to I/O3 DQMB CS D27 I/O0 to I/O3 DQMB CS D11 I/O0 to I/O3 DQMB CS D28 I/O0 to I/O3 DQMB CS D12 I/O0 to I/O3 DQMB CS D29 I/O0 to I/O3 DQMB CS D13 I/O0 to I/O3 DQMB CS D30 I/O0 to I/O3 DQMB CS D14 I/O0 to I/O3 DQMB CS D31 I/O0 to I/O3 DQMB CS D15

Parameter Symbol Value Unit Note Voltage on any pin relative to V SS VT –0.5 to VCC + 0.5 (≤ 4.6 (max)) Supply voltage relative to VSS VCC –0.5 to +4.6 V 1 Short circuit output current Iout 50 mA Power dissipation P T 4.0 W Operating temperature Topr 0 to +65 °C Storage temperature Tstg –55 to +125 °C Note: 1. Respect to V SS. DC Operating Conditions (Ta = 0 to +65°C) Parameter Symbol Min Max Unit Notes Supply voltage V CC 3.0 3.6 V 1, 2 VSS 00V3 Input high voltage V IH 2.0 V CC + 0.3 V 1, 4, 5 Input low voltage V IL –0.3 0.8 V 1, 6 Notes: 1. All voltage referred to V SS 2. The supply voltage with all V CC pins must be on the same level. 3. The supply voltage with all V SS pins must be on the same level. 4. CK, CKE, S, DQMB, DQ pins: VIH (max) = VCC + 0.5 V for pulse width ≤ 5 ns at VCC. 5. Others: V IH (max) = 4.6 V for pulse width ≤ 5 ns at VCC. 6. V IL (min) = –1.0 V for pulse width ≤ 5 ns at VSS.

VIL/VIH Clamp (Component characteristic) This SDRAM component has VIL and VIH clamp for CK, CKE, S, DQMB and DQ pins. Minimum VIL Clamp Current VIL (V) I (mA) –2 –32 –1.8 –25 –1.6 –19 –1.4 –13 –1.2 –8 –1 –4 –0.9 –2 –0.8 –0.6 –0.6 0 –0.4 0 –0.2 0 VIL (V) I (mA) –1.5 –1 –0.5–5 –15 –10 –25 –20 –30 –35 –20

VIH (V) I (mA) VCC + 2 10 VCC + 1.8 8 VCC + 1.6 5.5 VCC + 1.4 3.5 VCC + 1.2 1.5 VCC + 1 0.3 VCC + 0.8 0 VCC + 0.6 0 VCC + 0.4 0 VCC + 0.2 0 VCC + 0 0 VIH (V) VCC + 0 V CC + 1 V CC + 2VCC + 0.5 V CC + 1.5 I (mA)

IOL/IOH Characteristics (Component characteristic) Output Low Current (IOL) IOL IOL Vout (V) Min (mA) Max (mA) 00 0 0.4 27 71 0.65 41 108 0.85 51 134 1 58 151 1.4 70 188 1.5 72 194 1.65 75 203 1.8 77 209 1.95 77 212 3 80 220 3.45 81 223 IOL (mA) Vout (V) 250 200 150 100 0 0.5 1 1.5 2 2.5 3 3.5 min max

Output High Current (IOH) (Ta = 0 to 65˚C, VCC = 3.0 V to 3.45 V, VSS = 0 V) IOH IOH Vout (V) Min (mA) Max (mA) 3.45 — –3 3.3 — –28 30 – 7 5 2.6 –21 –130 2.4 –34 –154 2 –59 –197 1.8 –67 –227 1.65 –73 –248 1.5 –78 –270 1.4 –81 –285 1 –89 –345 0 –93 –503 IOH (mA) Vout (V) –100 –200 –300 –500 –600 –400 0.5 1 1.5 2 2.5 3 min max 3.50

DC Characteristics (Ta = 0 to 65˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) HB52RD328DC -A6F/A6FL -B6F/B6FL Parameter Symbol Min Max Min Max Unit Test conditions Notes Operating current ( CE latency = 2) I CC1 — 1248 — 1248 mA Burst length = 1 t RC = min 1, 2, 3 ( CE latency = 3) I CC1 — 1248 — 1248 mA Standby current in power down I CC2P — 48 — 48 mA CKE = V IL, tCK = 12 ns Standby current in power down (input signal stable) I CC2PS — 32 — 32 mA CKE = V IL, tCK = ∞ 7 Standby current in non power down I CC2N — 320 — 320 mA CKE, S = VIH, tCK = 12 ns Active standby current in power down I CC3P — 128 — 128 mA CKE = V IL, tCK = 12 ns 1, 2, 6 Active standby current in non power down I CC3N — 576 — 576 mA CKE, S = VIH, tCK = 12 ns 1, 2, 4 Burst operating current ( CE latency = 2) I CC4 — 1168 — 1168 mA t CK = min, BL = 4 1, 2, 5 ( CE latency = 3) I CC4 — 1168 — 1168 mA Refresh current I CC5 — 2048 — 2048 mA t RC = min 2, 3 Self refresh current I CC6 — 32 — 32 mA V IH ≥ VCC – 0.2 V VIL ≤ 0.2 V Self refresh current (L-version) I CC6 — 12.8 — 12.8 mA Input leakage current I LI –1 1 –1 1 µA 0 ≤ Vin ≤ VCC Output leakage current I LO –1.5 1.5 –1.5 1.5 µA 0 ≤ Vout ≤ VCC DQ = disable Output high voltage V OH 2.4 — 2.4 — V I OH = –4 mA Output low voltage V OL — 0.4 — 0.4 V I OL = 4 mA

Notes: 1. I CC depends on output load condition when the device is selected. I CC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CLK operating current. 7. After power down mode, no CLK operating current. 8. After self refresh mode set, self refresh current. Capacitance (Ta = 25°C, V CC = 3.3 V ± 0.3 V) Parameter Symbol Max Unit Notes Input capacitance (Address) C IN 150 pF 1, 2, 4 Input capacitance (RE, CE, W, S, CKE) C IN 150 pF 1, 2, 4 Input capacitance (CK) C IN 90 pF 1, 2, 4 Input capacitance (DQMB) C IN 30 pF 1, 2, 4 Input/Output capacitance (DQ) C I/O 30 pF 1, 2, 3, 4 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. 3. DQMB = V IH to disable Dout. 4. This parameter is sampled and not 100% tested.

AC Characteristics (Ta = 0 to 65˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) HB52RD328DC -A6F/A6FL -B6F/B6FL Parameter Symbol PC100 Symbol Min Max Min Max Unit Notes System clock cycle time ( CE latency = 2) t CK Tclk 10 — 15 — ns 1 ( CE latency = 3) t CK Tclk 10 — 10 — ns CK high pulse width t CKH Tch 4 — 4 — ns 1 CK low pulse width t CKL Tcl 4 — 4 — ns 1 Access time from CK ( CE latency = 2) t AC Tac — 6 — 8 ns 1, 2 ( CE latency = 3) t AC Tac — 6 — 6 ns Data-out hold time t OH Toh 3 — 3 — ns 1, 2 CK to Data-out low impedance t LZ 2 — 2 — ns 1, 2, 3 CK to Data-out high impedance t HZ — 6 — 6 ns 1, 4 Data-in setup time t AS, tCS, tDS, tCES Tsi 3 — 3 — ns 1, 5, 6 CKE setup time for power down exit t CESP Tpde 3 — 3 — ns 1 Data-in hold time t AH, tCH, tDH, tCEH Thi 1 — 1 — ns 1, 5 Ref/Active to Ref/Active command period t RC Trc 70 — 70 — ns 1 Active to Precharge command period t RAS Tras 50 120000 50 120000 ns 1 Active command to column command (same bank) t RCD Trcd 20 — 20 — ns 1 Precharge to active command period t RP Trp 20 — 20 — ns 1 Write recovery or data-in to precharge lead time t DPL Tdpl 10 — 10 — ns 1 Active (a) to Active (b) command period t RRD Trrd 20 — 20 — ns 1 Transition time (rise to fall) t T 1515n s Refresh period t REF — 64 — 64 ms

Notes: 1. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. 2. Access time is measured at 1.5 V. Load condition is CL = 50 pF. 3. t LZ (max) defines the time at which the outputs achieves the low impedance state. 4. t HZ (max) defines the time at which the outputs achieves the high impedance state. 5. t CES define CKE setup time to CK rising edge except power down exit command. 6. t AS/tAH: Address, tCS/tCH: S, RE, CE, W, DQMB tDS/tDH: Data-in, t CES/tCEH: CKE Test Conditions

• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures tT 2.4 V 0.4 V 0.8 V

2.0 Vinput

Relationship Between Frequency and Minimum Latency HB52RD328DC Parameter -A6F/A6FL/B6F/B6FL Frequency (MHz) 100 tCK (ns) Symbol PC100 Symbol 10 Notes Active command to column command (same bank) l RCD 21 Active command to active command (same bank) l RC 7= [ l RAS+ lRP] Active command to precharge command (same bank) l RAS 51 Precharge command to active command (same bank) l RP 21 Write recovery or data-in to precharge command (same bank) l DPL Tdpl 1 1 Active command to active command (different bank) l RRD 21 Self refresh exit time l SREX Tsrx 1 2 Last data in to active command (Auto precharge, same bank) l APW Tdal 3 = [l DPL + lRP] Self refresh exit to command input l SEC 7= [ l RC] Precharge command to high impedance ( CE latency = 2) l HZP Troh 2 ( CE latency = 3) l HZP Troh 3 Last data out to active command (auto precharge) (same bank) l APR 1 Last data out to precharge (early precharge) ( CE latency = 2) l EP –1 ( CE latency = 3) l EP –2 Column command to column command l CCD Tccd 1 Write command to data in latency l WCD Tdwd 0 DQMB to data in l DID Tdqm 0 DQMB to data out l DOD Tdqz 2 CKE to CK disable l CLE Tcke 1 Register set to active command l RSA Tmrd 1

Parameter -A6F/A6FL/B6F/B6FL Frequency (MHz) 100 tCK (ns) Symbol PC100 Symbol 10 Notes S to command disable l CDD 0 Power down exit to command input l PEC 1 Burst stop to output valid data hold ( CE latency = 2) l BSR 1 ( CE latency = 3) l BSR 2 Burst stop to output high impedance ( CE latency = 2) l BSH 2 ( CE latency = 3) l BSH 3 Burst stop to write data ignore l BSW 0 Notes: 1. l RCD to lRRD are recommended value. 2. Be valid [DSEL] or [NOP] at next command of self refresh exit. 3. Except [DSEL] and [NOP].

C K 0 / C K 1 ( i n p u t p i n ) : C K i s t he m as t er cl oc k i nput t o t hi s pi n. The ot her i nput s i gnal s ar e re fe rre d at C K rising edge. S 0/ S 1 (i n pu t p in ): Whe n S i s Low, t he com m and i nput cyc l e bec om es val i d. Whe n S i s Hi gh, al l i nput s ar e ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM modules, t hey func t ion i n a di ffe re nt wa y. The se pi ns def i ne oper at i on com m ands (r ea d, wr it e , et c .) depe ndi ng on t he combination of their voltage levels. For details, refer to the command operation section. A0 to A11 (i n pu t p in s ): R ow addr es s (A X0 t o AX11) i s det e rm i ned by A0 t o A11 l eve l at t he bank ac t ive command cycle CK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read or wr it e com m and cyc l e C K ri s i ng edge . And t hi s col um n addr es s bec om es burs t ac ce s s s t art addr es s . A10 def i nes t he pre cha rge m ode. Whe n A10 = Hi gh at t he pre cha rge com m and cyc l e, bot h banks ar e pre cha rged. B ut whe n A10 = Low at t he pre cha rge com m and cyc l e, onl y t he bank t hat i s s el e ct ed by A12/ A13 (B A) i s precharged. A12/A13 (input pin): A12/A13 is a bank select signal (BA). The memory array is divided into bank0, bank1, bank2 and bank3. If A12 is Low and A13 is Low, bank0 is selected. If A12 is High and A13 is Low, bank1 is selected. If A12 is Low and A13 is High, bank2 is selected. If A12 is High and A13 is HIgh, bank3 is selected. CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next C K ri s i ng edge i s val i d. If C KE i s Low, t he next C K ri s i ng edge i s i nval i d. Thi s pi n i s us ed for powe r-dow n mode, clock suspend mode and self refresh mode. DQ MB 0 to DQ MB 7 (i n pu t p in s ): R ea d oper at i on: If DQM B i s Hi gh, t he out put buff er bec om es Hi gh-Z. If the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks). Wr i te oper at i on: If DQM B i s Hi gh, t he pre vi ous dat a i s hel d (t he new dat a i s not wr it t en) . If DQM B i s Low, the data is written (The latency of DQMB during writing is 0 clock). DQ0 to DQ63 (DQ pins): Data is input to and output from these pins. V CC (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected.

The SDRAM module recognizes the following commands specified by the S, RE, CE, W and address pins. CKE Command Symbol n - 1 n S R EC EW A12/A13 A10 to A11 No operation NOP H × LHHH ×× × Burst stop in full page BST H × LHHL ×× × Column address and read command READ H × LHLH V LV Read with auto-precharge READ A H × LHLH V HV Column address and write command WRIT H × LHLLV LV Write with auto-precharge WRIT A H × LHLLV HV Row address strobe and bank active ACTV H × LLHH V VV Precharge select bank PRE H × LLHLV L × Precharge all bank PALL H × LLHL × H × Refresh REF/SELF H V L L L H ×× × Mode register set MRS H × LLLLV VV Note: H: V IH. L: VIL. ×: VIH or VIL. V: Valid address input Ignore command [DESL]: When this command is set (S is High), the SDRAM module ignore command input at the clock. However, the internal status is held. No op erat i on [N OP] : Thi s com m and i s not an exe cut i on com m and. Howe ver , t he i nt erna l oper at i ons continue. Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page) and is illegal otherwise. When data input/output is completed for a full page of data, it automatically returns to the start address, and input/output is performed repeatedly. Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address and the bank select address (BA). After the read operation, the output buffer becomes High-Z. Re ad wi th au to-p re ch arge [R EAD A] : Thi s com m and aut om at i ca l ly per form s a pre cha rge oper at i on af t er a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal.

Col u mn ad dr es s s tr obe an d wr it e com man d [WR IT ]: Thi s com m and s t art s a wr it e oper at i on. Whe n t he burs t wr it e m ode i s s el e ct ed, t he col um n addr es s and t he bank s el e ct addr es s (B A) bec om e t he burs t wr it e s t art addr es s . Whe n t he s i ngle wr it e m ode i s s el e ct ed, dat a i s onl y wr it t en t o t he l oca ti on s pec i fi ed by t he col um n address and the bank select address (BA). Wri t e wi th au to-p re ch arge [WR IT A] : Thi s com m and aut om at i ca l ly per form s a pre cha rge oper at i on af t er a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this command is illegal. Row ad dr es s s tr obe an d b ank act i vate [A CTV ]: Thi s com m and ac t iva t es t he bank t hat i s s el e ct ed by bank s el e ct addr es s (B A) and det e rm i nes t he row addr es s (A X0 t o AX11) . Whe n A12 and A13 ar e Low, bank 0 i s activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank 2 is activated. When A12 and A13 are High, bank 3 is activated. Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A12/A13. If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mod e re gi s ter s et [M RS ]: The S DRA M m odul e has a m ode re gi st e r t hat def i nes how i t oper at es . The m ode register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the mode re gi st e r conf i gurat i on. Af te r powe r on, t he cont e nts of t he m ode re gi st e r ar e undef i ned, exe cut e t he m ode register set command to set up the mode register.

Command Symbol n - 1 n DQMB Write enable/output enable ENB H × L Write inhibit/output disable MASK H × H Note: H: V IH. L: VIL. ×: VIH or VIL. Write: IDID is needed. Read: I DOD is needed. The SDRAM module can mask input/output data by means of DQMB. During reading, the output buffer is set to Low-Z by setting DQMB to Low, enabling data output. On the other hand, when DQMB is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQMB to Low. When DQMB is set to High, the previous data is held (t he new dat a i s not wr it t en) . De s ir ed dat a ca n be m as ke d duri ng burs t re ad or burs t wr it e by s et t i ng DQM B . For details, refer to the DQMB control section of the SDRAM module operating instructions. CKE Truth Table CKE Current state Command n - 1 n S R EC EW Address Active Clock suspend mode entry H L ××××× Any Clock suspend L L ××××× Clock suspend Clock suspend mode exit L H ××××× Idle Auto-refresh command (REF) H H LLLH × Idle Self-refresh entry (SELF) H LLLLH × Idle Power down entry H L L H H H × HL H ×××× Self refresh Self refresh exit (SELFX) L H L H H H × LH H ×××× Power down Power down exit L H L H H H × LH H ×××× Note: H: V IH. L: VIL. ×: VIH or VIL.

Cl ock s us p en d mod e en tr y: The S DRA M m odul e ent e rs cl oc k s us pend m ode fr om ac t ive m ode by s et t i ng C KE t o Low. If com m and i s i nput i n t he cl oc k s us pend m ode ent r y cyc l e, t he com m and i s val i d. The cl oc k suspend mode changes depending on the current status (1 clock before) as shown below. ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. RE AD s us p en d an d RE AD wi th Au to-p re ch arge s us p en d: The dat a bei ng out put i s hel d (a nd cont i nues t o be output). WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During clock suspend mode, keep the CKE to Low. Cl ock s us p en d mod e exi t : The S DRA M m odul e exi t s fr om cl oc k s us pend m ode by s et t i ng C KE t o Hi gh during the clock suspend state. IDLE: In this state, all banks are not selected, and completed precharge operation. Auto-refresh command [REF]: When this command is input from the IDLE state, the SDRAM module starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the aut o- ref res h oper at i on, re fre s h addr es s and bank s el e ct addr es s ar e gene ra te d i ns ide t he S DRA M m odul e. F or eve ry aut o- ref res h cyc l e, t he i nt erna l addr es s count e r i s updat e d. Ac cordi ngl y, 4096 t i me s ar e re qui red t o refresh the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state. In addi t i on, s i nce t he pre cha rge for al l banks i s aut om at i ca l ly per form e d af t er aut o- ref res h, no pre cha rge command is required after auto-refresh. S el f-r ef re sh en tr y [S E LF] : Whe n t hi s com m and i s i nput duri ng t he ID LE s t at e, t he S DRA M m odul e s t art s s el f- re fre s h oper at i on. Af te r t he exe cut i on of t hi s com m and, s el f- re fre s h cont i nues whi l e C KE i s Low. S inc e self-refresh is performed internally and automatically, external refresh operations are unnecessary. Power down mode entry: When this command is executed during the IDLE state, the SDRAM module enters powe r down m ode. In powe r down m ode, powe r cons um pt i on i s s uppre s se d by cut t i ng off t he i ni ti a l i nput circuit. S el f-r ef re sh exi t : Whe n t hi s com m and i s exe cut e d duri ng s el f- re fre s h m ode, t he S DRA M m odul e ca n exi t from self-refresh mode. After exiting from self-refresh mode, the SDRAM module enters the IDLE state. Powe r d own exi t : Whe n t hi s com m and i s exe cut e d at t he powe r down m ode, t he S DRA M m odul e ca n exi t from power down mode. After exiting from power down mode, the SDRAM module enters the IDLE state.

The following table shows the operations that are performed when each command is issued in each mode of the SDRAM module. The following table assumes that CKE is high. Current state SR E C E W Address Command Operation Precharge H ×××× DESL Enter IDLE after t RP LHH H × NOP Enter IDLE after t RP LHH L × BST NOP L H L H BA, CA, A10 READ/READ A ILLEGAL* 4 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL* 4 L L H H BA, RA ACTV ILLEGAL* 4 L L H L BA, A10 PRE, PALL NOP* 6 LLLH × REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Idle H ×××× DESL NOP LHH H × NOP NOP LHH L × BST NOP L H L H BA, CA, A10 READ/READ A ILLEGAL* 5 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL* 5 L L H H BA, RA ACTV Bank and row active L L H L BA, A10 PRE, PALL NOP LLLH × REF, SELF Refresh L L L L MODE MRS Mode register set Row active H ×××× DESL NOP LHH H × NOP NOP LHH L × BST NOP L H L H BA, CA, A10 READ/READ A Begin read L H L L BA, CA, A10 WRIT/WRIT A Begin write L L H H BA, RA ACTV Other bank active ILLEGAL on same bank*3 L L H L BA, A10 PRE, PALL Precharge LLLH × REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL

Current state SR E C E W Address Command Operation Read H ×××× DESL Continue burst to end LHH H × NOP Continue burst to end LHH L × BST Burst stop to full page L H L H BA, CA, A10 READ/READ A Continue burst read to CE latency and New read L H L L BA, CA, A10 WRIT/WRIT A Term burst read/start write L L H H BA, RA ACTV Other bank active ILLEGAL on same bank*3 L L H L BA, A10 PRE, PALL Term burst read and Precharge LLLH × REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Read with auto- precharge H ×××× DESL Continue burst to end and precharge LHH H × NOP Continue burst to end and precharge LHH L × BST ILLEGAL L H L H BA, CA, A10 READ/READ A ILLEGAL* 4 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL* 4 L L H H BA, RA ACTV Other bank active ILLEGAL on same bank*3 L L H L BA, A10 PRE, PALL ILLEGAL* 4 LLLH × REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Write H ×××× DESL Continue burst to end LHH H × NOP Continue burst to end LHH L × BST Burst stop on full page L H L H BA, CA, A10 READ/READ A Term burst and New read L H L L BA, CA, A10 WRIT/WRIT A Term burst and New write L L H H BA, RA ACTV Other bank active ILLEGAL on same bank*3 L L H L BA, A10 PRE, PALL Term burst write and Precharge*2 LLLH × REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL

Current state SR E C E W Address Command Operation Write with auto- precharge H ×××× DESL Continue burst to end and precharge LHH H × NOP Continue burst to end and precharge LHH L × BST ILLEGAL L H L H BA, CA, A10 READ/READ A ILLEGAL* 4 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL* 4 L L H H BA, RA ACTV Other bank active ILLEGAL on same bank*3 L L H L BA, A10 PRE, PALL ILLEGAL* 4 LLLH × REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Refresh (auto- refresh) H ×××× DESL Enter IDLE after t RC LHH H × NOP Enter IDLE after t RC LHH L × BST Enter IDLE after t RC L H L H BA, CA, A10 READ/READ A ILLEGAL* 5 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL* 5 L L H H BA, RA ACTV ILLEGAL* 5 L L H L BA, A10 PRE, PALL ILLEGAL* 5 LLLH × REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Notes: 1. H: V IH. L: VIL. ×: VIH or VIL. The other combinations are inhibit. 2. An interval of t DPL is required between the final valid data input and the precharge command. 3. If t RRD is not satisfied, this operation is illegal. 4. Illegal for same bank, except for another bank. 5. Illegal for all banks. 6. NOP for same bank, except for another bank.

From PRECHARGE state, command operation To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM module enters the IDLE state after tRP has elapsed from the completion of precharge. From IDLE state, command operation To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The SDRAM module enters refresh mode (auto-refresh or self-refresh). To [MRS]: The SDRAM module enters the mode register set cycle. From ROW ACTIVE state, command operation To [DESL], [NOP] or [BST]: These commands result in no operation. To [READ], [READ A]: A read operation starts. (However, an interval of t RCD is required.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of t RCD is required.) T o [A CTV ]: Thi s com m and m ake s t he ot her bank ac t ive . (H oweve r, an i nt erva l of t RRD i s re qui red. ) Attempting to make the currently active bank active results in an illegal command. T o [PR E] , [PA LL ]: The se com m ands s et t he S DRA M m odul e t o pre cha rge m ode. (H oweve r, an i nt erva l of tRAS is required.) From READ state, command operation To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: Data output by the previous read command continues to be output. After CE latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle. T o [A CTV ]: Thi s com m and m ake s ot her banks bank ac t ive . (H oweve r, an i nt erva l of t RRD i s re qui red. ) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the SDRAM module enters precharge mode.

From READ with AUTO-PRECHARGE state, command operation To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the SDRAM module then enters precharge mode. T o [A CTV ]: Thi s com m and m ake s ot her banks bank ac t ive . (H oweve r, an i nt erva l of t RRD i s re qui red. ) Attempting to make the currently active bank active results in an illegal command. From WRITE state, command operation To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. T o [A CTV ]: Thi s com m and m ake s t he ot her bank ac t ive . (H oweve r, an i nt erva l of t RRD i s re qui red. ) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the SDRAM module then enters precharge mode. From WRITE with AUTO-PRECHARGE state, command operation To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the SDRAM module enters precharge mode. T o [A CTV ]: Thi s com m and m ake s t he ot her bank ac t ive . (H oweve r, an i nt erva l of t RRD i s re qui red. ) Attempting to make the currently active bank active results in an illegal command. From REFRESH state, command operation T o [D ES L] , [N OP] , [B S T] : Af te r an aut o- ref res h cyc l e (a ft er t RC), t he S DRA M m odul e aut om at i ca l ly ent e rs the IDLE state.

CKE_ ACTIVE WRITE READ WRITE WITH AP READ WITH AP POWER APPLIED CKE CKE_ CKE CKE_ CKE CKE_ CKE CKE_ CKE CKE_ PRECHARGE AP READ WRITE WRITE WITH AP READ WITHREAD WITH AP WRITE WITH AP PRECHARGE PRECHARGE PRECHARGE BST (on full page) BST (on full page) READ Read WRITE Write Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state.

Mode Register Configuration The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A13, A12, A11, A10, A9 A8: (O PCO DE ): The S DRA M m odul e has t wo t ypes of wr it e m odes . One i s t he burst write mode, and the other is the single write mode. These bits specify write mode. B ur s t re ad an d b ur st wr it e: B urs t wr it e i s per form e d for t he s pec i fi ed burs t l engt h s t art i ng fr om t he col um n address specified in the write cycle. B ur s t re ad an d s i ngl e wr it e: Da ta i s onl y wr it t en t o t he col um n addr es s s pec i fi ed duri ng t he wr it e cyc l e, regardless of the burst length. A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set. A6, A5, A4: (LMODE): These pins specify the CE latency. A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected. A2, A1, A0: (BL): These pins specify the burst length. A2 A1 A0 Burst Length 000 1 001 2 010 4 011 8 1 1 1 F.P. BT=0 BT=1 100 R 110 R R R R

0 Sequential

1 Interleave

Burst TypeA6 A5 A4 CAS Latency 000 R 001 R 010 2* 011 3 1XX R A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OPCODE 0 LMODE BT BL Write modeA8 Burst read and burst write

1 Burst read and single write0

101 R R

F.P. = Full Page R is Reserved (inhibit) X: 0 or 1 Note: only -A6. A11 A10 A10 X X X A11 X X X A12A13 A13 X X X A12 X X X

Addressing(decimal) 000 001 010 011 111 InterleaveSequential 100 110 101 Starting Ad. 2, 3, 4, 5, 6, 7, 3, 4, 5, 6, 7, 4, 5, 6, 7, 5, 6, 7, 6, 7, 0, 1, 0, 1, 2, 0, 1, 2, 3, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, 2, 3, 0, 1, 6, 7, 3, 2, 1, 0, 7, 4, 5, 6, 7, 5, 4, 7, 6, 7, 4, 5, 6, 5, 4, 0, 1, 2, 3, 6, 1, 0, 3, 2, 4, 5, 2, 3, 0, 1, Burst length = 8 A1 A0 Addressing(decimal) InterleaveSequential Starting Ad. 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, Burst length = 4 Addressing(decimal) InterleaveSequential Starting Ad. 0, 1, 1, 0, 0, 1, 1, 0, Burst length = 2

Operation of the SDRAM module Read/Write Operations B ank act i ve: B efor e exe cut i ng a re ad or wr it e oper at i on, t he cor re spondi ng bank and t he row addr es s m us t be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to the s t at us of t he bank s el e ct addr es s (B A) pi n, and t he row addr es s (A X0 t o AX11) i s ac t iva t ed by t he A0 t o A11 pins at the bank active command cycle. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CE Latency - 1) cycle after read command set. The SDRAM module can perform a burst read operation. The burst length can be set to 1, 2, 4, 8 or full-page. The start address for a burst read is specified by the column address and the bank select address (BA) at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the CE Latency. The CE Latency can be set to 2 or 3. Whe n t he burs t l engt h i s 1, 2, 4 or 8, t he Dout buff er aut om at i ca l ly bec om es Hi gh-Z at t he next cl oc k af t er t he successive burst-length data has been output. The CE latency and burst length must be specified at the mode register. CE Latency READ CK Command Dout ACTV Row ColumnAddress CL = 2 CL = 3 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 tRCD CL = CE latency Burst Length = 4

BL = 1 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 6 out 7out 4 out 5 out 0-1 out 0 out 1 BL = 2 BL = 4 BL = 8 BL = full page tRCD BL : Burst Length CE Latency = 2 Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9, A8) of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4, 8, and ful l -pa ge, l i ke burs t re ad oper at i ons . The wr it e s t art addr es s i s s pec i fi ed by t he col um n addr es s and the bank select address (BA) at the write command set cycle. WRIT CK Command Din ACTV Row Column in 0 in 6 in 7 in 8 Address in 1 in 4 in 5 in 3 BL = 1 in 6 in 7in 4 in 5 in 0-1 in 0 in 1 BL = 2 BL = 4 BL = 8 BL = full page tRCD in 0 in 0 in 0 in 0 in 1 in 1 in 1 in 2 in 2 in 2 in 3 in 3 CE Latency = 2, 3

1. S in gl e wr it e: A s i ngle wr it e oper at i on i s ena bl ed by s et t i ng OP CO DE (A 9, A8) t o (1, 0). In a s i ngle wr it e oper at i on, dat a i s onl y wr it t en t o t he col um n addr es s and t he bank s el e ct addr es s (B A) s pec i fi ed by t he wr it e command set cycle without regard to the burst length setting. (The latency of data input is 0 clock). WRIT CK Command Din ACTV Row Column in 0 Address tRCD Auto Precharge Re ad wi th au to-p re ch arge : In t hi s oper at i on, s i nce pre cha rge i s aut om at i ca l ly per form e d af t er com pl et i ng a re ad oper at i on, a pre cha rge com m and nee d not be exe cut e d af t er ea ch re ad oper at i on. The com m and exe cut e d for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by lAPR is required before execution of the next command. CE latency Precharge start cycle 3 2 cycle before the final data is output 2 1 cycle before the final data is output Burst Read (Burst Length = 4) CK lAPR lRAS lAPR CL=2 Command CL=3 Command Dout Dout Note: Internal auto-precharge starts at the timing indicated by " ". And an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ". ACTV READ A ACTV out3out2out1out0 lRAS ACTV READ A ACTV out3out2out1out0

Write with auto-precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The com m and exe cut e d for t he s am e bank af t er t he exe cut i on of t hi s com m and m us t be t he bank ac t ive (A CTV ) com m and. In addi t i on, an i nt erva l of l AP W i s re qui red bet we en t he fi na l val i d dat a i nput and i nput of next command. Burst Write (Burst Length = 4) CK Command Din lAPW IRAS ACTV WRIT A in0 in1 in2 in3 ACTV Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ". Single Write CK Command Din lAPW IRAS ACTV WRIT A in ACTV Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ".

Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a ful l -pa ge burs t . The B ST com m and s et s t he out put buff er t o Hi gh-Z and s t ops t he ful l -pa ge burs t re ad. The timing from command input to the last data changes depending on the CE latency setting. In addition, the BST command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8. CE latency BST to valid data BST to high impedance 212 323 CE Latency = 2, Burst Length = full page l = 1 cycleBSR CK Command Dout out out outout l = 2 cycleBSH BST out out CE Latency = 3, Burst Length = full page l = 2 cycleBSR CK Command Dout out out outout l = 3 cycleBSH BST outout out

B ur s t s top com man d at b ur st wr it e: The burs t s t op com m and (B S T com m and) i s us ed t o s t op dat a i nput duri ng a ful l -pa ge burs t wr it e . No dat a i s wr it t en i n t he s am e cl oc k as t he B ST com m and, and i n s ubs eque nt cl oc ks . In addi t ion, t he B ST com m and i s onl y val i d duri ng ful l -pa ge burs t m ode, and i s i l le gal wi t h burs t lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge command. Burst Length = full page t CK Command Din in DPL in PRE/PALLBST I = 0 cycleBSW

Read command to Read command interval: 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no l es s t han 1 cl oc k. Eve n whe n t he fi rs t com m and i s a burs t re ad t hat i s not yet fi ni s hed, t he dat a re ad by t he second command will be valid. READ to READ Command Interval (same ROW address in same bank) CK Command Dout out B3 Address out B1 out B2 BA ACTV Row Column A READ READ Column B out A0 out B0 Bank0 Active Column =A Read Column =B Read Column =A Dout Column =B Dout CE Latency = 3 Burst Length = 4 Bank 0 2. S ame b ank , d if fer en t RO W ad dr es s : Whe n t he R OW addr es s cha nges on s am e bank, cons e cut i ve re ad com m ands ca nnot be exe cut e d; i t i s nec es s a ry t o s epa ra te t he t wo re ad com m ands wi t h a pre cha rge com m and and a bank-active command. 3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 cl oc k, provi de d t hat t he ot her bank i s i n t he bank- ac ti ve s t at e. Eve n whe n t he fi rs t com m and i s a burs t re ad that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (different bank) CK Command Dout out B3 Address out B1 out B2 BA ACTV Row 0 Row 1 ACTV READ Column A out A0 out B0 Bank0 Active Bank3 Active Bank0 Read Bank3 Read READ Column B Bank0 Dout Bank3 Dout CE Latency = 3 Burst Length = 4

Write command to Write command interval: 1. Same bank, same ROW address: When another write command is executed at the same ROW address of t he s am e bank as t he pre ce ding wr it e com m and, t he s ec ond wr it e ca n be per form e d af t er an i nt erva l of no l es s than 1 clock. In the case of burst writes, the second write command has priority. WRITE to WRITE Command Interval (same ROW address in same bank) CK Command Din in B3 Address in B1 in B2 BA ACTV Row Column A WRIT WRIT Column B in A0 in B0 Bank0 Active Column =A Write Column =B Write Burst Write Mode Burst Length = 4 Bank 0 2. S ame b ank , d if fer en t RO W ad dr es s : Whe n t he R OW addr es s cha nges , cons e cut i ve wr it e com m ands ca nnot be exe cut e d; i t i s nec es s a ry t o s epa ra te t he t wo wr it e com m ands wi t h a pre cha rge com m and and a bank-active command. 3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 cl oc k, provi de d t hat t he ot her bank i s i n t he bank- ac ti ve s t at e. In t he ca s e of burs t wr it e , t he s ec ond wr it e command has priority. WRITE to WRITE Command Interval (different bank) CK Command Din in B3 Address in B1 in B2 BA ACTV Row 0 Row 1 ACTV WRIT Column A in A0 in B0 Bank0 Active Bank3 Active Bank0 Write Bank3 Write WRIT Column B Burst Write Mode Burst Length = 4

Read command to Write command interval: 1. S ame b ank , s ame RO W ad dr es s : Whe n t he wr it e com m and i s exe cut e d at t he s am e R OW addr es s of t he same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, DQMB must be set High so that the output buffer becomes High-Z before data input. READ to WRITE Command Interval (1) CK Command Dout in B2 in B3 READ WRIT in B0 in B1 High-Z Din CL=2 CL=3 DQMB Burst Length = 4 Burst write READ to WRITE Command Interval (2) CK Command Dout READ WRIT Din CL=2 CL=3 DQMB High-Z 2 clock High-Z 2. S ame b ank , d if fer en t RO W ad dr es s : Whe n t he R OW addr es s cha nges , cons e cut i ve wr it e com m ands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-active command. 3. Di ff er en t b ank : Whe n t he bank cha nges , t he wr it e com m and ca n be per form e d af t er an i nt erva l of no l es s than 1 clock, provided that the other bank is in the bank-active state. However, DQMB must be set High so that the output buffer becomes High-Z before data input.

Write command to Read command interval: 1. S ame b ank , s ame RO W ad dr es s : Whe n t he re ad com m and i s exe cut e d at t he s am e R OW addr es s of t he same bank as the preceding write command, the read command can be performed after an interval of no less than 1 cl oc k. Howe ver , i n t he ca s e of a burs t wr it e , dat a wi l l cont i nue t o be wr it t en unt i l one cyc l e bef ore t he re ad command is executed. WRITE to READ Command Interval (1) CK Command Din WRIT READ in A0 out B1 out B2 out B3out B0Dout Column = A Write Column = B Read Column = B Dout CE Latency DQMB Burst Write Mode CE Latency = 2 Burst Length = 4 Bank 0 WRITE to READ Command Interval (2) CK Command Din WRIT READ in A0 out B1 out B2 out B3out B0Dout Column = A Write Column = B Read Column = B Dout CE Latency in A1 DQMB Burst Write Mode CE Latency = 2 Burst Length = 4 Bank 0 2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be exe cut e d; i t i s nec es s a ry t o s epa ra te t he t wo com m ands wi t h a pre cha rge com m and and a bank- ac ti ve command. 3. Di ff er en t b ank : Whe n t he bank cha nges , t he re ad com m and ca n be per form e d af t er an i nt erva l of no l es s than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address).

Read with auto precharge to Read command interval 1. Di ff er en t b ank : Whe n s om e banks ar e i n t he ac t ive s t at e, t he s ec ond re ad com m and (a not her bank) i s exe cut e d. Eve n whe n t he fi rs t re ad wi t h aut o- prec har ge i s a burs t re ad t hat i s not yet fi ni s hed, t he dat a re ad by t he s ec ond com m and i s val i d. The i nt erna l aut o- prec har ge of one bank s t art s at t he next cl oc k of t he s ec ond command. Read with Auto Precharge to Read Command Interval (Different bank) CK Command BA Dout READ A READ out A0 out A1 out B0 out B1 CE Latency = 3 Burst Length = 4 bank0 Read A bank3 Read Note: Internal auto-precharge starts at the timing indicated by " ". 2. Same bank: The consecutive read command (the same bank) is illegal. Write with auto precharge to Write command interval 1. Di ff er en t b ank : Whe n s om e banks ar e i n t he ac t ive s t at e, t he s ec ond wr it e com m and (a not her bank) i s executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank starts at the next clock of the second command . Write with Auto Precharge to Write Command Interval (Different bank) CK Command BA Din WRIT A WRIT in B1 in B2 in B3in A0 in A1 in B0 Burst Length = 4 bank0 Write A bank3 Write Note: Internal auto-precharge starts at the timing indicated by " ". 2. Same bank: The consecutive write command (the same bank) is illegal.

Read with auto precharge to Write command interval Di ff er en t b ank : Whe n s om e banks ar e i n t he ac t ive s t at e, t he s ec ond wr it e com m and (a not her bank) i s executed. However, DQMB must be set High so that the output buffer becomes High-Z before data input. The internal auto-precharge of one bank starts at the next clock of the second command. Read with Auto Precharge to Write Command Interval (Different bank) CK Command BA Dout Din CL = 2 CL = 3 READ A WRIT in B0 in B1 in B2 in B3 Burst Length = 4bank0 Read A bank3 Write Note: Internal auto-precharge starts at the timing indicated by " ". DQMB High-Z 2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command.

Write with auto precharge to Read command interval 1. Di ff er en t b ank : Whe n s om e banks ar e i n t he ac t ive s t at e, t he s ec ond re ad com m and (a not her bank) i s exe cut e d. Howe ver , i n ca s e of a burs t wr it e , dat a wi l l cont i nue t o be wr it t en unt i l one cl oc k bef ore t he re ad command is executed. The internal auto-precharge of one bank starts at the next clock of the second command. Write with Auto Precharge to Read Command Interval (Different bank) CK Command BA Dout Din WRIT A READ out B0 out B1 out B2 out B3 CE Latency = 3 Burst Length = 4 bank0 Write A bank3 Read Note: Internal auto-precharge starts at the timing indicated by " ". DQMB in A0 2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command.

Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output buffer then becomes High-Z after t he cl oc ks def i ned by l HZ P, t her e i s a ca s e of i nt err upti on t o burs t re ad dat a out put wi l l be i nt err upte d, i f t he precharge command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (same bank): To output all data CE Latency = 2, Burst Length = 4 CK Command Dout READ PRE/PALL out A0 out A1 out A2 out A3 CL=2 l = -1 cycleEP CE Latency = 3, Burst Length = 4 CK Command Dout READ PRE/PALL out A0 out A1 out A2 out A3 CL=3 l = -2 cycle EP

READ to PRECHARGE Command Interval (same bank): To stop output data CE Latency = 2, Burst Length = 1, 2, 4, 8, full page burst CK Command Dout READ PRE/PALL out A0 High-Z lHZP = 2 CE Latency = 3, Burst Length = 1, 2, 4, 8, full page burst CK Command Dout READ PRE/PALL out A0 High-Z lHZP = 3

Wri t e com man d to Pr ech arge com man d i nt er val (s am e b ank ): Whe n t he pre cha rge com m and i s exe cut e d for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cl oc k. Howe ver , i f t he burs t wr it e oper at i on i s unfi ni s hed, t he i nput dat a m us t be m as ke d by m ea ns of DQM B for assurance of the clock defined by tDPL. WRITE to PRECHARGE Command Interval (same bank): Burst Length = 4 (To stop write operation) CK Command Din WRIT PRE/PALL tDPL DQMB CK in A0 in A1 Command Din WRIT PRE/PALL DQMB tDPL Burst Length = 4 (To write all data) CK in A0 in A1 in A2 Command Din WRIT PRE/PALL in A3 DQMB tDPL

Bank active command interval: 1. Same bank: The interval between the two bank-active commands must be no less than t RC. Bank Active to Bank Active for Same Bank CK Command Address BA Bank 0 Active ACTV ROW ACTV ROW Bank 0 Active t RC 2. In the case of different bank-active commands: The interval between the two bank-active commands must be no less than tRRD. Bank Active to Bank Active for Different Bank CK Command Address BA Bank 0 Active Bank 3 Active ACTV ROW:0 ACTV ROW:1 t RRD

Mod e re gi s ter s et to B ank -ac ti ve com man d i nt er val: The i nt erva l bet we en s et t i ng t he m ode re gi st e r and executing a bank-active command must be no less than lRSA. CK Command Address Mode Register Set Bank Active MRS ACTV I RSA BS & ROWCODE DQMB Control The DQMB mask the DQ data. The timing of DQMB is different during reading and writing. Re adi n g: Whe n dat a i s re ad, t he out put buff er ca n be cont r oll e d by DQM B . B y s et t i ng DQM B t o Low, t he out put buff er bec om es Low- Z, ena bl ing dat a out put . B y s et t i ng DQM B t o Hi gh, t he out put buff er bec om es High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQMB during reading is 2 clocks. Wri t in g: Input dat a ca n be m as ke d by DQM B . B y s et t i ng DQM B t o Low, dat a ca n be wr it t en. In addi t i on, when DQMB is set to High, the corresponding data is not written, and the previous data is held. The latency of DQMB during writing is 0 clock.

l = 2 Latency out 3 DOD DQMB High-Z Writing CK Din in 0 in 1 l = 0 Latency in 3 /;/; DID DQMB

Au to-r ef re sh : Al l t he banks m us t be pre cha rged bef ore exe cut i ng an aut o- ref res h com m and. S inc e t he aut o- refresh command updates the internal counter every time it is executed and determines the banks and the ROW addr es s es t o be re fre s hed, ext e rnal addr es s s pec i fi ca ti on i s not re qui red. The re fre s h cyc l e i s 4096 cyc l es / 64 m s . (4096 cyc l es ar e re qui red t o re fre s h al l t he R OW addr es s es . ) The out put buff er bec om es Hi gh-Z af t er aut o- ref res h s t art . In addi t i on, s i nce a pre cha rge has bee n com pl et e d by an i nt erna l oper at i on af t er t he aut o- refresh, an additional precharge operation by the precharge command is not required. S el f-r ef re sh : Af te r exe cut i ng a s el f- re fre s h com m and, t he s el f- re fre s h oper at i on cont i nues whi l e C KE i s hel d Low. Dur ing s el f- re fre s h oper at i on, al l R OW addr es s es ar e re fre s hed by t he i nt erna l re fre s h t i me r. A s el f- re fre s h i s t er mi na te d by a s el f- re fre s h exi t com m and. B efor e and af t er s el f- re fre s h m ode, exe cut e aut o- ref res h to all refresh addresses in or within 64 ms period on the condition (1) and (2) below. (1) Enter self-refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. (2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 µs after exiting from self-refresh mode. Others Powe r- down mod e: The S DRA M m odul e ent e rs powe r-dow n m ode whe n C KE goes Low i n t he ID LE s t at e. In powe r down m ode, powe r cons um pt i on i s s uppre s se d by dea ct i vat i ng t he i nput i ni ti a l ci r cui t . P ower down m ode cont i nues whi l e C KE i s hel d Low. In addi t i on, by s et t i ng C KE t o Hi gh, t he S DRA M m odul e exi t s fr om the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not performed. Cl ock s us p en d mod e: B y dri vi ng C KE t o Low duri ng a bank- ac ti ve or re ad/ wr it e oper at i on, t he S DRA M m odul e ent e rs cl oc k s us pend m ode. Dur ing cl oc k s us pend m ode, ext e rnal i nput s i gnal s ar e i gnore d and t he i nt erna l s t at e i s m ai nt ai ned. Whe n C KE i s dri ve n Hi gh, t he S DRA M m odul e t er mi na te s cl oc k s us pend m ode, and command input is enabled from the next clock. For details, refer to the "CKE Truth Table". Power-up sequence: The SDRAM module should be gone on the following sequence with power up. The CK, CKE, S, DQMB and DQ pins keep low till power stabilizes. The CK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence. The CKE and DQMB is driven to high between power stabilizes and the initialization sequence. This SDRAM module has VCC clamp diodes for CK, CKE, S, DQMB and DQ pins. If these pins go high before power up, the large current flows from these pins to VCC through the diodes. Initialization sequence: When 200 µs or more has past after the above power-up sequence, all banks must be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). S et t he m ode re gi st e r s et com m and (M R S) t o i ni ti a li z e t he m ode re gi st e r. We re com m end t hat by kee pi ng DQM B t o Hi gh, t he out put buff er bec om es Hi gh-Z duri ng Ini t i al i za ti on s eque nce , t o avoi d DQ bus cont e nti on on memory system formed with a number of device.

Power up sequence Initialization sequence 100 μs 0 V Low Low Low CKE, DQMB CK S, DQ 200 μs Power stabilize

S tRAS tRCD tCHtCS /;/; /;/; /;/;/;/;/;/; /;/; /;/; /;/; /;/; /;/; /;/;/;/; /;/; /;/; /;/; /;/;/;/;/;/; /;/; /;/; /;/;/;/;/; /;/; /;/; /;/;/; /;/; RE CE W A12/A13 /;/;/;/;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; A10 Address DQMB Din Dout /;/; /;/; tCHtCS tCKH t tCK tAC tAC CKL tAC tOHtOH tOHtOH tRP t RC CE latency = 2 Burst length = 4 Bank 0 access = V or V /;/; /;/; tCHtCS tCHtCS tCHtCS tAHtAS tAHtAS tAHtAS tCHtCS tCHtCS tCHtCS tAHtAS tAHtAS tCHtCStCHtCS tCHtCS tCHtCS tCHtCS tAHtAS tAHtAS tAHtAS tCHtCS tCHtCS tCHtCS tCHtCS tAHtAS tAHtAS tAHtAS tAC tLZ VIH IH IL tHZ

S tRAS tRCD /;/; RE CE W A12/A13 /;/;/;/; /;/; A10 Address Din Dout tCHtCS tCKH t tCK tDH tDH CKL tDH t DHtDStDS tDStDS tRP tRC tDPL Bank 0 Write tCHtCS Bank 0 Active Bank 0 Precharge tCHtCS tCHtCS tCHtCS tCHtCS tCHtCS tCHtCS tCHtCS tAHtAStAHtAS tAHtAS tAHtAS tAHtAS tAHtAS tCHtCS tAHtAS tCHtCS tCHtCS tCHtCS tAHtAS tCHtCS tAHtAS tCHtCS tCHtCS tCHtCS tAHtAS tAHtAS /;/; /;/;/; /;/; /;/; /;/; /;/; /;/;/; /;/; /;/; /;/; VIH CE latency = 2 Burst length = 4 Bank 0 access = V or V IH IL DQMB

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CK CKE S RE CE W BA Address DQMB Din Dout /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/;/; /;/; High-Z b b+3 b’ b’+1 b’+2 b’+3 l valid C: b’ RSA code l RCDl RP Precharge If needed Mode register Set Bank 3 Active Bank 3 Read /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/;/;/; /;/; /;/; /;/; /;R: b C: b /;/; /;/; /;/; Output mask VIH l = 3 CE latency = 3 Burst length = 4 = V or V /;/; IH IL RCD

0 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 0 /;/; /;/; R:a C:a R:b C:b C:b' C:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 CKE RE S CE W Address DQMB Dout Din CK BA /;/;/;/;/; /;/; /;/; /;/; /;/;/;/; /;/;/;/; R:a C:a R:b C:b C:b' C:b" /;/;/; a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 /;/; /;/; /;/; /;/;/;/; /;/; /;/; /;/;/;/;/;/; /;/; /;/;/;/;/; /;/;/;/; /;/; /;/;/; Bank 0 Active Bank 0 Read Bank 3 Active Bank 3 Read Bank 3 Read Bank 3 Read Bank 0 Precharge Bank 3 Precharge Bank 0 Active Bank 0 Write Bank 3 Active Bank 3 Write Bank 3 Write Bank 3 Write Bank 0 Precharge Bank 3 Precharge CKE RE S CE W Address DQMB Din Dout BA High-Z High-Z /;/; VIH VIH Read cycle RE-CE delay = 3 CE latency = 3 Burst length = 4 = V or V IH IL Write cycle RE-CE delay = 3 CE latency = 3 Burst length = 4 = V or V IH IL

/;/; /;/;/; /;/; 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 /;/; /;/; /;R:a C:a R:b C:a' /;/; /;/; /;/; R:a C:a C:a a a a a /;/; /;/; /;/; /;/; /;/;/;/;/;/;/; Bank 0 Active Bank 0 Read Bank 3 Active Bank 0 Write Bank 0 Precharge Bank 3 Precharge Bank 0 Active Bank 0 Read Bank 0 Write Bank 0 Precharge /;/;/;/; R:b Bank 3 Active /;/;/;/;/; /; /; C:a Bank 0 Read a a+1 a+2 a+3 /;/;/;/;/;/;/;/;/; Bank 0 Write Bank 0 Write CKE RE S CE W Address DQMB Din Dout CK BA CKE RE S CE W Address DQMB BA /;/;/;/;/; C:b bc a+1 a+3 a+1 a+2 a+3 C:c VIH VIH Read/Single write RE-CE delay = 3 CE latency = 3 Burst length = 4 = V or V IH IL Din Dout

/;/;/;/;/;/;/;/;/; /;/;/;/; /;/;/;/; /;/;/;/; 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 /;/; /;/; R:a C:a R:b C:a' /;/;/; R:a C:a C:a /;/; /;/; a a+1 a+2 a+3 a+1 a a+1 a+2 a+3 /;/;/;/; /;/; /;/; /;/; /;/;/; /;/; /;/;/;/; Bank 0 Active Bank 0 Read Bank 0 Write Bank 0 Precharge /;/;/;/;/;/; R:b Bank 3 Active /;/;/;/;/; /;/;/;/;/; CKE RE S CE W Address DQMB CK BA CKE RE S CE W Address DQMB BA a+1 a+2 a+3 a a+3 a Bank 0 Active Bank 0 Read Bank 3 Active Clock suspend Bank 0 Write Bank 0 Precharge Bank 3 Precharge /;/; VIH Read/Burst write RE-CE delay = 3 CE latency = 3 Burst length = 4 = V or V /;/; IH IL Din Dout Din Dout

Full Page Read/Write Cycle High-Z R:a C:a R:b /;/;/;/;/; R:a C:a R:b High-Z /;/; /;/; /;/;/;/;/; /;/;/;/;/;/;/;/; /;/; /;/; /;/; /;/;/;/; Bank 0 Active Bank 0 Read Bank 3 Active Burst stop Bank 3 Precharge Bank 0 Active Bank 0 Write Bank 3 Active Burst stop Bank 3 Precharge /;/;/; CKE RE S CE W Address DQMB Din Dout CK BA CKE RE S CE W Address DQMB BA VIH VIH a a+1 a+2 a+3 Read cycle RE-CE delay = 3 CE latency = 3 Burst length = full page = V or V IH IL Write cycle RE-CE delay = 3 CE latency = 3 Burst length = full page = V or V IH IL a a+1 a+2 a+3 a+6a+5a+4Din Dout

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CK CKE S CE W BA Address DQMB Din Dout /;/; /;/; /;/; /;/; /;/; /;/; /;/; High-Z RP /;/; /;/; /;/; Precharge If needed Auto Refresh Active Bank 0 t RCt RCt Auto Refresh Read Bank 0 /;/; /;/; /;/; R:a C:aA10=1 RE /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; a a+1 VIH Refresh cycle and Read cycle RE-CE delay = 2 CE latency = 2 Burst length = 4 = V or V IH IL Self Refresh Cycle CK CKE S RE CE W BA Address DQMB Din Dout /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/;/;/; /;/; Precharge command If needed Self refresh entry command Auto refresh Self refresh exit ignore command or No operation /;/; /;/; /;/; /;/; CKE Low /;/; A10=1 RCtRPt /;/; /;/; Self refresh cycle RE-CE delay = 3 CE latency = 3 Burst length = 4 = V or V IH IL High-Z Next clock enable /;/;/; RCt Next clock enable /;/; lSREX Self refresh entry command

/;/;/; /;/;/;/;/; /;/; /;/; /;/; 0123 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 0 /;/; /;/;/;/; /;/; /;/; R:a C:a R:b a a+1 a+2 a+3 b b+1 b+2 /;/;/;/; /;/; /;/; /;/; R:a C:a R:b C:b /;/; /;/; /;/; a a+1 a+2 b b+1 b+2 b+3 /;/; /;/; C:b /;/;/; Bank0 Active Active clock suspend start Active clock supend end Bank0 Read Bank3 Active Read suspend start Read suspend end Bank0 Precharge Bank3 Read Earliest Bank3 Precharge Bank0 Write Bank0 Active Active clock suspend start Active clock suspend end Bank3 Active Write suspend start Write suspend end Bank3 Write Bank0 Precharge Earliest Bank3 Precharge /;/; /;/; /;/; b+3 /;/; /;/; /;/; /;/;/;/;/; /;/; /;/;/;/;/;/;/;/;/; CKE RE S CE W Address DQMB CK BA CKE RE S CE W Address DQMB BA a+3 High-Z High-Z /;/; /;/; /;/; /;/; /;/; tCES tCEH tCES Read cycle RE-CE delay = 2 CE latency = 2 Burst length = 4 = V or V IH IL Write cycle RE-CE delay = 2 CE latency = 2 Burst length = 4 = V or V /;/; IH IL Dout Din Dout Din

S RE CE W BA Address DQMB Din Dout /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; /;/; Precharge command If needed Power down entry Active Bank 0 Power down mode exit /;/; /;/; CKE Low R: a /;/; /;/; A10=1 RPt /;/; /;/; /;/; High-Z Power down cycle RE-CE delay = 3 CE latency = 3 Burst length = 4 = V or V IH IL Initialization Sequence 7891 0 52 53 5448 49 50 51 /;/; Auto Refresh Bank active If needed RCt RCt Auto Refresh Valid 0123456 CK CKE S RE CE W Address DQMB DQ /;/; t valid RSA tRP All banks Precharge Mode register Set /;/; VIH VIH /; /; High-Z /;/; /;/; /;/; /;/; /;/; /;/; /;/;/; /;/; /;/; code

1.00 ± 0.10 0.039 ± 0.004 Detail A

0.25 Max

0.010 Max

2.55 Min

0.100 Min

0.60 ± 0.05 0.024 ± 0.002 0.80 0.031 2-R2.00 2-R0.079 3.70 0.146 23.20 0.913 4.60 0.181 2.10 0.083 32.80 1.291 4.00 ± 0.10 0.157 ± 0.004

3.80 Max

0.150 Max

(Datum -A-) 1.50 ± 0.10 0.059 ± 0.004 4.00 ± 0.10 0.157 ± 0.004 (DATUM -A-) Detail B R0.75 R0.030 2.5 0.098

2.00 Min

0.079 Min

(back) 2R3.00 Min 2R0.118 Min

4.00 Min

0.157 Min

3.20 Min

0.126 Min

3.30 0.130 23.20 0.913 4.60 0.1812.50 0.098 32.80 1.291 (Datum -A-) 31.75 1.250 20.00 0.787 67.60 2.661 AB Component area (front) Unit: mm inch

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