HB52D88GB-B6F

HB52D88GB-F ELPIDA | Alldatasheet

Document overview

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Technical content

Features

• 144-pin Zig Zag Dual tabs socket type ¾ Outline: 38.00 mm (Length) · 30.00 mm (Height) · 3.80 mm (Thickness) ¾ Lead pitch: 0.50 mm
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Data bus width: · 64 Non parity
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length : 1/2/4/8/full page
• 2 variations of burst sequence ¾ Sequential (BL = 1/2/4/8/full page) ¾ Interleave (BL = 1/2/4/8)

• Programmable CE latency : 2/3 (HB52D88GB-A6F/A6FL) : 3 (HB52D88GB-B6F/B6FL)
• Byte control by DQMB
• Refresh cycles: 4096 refresh cycles/64 ms
• 2 variations of refresh ¾ Auto refresh ¾ Self refresh
• Low self refresh current: HB52D88GB-A6FL/B6FL (L-version)
• Full page burst length capability ¾ Sequential burst ¾ Burst stop capability

Ordering Information

Type No. Frequency CE latency Package Contact pad HB52D88GB-A6F HB52D88GB-B6F HB52D88GB-A6FL HB52D88GB-B6FL

100 MHz

Micro DIMM (144-pin) Gold Pin Arrangement Front Side Back Side 2pin 144pin 1pin 143pin

Pin Arrangement (cont.) Front side Back side Pin No. Signal n ame Pin No. Signal n ame Pin No. Signal n ame Pin No. Signal n ame 1V SS 73 NC 2 V SS 74 CK1

3 DQ0 75 V SS 4 DQ32 76 V SS

5 DQ1 77 NC 6 DQ33 78 NC

7 DQ2 79 NC 8 DQ34 80 NC

9 DQ3 81 V CC 10 DQ35 82 V CC

11 V CC 83 DQ16 12 V CC 84 DQ48

13 DQ4 85 DQ17 14 DQ36 86 DQ49

15 DQ5 87 DQ18 16 DQ37 88 DQ50

17 DQ6 89 DQ19 18 DQ38 90 DQ51

19 DQ7 91 V SS 20 DQ39 92 V SS

21 V SS 93 DQ20 22 V SS 94 DQ52

23 DQMB0 95 DQ21 24 DQMB4 96 DQ53

25 DQMB1 97 DQ22 26 DQMB5 98 DQ54

27 V CC 99 DQ23 28 V CC 100 DQ55

29 A0 101 V CC 30 A3 102 V CC

31 A1 103 A6 32 A4 104 A7

33 A2 105 A8 34 A5 106 A13 (BA0)

35 V SS 107 V SS 36 V SS 108 V SS

37 DQ8 109 A9 38 DQ40 110 A12 (BA1)

39 DQ9 111 A10 (AP) 40 DQ41 112 A11

41 DQ10 113 V CC 42 DQ42 114 V CC

43 DQ11 115 DQMB2 44 DQ43 116 DQMB6

45 V CC 117 DQMB3 46 V CC 118 DQMB7

47 DQ12 119 V SS 48 DQ44 120 V SS

49 DQ13 121 DQ24 50 DQ45 122 DQ56

51 DQ14 123 DQ25 52 DQ46 124 DQ57

53 DQ15 125 DQ26 54 DQ47 126 DQ58

55 V SS 127 DQ27 56 V SS 128 DQ59

57 NC 129 V CC 58 NC 130 V CC

59 NC 131 DQ28 60 NC 132 DQ60

61 CK0 133 DQ29 62 CKE0 134 DQ61

63 V CC 135 DQ30 64 V CC 136 DQ62

65 RE 137 DQ31 66 CE 138 DQ63

Pin No. Signal n ame Pin No. Signal n ame Pin No. Signal n ame Pin No. Signal n ame

67 W 139 V SS 68 NC 140 V SS

69 S0 141 SDA 70 NC 142 SCL

71 NC 143 V CC 72 NC 144 V CC

¾ Row addressA0 to A11 ¾ Column address A0 to A8 A12/A13 Bank select address BA1, BA0 DQ0 to DQ63 Data-input/output S0 Chip select RE Row address asserted bank enable CE Column address asserted W Write enable DQMB0 to DQMB7 Byte input/output mask CK0/CK1 Clock input CKE0 Clock enable SDA Data-input/output for serial PD SCL Clock input for serial PD VCC Power supply VSS Ground NC No connection

Serial PD Matrix*1 Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

0 Number of bytes used by

1 Total SPD memory size 000010000 8 256 byte

2 Memory type 000001000 4 SDRAM

3 Number of row addresses bits 000011000 C 1 2

4 Number of c ol umn addr es ses b i t s 000010010 9 9

5 Number of banks 000000010 1 1

6 Module data width 010000004 0 6 4

7 Module data width (continued) 000000000 0 0 ( + )

8 Module interface signal levels 000000010 1 LVTTL

9 SDRAM cycle time

(highest CE latency) 10 ns 10100000A 0 C L = 3

10 SDRAM access from Clock

(highest CE latency) 6 ns 011000006 0 C L = 3

11 Module configuration type 000000000 0 Non parity

12 Refresh rate/type 100000008 0 Normal

(15.625 ms) Self refresh

13 SDRAM width 000100001 0 8 M · 16

14 Error checking SDRAM width 000000000 0 —

15 SDRAM device attributes:

minimum clock delay for back- to-back random column addresses 000000010 1 1 C L K

16 SDRAM device attributes:

100011118 F 1 , 2 , 4 , 8 , full

17 SDRAM device attributes:

18 SDRAM device attributes:

000001100 6 2 , 3

19 SDRAM device attributes:

20 SDRAM device attributes:

21 SDRAM module attributes 000000000 0 Unbuffer

22 SDRAM device attributes:

000011100 E V CC – 10%

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

23 SDRAM cycle time

(2nd highest CE latency) (-A6F/A6FL) 10 ns 10100000A 0 CL=2 (-B6F/B6FL) 15 ns 11110000F 0

24 SDRAM access from Clock

(2nd highest CE latency) (-A6F/A6FL) 6 ns 011000006 0 CL=2 (-B6F/B6FL) 8 ns 100000008 0

25 SDRAM cycle time

(3rd highest CE latency) Undefined 000000000 0

26 SDRAM access from Clock

(3rd highest CE latency) Undefined 000000000 0

27 Minimum row precharge time 000101001 4 2 0 n s

28 Row active to row active min 000101001 4 2 0 n s

29 RE to CE delay min 000101001 4 2 0 n s

30 Minimum RE pulse width 001100103 2 5 0 n s

31 Density of each bank on

32 Address and command signal

33 Address and command signal

34 Data signal input setup time 001000002 0 2 n s

35 Data signal input hold time 000100001 0 1 n s

36 to 61 Superset information 000000000 0 Future use 62 SPD data revision code 000100101 2 Rev. 1.2A

63 Checksum for bytes 0 to 62

(-A6F/A6FL)

000011010 D 1 3

(-B6F/B6FL) 011111017 D 1 2 5

64 Manuf ac turer’ s JE DE C ID c o d e 000001110 7 HITACHI

65 to 71 Manuf ac turer’ s JE DE C ID c o d e 000000000 0 8bit code)

73 Manufacturer’s part number 010010004 8 H

74 Manufacturer’s part number 010000104 2 B

75 Manufacturer’s part number 001101013 5 5

76 Manufacturer’s part number 001100103 2 2

77 Manufacturer’s part number 010001004 4 D

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

78 Manufacturer’s part number 001110003 8 8

79 Manufacturer’s part number 001110003 8 8

80 Manufacturer’s part number 010001114 7 G

81 Manufacturer’s part number 010000104 2 B

82 Manufacturer’s part number 001011012 D —

83 Manufacturer’s part number

(-A6F/A6FL) 010000014 1 A (-B6F/B6FL) 010000104 2 B

84 Manufacturer’s part number 001101103 6 6

85 Manufacturer’s part number 010001104 6 F

86 Manufacturer’s part number

(L-version)

010011004 C L

Manufacturer’s part number001000002 0 (Space)

87 Manufacturer’s part number 001000002 0 (Space)

88 Manufacturer’s part number 001000002 0 (Space)

89 Manufacturer’s part number 001000002 0 (Space)

90 Manufacturer’s part number 001000002 0 (Space)

(BCD)*4 (BCD)*4 95 to 98 Assembly serial number * 6

126 Intel specification frequency 011001006 4 100 MHz

127 Intel specification CE# latency

(-A6F/A6FL) 11000111C 7 C L = 2 , 3 (-B6F/B6FL) 11000101C 5 C L = 3 Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High” These SPD are based on Intel specification (Rev.1.2A). 2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119. 3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on ASCII code.) 4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is “Binary Coded Decimal”. 5. All bits of 99 through 125 are not defined (“1” or “0”). 6. Bytes 95 through 98 are assembly serial number.

RAS (D0 to D3) CAS (D0 to D3) A0 to A11 A0 to A11 (D0 to D3) CKE0 CKE (D0 to D3) VCC VCC (D0 to D3, U0) VSS VSS (D0 to D3, U0) C100-C103 Serial PD SDA VSS SCL SDASCL Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. CK0 CLK (D0)

8 N0, N1

8 N2, N3

CLK (D1) C0-C7 CK1 CLK (D2) CLK (D3) RE CE A13 (D0 to D3) BA1 A12 (D0 to D3) BA0 W CS DQMB4 DQ32 to DQ39

8 N8, N9

8 N10, N11

8 N4, N5

8 N6, N7

8 N12, N13

8 N14, N15

• D0 to D3 : HM5212165 U0 : 2-kbit EEPROM C0 to C7 : 0.33 µF C100 to C103 : 0.1 µF N0 to N15 : Network resistors (10 W )

Parameter Symbol Value Unit Note Voltage on any pin relative to VSS VT –0.5 to VCC + 0.5 (£ 4.6 (max)) Supply voltage relative to VSS VCC –0.5 to +4.6 V 1 Short circuit output current Iout 50 mA Power dissipation P T 8.0 W Operating temperature Topr 0 to +65 °C Storage temperature Tstg –55 to +125 °C Note: 1. Respect to VSS . DC Operating Conditions (Ta = 0 to +65°C) Parameter Symbol Min Max Unit Notes Supply voltage V CC 3.0 3.6 V 1, 2 VSS 00V3 Input high voltage V IH 2.0 V CC + 0.3 V 1, 4, 5 Input low voltage V IL –0.3 0.8 V 1, 6 Notes: 1. All voltage referred to VSS 2. The supply voltage with all VCC pins must be on the same level. 3. The supply voltage with all VSS pins must be on the same level. 4. CK, CKE, S, DQMB, DQ pins: VIH (max) = VCC + 0.5 V for pulse width £ 5 ns at VCC . 5. Others: VIH (max) = 4.6 V for pulse width £ 5 ns at VCC . 6. VIL (min) = –1.0 V for pulse width £ 5 ns at VSS .

V IL/VIH Clamp (Component characteristic) This SDRAM component has VIL and VIH clamp for CK, CKE, S, DQMB and DQ pins. Minimum V IL Clamp Current VIL (V) I (mA) –2 –32 –1.8 –25 –1.6 –19 –1.4 –13 –1.2 –8 –1 –4 –0.9 –2 –0.8 –0.6 –0.6 0 –0.4 0 –0.2 0 VIL (V) I (mA) –1.5 –1 –0.5–5 –15 –10 –25 –20 –30 –35 –20

Minimum V IH Clamp Current VIH (V) I (mA) VCC + 2 10 VCC + 1.8 8 VCC + 1.6 5.5 VCC + 1.4 3.5 VCC + 1.2 1.5 VCC + 1 0.3 VCC + 0.8 0 VCC + 0.6 0 VCC + 0.4 0 VCC + 0.2 0 VCC + 0 0 VIH (V) VCC + 0 V CC + 1 V CC + 2VCC + 0.5 V CC + 1.5 I (mA)

IOL /IOH Characteristics (Component characteristic) Output Low Current (IOL ) IOL IOL Vout (V) Min (mA) Max (mA) 00 0 0.4 27 71 0.65 41 108 0.85 51 134 1 58 151 1.4 70 188 1.5 72 194 1.65 75 203 1.8 77 209 1.95 77 212 3 80 220 3.45 81 223 IOL (mA) Vout (V) 250 200 150 100 0 0.5 1 1.5 2 2.5 3 3.5 min max

Output High Current (IOH ) (Ta = 0 to 65˚C, VCC = 3.0 V to 3.45 V, VSS = 0 V) IOH IOH Vout (V) Min (mA) Max (mA) 3.45 — –3 3.3 — –28 3 0 –75 2.6 –21 –130 2.4 –34 –154 2 –59 –197 1.8 –67 –227 1.65 –73 –248 1.5 –78 –270 1.4 –81 –285 1 –89 –345 0 –93 –503 IOH (mA) Vout (V) –100 –200 –300 –500 –600 –400 0.5 1 1.5 2 2.5 3 min max 3.50

DC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V – 0.3 V, VSS = 0 V) HB52D88GB -A6F/B6F/A6FL/B6FL Parameter Symbol Min Max Unit Test conditions Notes Operating current I CC1 — 480 mA Burst length = 1 tRC = min 1, 2, 3 Standby current in power down ICC2P — 12 mA CKE0 = V IL, tCK = 12 ns 6 Standby current in power down (input signal stable) ICC2PS — 8 mA CKE0 = V IL, tCK = ¥ 7 Standby current in non power down ICC2N — 60 mA CKE0, S = VIH, tCK = 12 ns Active standby current in power down ICC3P — 24 mA CKE0, S = VIH, tCK = 12 ns 1, 2, 6 Active standby current in non power down ICC3N — 140 mA CKE0, S = VIH, tCK = 12 ns 1, 2, 4 Burst operating current I CC4 — 480 mA t CK = min, BL = 4 1, 2, 5 Refresh current I CC5 — 880 mA t RC = min 3 Self refresh current I CC6 — 8 mA V IH ‡ VCC – 0.2 V VIL £ 0.2 V Self refresh current (L-version) ICC6 — 6.4 mA Input leakage current I LI –10 10 mA0 £ Vin £ VCC Output leakage current I LO –10 10 mA0 £ Vout £ VCC DQ = disable Output high voltage V OH 2.4 — V I OH = –4 mA Output low voltage V OL — 0.4 V I OL = 4 mA Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK0/CK1 operating current. 7. After power down mode, no CK0/CK1 operating current. 8. After self refresh mode set, self refresh current.

Capacitance (Ta = 25°C, VCC = 3.3 V – 0.3 V) Parameter Symbol Max Unit Notes Input capacitance (Address) C IN 50 pF 1, 2, 4 Input capacitance (RE, CE, W, CK0/CK1, CKE0) C IN 50 pF 1, 2, 4 Input capacitance (S0)C IN 50 pF 1, 2, 4 Input capacitance (DQMB0 to DQMB7) C IN 20 pF 1, 2, 4 Input/Output capacitance (DQ0 to DQ63) C I/O 20 pF 1, 2, 3, 4 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. 3. DQMB = V IH to disable Data-out. 4. This parameter is sampled and not 100% tested.

AC Characteristics (Ta = 0 to 65˚C, VCC = 3.3 V – 0.3 V, VSS = 0 V) HB52D88GB -A6F/A6FL -B6F/B6FL Parameter Symbol PC100 Symbol Min Max Min Max Unit Notes System clock cycle time (CE latency = 2) t CK Tclk 10 — 15 — ns 1 (CE latency = 3) t CK Tclk 10 — 10 — ns CK high pulse width t CKH Tch 3 — 3 — ns 1 CK low pulse width t CKL Tcl 3 — 3 — ns 1 Access time from CK (CE latency = 2) t AC Tac — 6 — 8 ns 1, 2 (CE latency = 3) t AC Tac — 6 — 6 ns Data-out hold time t OH Toh 3 — 3 — ns 1, 2 CK to Data-out low impedance tLZ 2 — 2 — ns 1, 2, 3 CK to Data-out high impedance tHZ — 6 — 6 ns 1, 4 Data-in setup time t AS , tCS , tDS , tCES Tsi 2 — 2 — ns 1, 5, 6 CKE setup time for power down exit t CESP Tpde 2 — 2 — ns 1 Data-in hold time t AH , tCH , tDH , tCEH Thi 1 — 1 — ns 1, 5 Ref/Active to Ref/Active command period t RC Trc 70 — 70 — ns 1 Active to Precharge command period tRAS Tras 50 120000 50 120000 ns 1 Active command to column command (same bank) tRCD Trcd 20 — 20 — ns 1 Precharge to active command period tRP Trp 20 — 20 — ns 1 Write recovery or data-in to precharge lead time tDPL Tdpl 10 — 10 — ns 1 Active (a) to Active (b) command period tRRD Trrd 20 — 20 — ns 1 Transition time (rise and fall) tT 1515n s Refresh period t REF — 64 — 64 ms

Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.5 V. 2. Access time is measured at 1.5 V. Load condition is CL = 50 pF. 3. t LZ (min) defines the time at which the outputs achieves the low impedance state. 4. tHZ (max) defines the time at which the outputs achieves the high impedance state. 5. tCES define CKE setup time to CK rising edge except power down exit command. 6. tAS /tAH : Address, tCS /tCH : S, RE, CE, W, DQMB tDS /tDH : Data-in, tCES /tCEH : CKE Test Conditions

• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures tT 2.4 V 0.4 V0.8 V

2.0 Vinput

Relationship Between Frequency and Minimum Latency HB52D88GB Parameter -A6F/A6FL/B6F/B6FL Frequency (MHz) 100 tCK (ns) Symbol PC100 Symbol 10 Notes Active command to column command (same bank) l RCD 21 Active command to active command (same bank) lRC 7 = [l RAS + lRP ] Active command to precharge command (same bank) l RAS 51 Precharge command to active command (same bank) lRP 21 Write recovery or data-in to precharge command (same bank) lDPL Tdpl 1 1 Active command to active command (different bank) lRRD 21 Self refresh exit time l SREX Tsrx 1 2 Last data in to active command (Auto precharge, same bank) lAPW Tdal 4 = [l DPL + lRP ] Self refresh exit to command input l SEC 7 = [l RC ] Precharge command to high impedance (CE latency = 2) l HZP Troh 2 (CE latency = 3) l HZP Troh 3 Last data out to active command (auto precharge) (same bank) lAPR 1 Last data out to precharge (early precharge) (CE latency = 2) l EP –1 (CE latency = 3) l EP –2 Column command to column command l CCD Tccd 1 Write command to data in latency l WCD Tdwd 0 DQMB to data in l DID Tdqm 0 DQMB to data out l DOD Tdqz 2 CKE to CK disable l CLE Tcke 1 Register set to active command l RSA Tmrd 1

Parameter -A6F/A6FL/B6F/B6FL Frequency (MHz) 100 tCK (ns) Symbol PC100 Symbol 10 Notes S to command disable l CDD 0 Power down exit to command input l PEC 1 Burst stop to output valid data hold (CE latency = 2) l BSR 1 (CE latency = 3) l BSR 2 Burst stop to output high impedance (CE latency = 2) l BSH 2 (CE latency = 3) l BSH 3 Burst stop to write data ignore l BSW 0 Notes: 1. lRCD to lRRD are recommended value. 2. Be valid [DSEL] or [NOP] at next command of self refresh exit. 3. Except [DSEL] and [NOP].

CK0/CK1 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK rising edge. S0 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM modules, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A11 (input pins): Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active command cycle CK rising edge. Column address (AY0 to AY8) is determined by A0 to A8 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by A12/A13 (BA) is precharged. A12/A13 (input pin): A12/A13 is a bank select signal (BA). The memory array is divided into bank0, bank1, bank2 and bank3. If A12 is Low and A13 is Low, bank0 is selected. If A12 is High and A13 is Low, bank1 is selected. If A12 is Low and A13 is High, bank2 is selected. If A12 is High and A13 is HIgh, bank3 is selected. CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power- down and clock suspend modes. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written. DQ0 to DQ63 (DQ pins): Data is input to and output from these pins. V CC (power supply pins): 3.3 V is applied. V SS (power supply pins): Ground is connected. Detailed Operation Part Refer to the HM5212165F/HM5212805F-75/A60/B60 datasheet.

0.80 – 0.08 Detail A

3.80 Max

1.0 – 0.08 0.50 0.37 – 0.03 Detail B 4-R1.0 – 0.1 R1.0 – 0.1 5.0 – 0.1

2.00 Min

0.25 Max

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3.5 Min

2.5 Min

30.0 15.0

42.0 Max

1.0 Min

(38.0) 35.50 37.0 – 0.08 35.50 17.625 17.875 0.875 0.625 1.0 Min 1.0 Min Unit: mm 4.0 – 0.1 B Component area (front) A Component area (back)

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