FX1763XEJV

FX1763XEJV INFINEON | Alldatasheet

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Technical content

Rev. 1.1, 2014-10-30 IFX1763 Wide Input Range Low Noise 500mA LDO

IFX1763XEJ V PG-DSO-8 Exposed Pad 1763EV IFX1763XEJ V33 PG-DSO-8 Exposed Pad 1763EV33 IFX1763LD V PG-TSON-10 176LV IFX1763LD V33 PG-TSON-10 176LV33 PG-DSO-8 Exposed Pad PG-TSON-10 Data Sheet 2 Rev. 1.1, 2014-10-30 Wide Input Range Low Noise 500mA LDO IFX1763 1O v e r v i e w

Features

Low Noise down to 24 µ VRMS (BW = 10 Hz to 100 kHz)
500 mA Current Capability
Low Quiescent Current: 30 µA
Wide Input Voltage Range: 1.8 V to 20 V
2.5% Output Voltage Accuracy (over full temperature and load range)
Low Dropout Voltage: 320 mV
Very low Shutdown Current: < 1 µA
No Protection Diodes Needed
Fixed Output Voltage: 3.3 V
Adjustable Version with Output from 1.22 V to 20 V
Stable with ≥ 3.3 µF Output Capacitor
Stable with Aluminium, Tantalum or Ceramic Capacitors
Reverse Battery Protection
No Reverse Current
Overcurrent and Overtemperature Protected
DSO-8 Exposed Pad and TSON-10 Exposed Pad packages
Green Product (RoHS compliant)

Applications

Microcontroller Supply
Battery-Powered Systems
Noise Sensitive Instruments
Radar Applications
Image Sensors The IFX1763 is not qualified and manufactured accord ing to the requirements of Infineon Technologies with regards to automotive and/or transportation applications. For automotive applications please refer to the Infineon

Data Sheet 3 Rev. 1.1, 2014-10-30 The IFX1763 is a micropower, low noise, low dropout volt age regulator. The device is capable of supplying an output current of 500 mA with a dropout voltage of 320 mV. Designed for use in battery-powered systems, the low quiescent current of 30 µA makes it an ideal choice. A key feature of the IFX1763 is its low output noise. By adding an external 0.01 µF bypass capacitor output noise values down to 24 µVRMS over a 10 Hz to 100 kHz bandwidth can be reached. The IFX1763 voltage regulator is stable with output capacitors as sm all as 3.3 µF. Small ceramic capacitors can be used without the series resistance required by many other regulators. Its internal protection circuitry includes reverse battery protection, current limiting and reverse current protection. The IF X1763 comes as fixed output voltage 3.3 V as well as adjustable device with a 1.22 V reference voltage. It is available in a DSO-8 Exposed Pad and as well as in a TSON-10 Exposed Pad package.

Data Sheet 4 Rev. 1.1, 2014-10-30 IFX1763 Block Diagram

2 Block Diagram

Note: Pin numbers in the block diagrams refer to the DSO-8 EP package type. Figure 1 Block Diagram IFX1763 fixed voltage version Figure 2 Block Diagram IFX1763 adjustable version Bias Voltage reference Saturation Control Temperature Protection Over Current Protection IFX1763 IN EN GND BYP OUT SENSE Error Amplifier Bias Voltage reference Saturation Control Temperature Protection Over Current Protection IFX1763 ADJ IN EN GND BYP OUT ADJ Error Amplifier

Data Sheet 5 Rev. 1.1, 2014-10-30

3 Pin Configuration

3.1 Pin Assignment

Figure 3 Pin Configuration of IFX1763 in PG-DSO-8 Exposed Pad for fixed voltage and adjustable version Figure 4 Pin Configuration of IFX1763 in PG-TSO N-10 for fixed voltage and adjustable version IN NC GND OUT ADJ NC BYP EN IN NC GND OUT SENSE NC BYP EN IFX1763 XEJ V33 IFX1763XEJ V 9 9 IFX1763LD V33 OUT OUT NC SENSE BYP IN IN NC EN GND IFX1763LD V OUT OUT NC ADJ BYP IN IN NC EN GND 11 11

Data Sheet 6 Rev. 1.1, 2014-10-30 IFX1763 Pin Configuration

3.2 Pin Definitions and Functions

1 (DSO-8 EP) 1,2 (TSON-10) OUT Output. Supplies power to the load. For this pin a minimum output capacitor of 3.3 µF is required to prevent oscillations. Larger output capacitors may be required for applications with large transient loads in order to limit peak voltage transients or when the regulator is applied in conjunction with a bypass capacitor. For more details please refer to the section “Application Information” on Page 24. 2 (DSO-8 EP) 4 (TSON-10) SENSE (fix voltage version) Output Sense. For the fixed voltage version the SENSE pin is the input to the error amplifier. This allows to achieve an optimized regulation performance in case of small voltage drops Rp that occur between regulator and load. In applications where such drops are relevant they can be eliminated by connecting the SENSE pin directly at the load. In standard configurations the SENSE pin can be connected directly to the OUT pin. For further details please refer to the section “Kelvin Sense Connection” on Page 25. 2 (DSO-8 EP) 4 (TSON-10) ADJ (adjustable version) Adjust. For the adjustable version the ADJ pin is the input to the error amplifier. The ADJ pin voltage is 1.22V referenced to ground and allows an output voltage range from 1.22V to 20V - VDR. The ADJ pin is internally clamped to ±7 V. Please note that the bias current of the ADJ pin is flowing into the pin.1) 3, 7 (DSO-8 EP) 3, 8 (TSON-10) NC No Connect. The NC Pins have no connection to any internal circuitry. Connect either to GND or leave open. 4 (DSO-8) 5 (TSON-10) BYP Bypass. The BYP pin is used to bypass the reference of the IFX1763 to achieve low noise performance. The BYP-pin is clamped internally to ±0.6 V (i.e. one VBE). A small capacitor from the output to the BYP pin will bypass the reference to lower the output voltage noise2). If not used this pin must be left unconnected. 5 (DSO-8 EP) 7 (TSON-10) EN Enable. With the EN pin the IFX1763 can be put into a low power shutdown state. The output will be off when the EN is pulled low. The EN pin can be driven by 5V logic or open-collector logic with pull-up resistor. The pull-up resistor is required to supply the pull-up current of the open-collector gate 3) and the EN pin current4). Please note that if the EN pin is not used it must be connected to VIN. It must not be left floating. 6 (DSO-8 EP) 6,(TSON-10) GND Ground. For the ADJ version connect the bottom of the output voltage setting resistor divider directly to the GND pin for optimum load regulation performance. 8 (DSO-8 EP) 9, 10 (TSON-10) IN Input. Via the input pin IN the power is supplied to the device. A capacitor at the input pin is required if the device is more than 6 inches away from the main input filter capacitor or if bigger inductance is present at the IN pin5). The IFX1763 is designed to withstand reverse voltages on the Input pin with respect to GND and Output. In the case of reverse input (e.g. due to a wrongly attached battery) the device will act as if there is a diode in series with its input. In this way there will be no reverse current flowing into the regulator and no reverse voltage will appear at the load. Hence, the device will protect both - the device itself and the load. 9 (DSO-8 EP) 11 (TSON-10) Tab Exposed Pad. To ensure proper thermal performance,solder Pin 11 (exposed pad) of TSON-10 to the PCB ground and tie directly to Pin 6. In the case of DSO-

8 EP as well solder exposed pad (Pin 9) to the PCB ground and tie directly to

Pin 6.

Data Sheet 7 Rev. 1.1, 2014-10-30 1) The typical value of the ADJ pin bias current is 60 nA wi th a very good temperature stability.See also the corresponding Typical Performance Graph “Adjust Pin Bias current IADJ versus Junction Temperature TJ” on Page 20. 2) A maximum value of 10 nF can be used for reducing output voltage noise over the bandwidth from 10 Hz to 100 kHz. 3) Normally several microamperes. 4) Typical value is 1 µA. 5) In general the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery- powered circuits. Depending on actual conditions an input capacitor in the range of 1 to 10 µF is sufficient.

Data Sheet 8 Rev. 1.1, 2014-10-30 IFX1763 General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings

Stresses above the ones listed here may cause perma nent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection func tions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Table 1 Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to gr ound, positive current flowing into pin (unless otherwise specified) 1) Not subject to production test, specified by design. Parameter Symbol Va lues Unit Note / Test Condition Number Min. Typ. Max. Input Voltage Voltage VIN -20 – 20 V – P_4.1.1 Output Voltage Voltage VOUT -20 – 20 V – P_4.1.2 Input to Output Differential Voltage VIN -V OUT -20 – 20 V – P_4.1.3 Sense Pin Voltage VSENSE -20 – 20 V – P_4.1.4 ADJ Pin Voltage VADJ -7 – 7 V – P_4.1.5 BYP Pin Voltage VBYP -0.6 – 0.6 V P_4.1.6 Enable Pin Voltage VEN -20 – 20 V – P_4.1.7 Temperatures Junction Temperature Tj -40 – 150 °C – P_4.1.8 Storage Temperature Tstg -55 – 150 °C – P_4.1.9 ESD Susceptibility All Pins VESD -2 – 2 kV HBM 2) 2) ESD susceptibility, HBM accordin g to ANSI/ESDA/JEDEC JS001 (1.5k Ω, 100 pF) P_4.1.10 All Pins VESD -1 – 1 kV CDM 3) 3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101 P_4.1.11

General Product Characteristics Data Sheet 9 Rev. 1.1, 2014-10-30

4.2 Functional Range

Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table.

4.3 Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 2 Functional Range Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Input Voltage Range (3.3 V fix voltage version) VIN 3.8 V – 20 V – P_4.2.1 Input Voltage Range (adjustable voltage version) VIN 2.3 – 20 V – 1) 1) For the IFX1763 adjustable version the minimum limit of the functional range VIN is tested and specified with the ADJ- pin connected to the OUT pin. P_4.2.2 Operating Junction Temperature Tj -40 – 125 °C – P_4.2.3 Table 3 Thermal Resistance 1) 1) Not subject to production test, specified by design. Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. IFX1763X EJ (PG-DSO-8 Exposed Pad) Junction to Case RthJC – 7.0 – K/W – P_4.3.1 Junction to Ambient RthJA –3 9 –K / W – 2) P_4.3.2 Junction to Ambient RthJA – 155 – K/W Footprint only 3) P_4.3.3 Junction to Ambient RthJA –6 6 –K / W 3 0 0 m m 2 heatsink area on PCB3) P_4.3.4 Junction to Ambient RthJA –5 2 –K / W 6 0 0 m m 2 heatsink area on PCB3) P_4.3.5 IFX1763 LD (PG-TSON-10) Junction to Case RthJC – 6.4 – K/W – P_4.3.6 Junction to Ambient RthJA –5 3 –K / W – 2) P_4.3.7 Junction to Ambient RthJA – 183 – K/W Footprint only 3) P_4.3.8 Junction to Ambient RthJA –6 9 –K / W 3 0 0 m m 2 heatsink area on PCB3) P_4.3.9 Junction to Ambient RthJA –5 7 –K / W 6 0 0 m m 2 heatsink area on PCB3) P_4.3.10

Data Sheet 10 Rev. 1.1, 2014-10-30 IFX1763 General Product Characteristics 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).

Electrical Characteristics

Data Sheet 11 Rev. 1.1, 2014-10-30

5 Electrical Characteristics

5.1 Electrical Characteristics Table

Table 4 Electrical Characteristics -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless otherwise specified. Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Minimum Operating Voltage VIN,min –1 . 8 2 . 3 V IOUT =5 0 0m A1)2)3) P_5.1.1 Output Voltage4) IFX1763XEJ V33 IFX1763LD V33 VOUT 3.220 3.30 3.380 V 1m A < IOUT < 500 mA,

4.3 V < VIN <2 0V

P_5.1.2 IFX1763XEJ V IFX1763LD V VOUT 1.190 1.22 1.250 V 1m A < IOUT < 500 mA;

2.3 V < VIN <2 0V 3)

P_5.1.3 Line Regulation IFX1763XEJ V33 IFX1763LD V33 ∆VOUT –1 2 0 m V ∆VIN = 3.8 V to 20 V; IOUT =1m A P_5.1.4 IFX1763XEJ V IFX1763LD V ∆VOUT –1 2 0 m V ∆VIN = 2.0 V to 20 V; IOUT =1m A 3) P_5.1.5 Load Regulation IFX1763XEJ V33 IFX1763LD V33 ∆VOUT –9 2 2 m V TJ =2 5 ° C ;VIN =4 . 3V ; ∆ IOUT = 1 to 500 mA P_5.1.6 IFX1763XEJ V33 IFX1763LD V33 ∆VOUT –– 3 8 m V VIN =4 . 3V ; ∆ IOUT = 1 to 500 mA P_5.1.7 IFX1763XEJ V IFX1763LD V ∆VOUT –4 8m V TJ =2 5 ° C ; VIN =2 . 3V ; ∆IOUT =1 t o 5 0 0m A3) P_5.1.8 IFX1763XEJ V IFX1763LD V ∆VOUT –– 1 4 m V VIN =2 . 3V ; ∆IOUT =1 t o 5 0 0m A3) P_5.1.9 Dropout Voltage2)5)6) Dropout Voltage VDR – 100 130 mV IOUT =1 0m A ; VIN = VOUT,nom; TJ =2 5 ° C P_5.1.10 Dropout Voltage VDR – – 190 mV IOUT =1 0m A ; VIN = VOUT,nom P_5.1.11 Dropout Voltage VDR – 150 190 mV IOUT =5 0m A ; VIN = VOUT,nom; TJ =2 5 ° C P_5.1.12 Dropout Voltage VDR – – 250 mV IOUT =5 0m A ; VIN = VOUT,nom P_5.1.13 Dropout Voltage VDR – 190 220 mV IOUT =1 0 0m A ; VIN = VOUT,nom; TJ =2 5 ° C P_5.1.14 Dropout Voltage VDR – – 300 mV IOUT =1 0 0m A ; VIN = VOUT,nom P_5.1.15 Dropout Voltage VDR – 320 350 mV IOUT =5 0 0m A ; VIN = VOUT,nom; TJ =2 5 ° C P_5.1.16

Data Sheet 12 Rev. 1.1, 2014-10-30 IFX1763 Dropout Voltage VDR – – 450 mV IOUT =5 0 0m A ; VIN = VOUT,nom P_5.1.17 GND Pin Current5)7) GND Pin Current IGND –3 0 6 0 µ A VIN = VOUT,nom; IOUT =0m A P_5.1.18 GND Pin Current IGND – 50 100 µA VIN = VOUT,nom; IOUT =1m A P_5.1.19 GND Pin Current IGND – 300 850 µA VIN = VOUT,nom; IOUT =5 0m A P_5.1.20 GND Pin Current IGND –0 . 7 2 . 2 m A VIN = VOUT,nom; IOUT =1 0 0m A P_5.1.21 GND Pin Current IGND –3 8m A VIN = VOUT,nom; IOUT =2 5 0m A P_5.1.22 GND Pin Current IGND –1 1 2 2 m A VIN = VOUT,nom; IOUT =5 0 0m A ; TJ ≥ 25°C P_5.1.23 GND Pin Current IGND –1 1 3 1 m A VIN = VOUT,nom; IOUT =5 0 0m A ; TJ < 25°C P_5.1.24 Quiescent Current in Off-Mode (EN-pin low) Iq –0 . 1 1µ A VIN =6V ; VEN =0V ; TJ =2 5 ° C P_5.1.25 Enable Enable Threshold High Vth,EN –0 . 8 2 . 0 V VOUT = Off to On P_5.1.26 Enable Threshold Low Vtl,EN 0.25 0.65 – V VOUT = On to Off P_5.1.27 EN Pin Current8) IEN –0 . 0 1 –µ A VEN =0V ; TJ = 25°C P_5.1.28 EN Pin Current8) IEN –1 –µ A VEN =2 0V ; TJ = 25°C P_5.1.29 Adjust Pin Bias Current9)11) ADJ Pin Bias Current Ibias,ADJ –6 0 –n A TJ = 25°C P_5.1.30 Output Voltage Noise11) Output Voltage Noise IFX1763XEJ V10) IFX1763LD V10) eno –4 1 – µVRMS COUT = 10 µF ceramic; CBYP =1 0n F ; IOUT =5 0 0m A ; (BW = 10 Hz to 100 kHz) P_5.1.31 Output Voltage Noise IFX1763XEJ V10) IFX1763LD V10) eno –2 8 – µVRMS COUT = 10 µF ceramic +250mΩ resistor in series; CBYP =1 0n F ; IOUT =5 0 0m A ; (BW = 10 Hz to 100 kHz) P_5.1.32 Output Voltage Noise IFX1763XEJ V10) IFX1763LD V10) eno –2 9 – µVRMS COUT = 22 µF ceramic; CBYP =1 0n F ; IOUT =5 0 0m A ; (BW = 10 Hz to 100 kHz) P_5.1.33 Table 4 Electrical Characteristics (cont’d) -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless otherwise specified. Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 13 Rev. 1.1, 2014-10-30 Output Voltage Noise IFX1763XEJ V10) IFX1763LD V10) eno –2 4 – µVRMS COUT = 22 µF ceramic +250mΩ resistor in series; CBYP =1 0n F ; IOUT =5 0 0m A ; (BW = 10 Hz to 100 kHz) P_5.1.34 Output Voltage Noise IFX1763XEJ V33 IFX1763LD V33 eno –4 5 – µVRMS COUT = 10 µF ceramic; CBYP =1 0n F ; IOUT =5 0 0m A ; (BW = 10 Hz to 100 kHz) P_5.1.35 Output Voltage Noise IFX1763XEJ V33 IFX1763LD V33 eno –3 5 – µVRMS COUT = 10 µF ceramic +250mΩ resistor in series; CBYP =1 0n F ; IOUT =5 0 0m A ; (BW = 10 Hz to 100 kHz) P_5.1.36 Output Voltage Noise IFX1763XEJ V33 IFX1763LD V33 eno –3 3 – µVRMS COUT = 22 µF ceramic; CBYP =1 0n F ; IOUT =5 0 0m A ; (BW = 10 Hz to 100 kHz) P_5.1.37 Output Voltage Noise IFX1763XEJ V33 IFX1763LD V33 eno –3 0 – µVRMS COUT = 22 µF ceramic +250mΩ resistor in series; CBYP =1 0n F ; IOUT =5 0 0m A ; (BW = 10 Hz to 100 kHz) P_5.1.38 Power Supply Ripple Rejection11) Power Supply Ripple Rejection PSRR 50 65 – dB VIN - VOUT = 1.5V (avg); VRIPPLE =0 . 5 V p p ; fr =1 2 0 H z ; IOUT =5 0 0 m A P_5.1.39 Output Current Limitation Output Current Limit IOUT,limit 520 – – mA VIN =7V ; VOUT = 0 V P_5.1.40 Output Current Limit IOUT,limit 520 – – mA VIN = VOUT,nom +1V o r

2.3 V12);

∆VOUT =- 0 . 1V P_5.1.41 Input Reverse Leakage Current Input Reverse Leakage Ileak,rev –– 1m A VIN =- 2 0V ; VOUT = 0 V P_5.1.42 Reverse Output Current13) Fixed Voltage Versions IReverse –1 0 2 0 µ A VOUT = VOUT,nom; VIN < VOUT,nom; TJ = 25°C P_5.1.43 Adjustable Voltage Version IReverse –5 1 0 µ A VOUT =1 . 2 2V ; VIN < 1.22 V; TJ =2 5 ° C3) P_5.1.44 Table 4 Electrical Characteristics (cont’d) -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless otherwise specified. Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 14 Rev. 1.1, 2014-10-30 IFX1763 Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specified mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and the given supply voltage. Output Capacitor11) Output Capacitance COUT 3.3 – – µF CBYP = 0 nF P_5.1.45 ESR ESR –14) –3 Ω – P_5.1.46 1) This parameter defines the minimum input voltage for whic h the device is powered up and provides the maximum output current of 500 mA. Due to the nominal output voltage of 3.3 V of the fixed voltage version or depending on the chosen setting of the external voltage divider as well as on the applied conditions the device may either regulate its nominal output voltage or it may be in tracking mode. For further details please also refer to the VOUT specification in Table 4. 2) For the IFX1763XEJ V and IFX1763LD V adjustable versions the dropout voltage for certain output voltage / load conditions will be restricted by the minimum input voltage specification. 3) The adjustable versions of the IFX1763 are tested and specified for these conditions with the ADJ pin connected to the OUT pin. 4) The operation conditions are limited by the maximum junction temperature. The regulated output voltage specification will only apply for conditions where the limit of the maximum junction temperature is fulfilled. It will therefore not apply for all possible combinations of input voltage and output current at a given output voltage. When operating at maximum input voltage, the output current must be limited for thermal reasons. The same holds true when operating at maximum output current where the input voltage range must be limited for thermal reasons. 5) To satisfy requirements for minimum input vo ltage, the adjustable version of the IFX1763 is tested and specified for these conditions with an external resistor divider (two 250 kΩ resistors) for an output voltage of 2.44 V. The external resistors will add a 5 µA DC load on the output. 6) The dropout voltage is the minimum inpu t to output voltage differential needed to maintain regulation at a specified output current. In dropout, the output voltage will be equal to VIN - VDR. 7) GND-pin current is tested with VIN=VOUT,nom or VIN = 2.3 V, whichever is greater, and a current source load. This means that this parameter is tested while being in dropout condition and thus reflects a worst case condition. The GND-pin current will in most cases decrease slightly at higher input voltages - please also refer to the corresponding typical performance graphs. 8) The EN pin current flows into EN pin. 9) The ADJ pin current flows into ADJ pin. 10) ADJ pin connected to OUT pin. 11) Not subject to production test, specified by design. 12) whichever of the two values of VIN is greater in order to also satisfy the requirements for VIN,min. 13) Reverse output current is tested with the IN pin grounded and the OUT pin forced to the rated output voltage. This current flows into the OUT pin and out of the GND pin. 14) CBYP =0n F , COUT ≥ 3.3 µF; please note that for cases where a bypass capacitor at BYP is used - depending on the actual applied capacitance of COUT and CBYP - a minimum requirement for ESR may apply. For further details please also refer to the corresponding typical performance graph. Table 4 Electrical Characteristics (cont’d) -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless otherwise specified. Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Typical Performance Characteristics Data Sheet 15 Rev. 1.1, 2014-10-30

6 Typical Performance Characteristics

Dropout Voltage VDR versus Output Current IOUT Guaranteed Dropout Voltage VDR versus Output Current IOUT Dropout Voltage VDR versus Junction Temperature TJ Quiescent Current versus Junction Temperature TJ 0 100 200 300 400 500 100 150 200 250 300 350 400 450 500 IOUT [A] VDR [mV] Tj = −40 °C Tj = 25 °C Tj = 125 °C 0 100 200 300 400 500 100 150 200 250 300 350 400 450 500 IOUT [A] VDR [mV] Δ = Guaranteed Limits Tj ≤ 25 °C Tj ≤ 125 °C −50 0 50 100 100 150 200 250 300 350 400 450 500 Tj [°C] VDR [mV] IOUT = 10 mA IOUT = 50 mA IOUT = 100 mA IOUT = 500 mA −50 0 50 100 Tj [°C] Iq [µA] VIN = 6 V IOUT = 0 mA . VEN = VIN

Data Sheet 16 Rev. 1.1, 2014-10-30 IFX1763 Typical Performance Characteristics Output Voltage VOUT versus Junction Temperature TJ (IFX1763XEJ V33) Output / ADJ Pin Voltage VOUT versus Junction Temperature TJ (IFX1763XEJ V) Quiescent Current Iq versus Input Voltage VIN (IFX1763XEJ V33) Quiescent Current Iq versus Input Voltage VIN (IFX1763XEJ V) −50 0 50 100 3.24 3.26 3.28 3.3 3.32 3.34 3.36 Tj [°C] VOUT [V] IOUT = 1 mA −50 0 50 100 1.2 1.205 1.21 1.215 1.22 1.225 1.23 1.235 1.24 Tj [°C] ADJ Pin Voltage [V] IOUT = 1 mA 0 2 4 6 8 10 100 200 300 400 500 600 700 800 VIN [V] IGND [µA] VOUT,nom = 3.3 V IOUT,nom = 0 mA VEN = VIN Tj = 25 °C 0 5 10 15 20 VIN [V] IGND [µA] VOUT,nom = 1.22 V RLoad = 250 kΩ VEN = VIN Tj = 25 °C

Typical Performance Characteristics Data Sheet 17 Rev. 1.1, 2014-10-30 GND Current IGND versus Input Voltage VIN (IFX1763XEJ V33) GND Current IGND versus Input Voltage VIN (IFX1763XEJ V) GND Current IGND versus Input Voltage VIN (IFX1763XEJ V33) GND Current IGND versus Input Voltage VIN (IFX1763XEJ V) 0 2 4 6 8 10 200 400 600 800 1000 1200 VIN [V] IGND [µA] [* for VOUT = 3.3 V] Tj = 25°C RLoad = 3.3 kΩ / IOUT = 1 mA* RLoad = 330 Ω / IOUT = 10 mA* RLoad = 66 Ω / IOUT = 50 mA* 0 2 4 6 8 10 100 150 200 250 300 350 400 VIN [V] IGND [µA] [* for VOUT = 1.22 V] Tj = 25°C RLoad = 1.22 kΩ / IOUT = 1 mA* RLoad = 122 Ω / IOUT = 10 mA* RLoad = 24.4 Ω / IOUT = 50 mA* 0 2 4 6 8 10 2000 4000 6000 8000 10000 12000 14000 16000 VIN [V] IGND [µA] [* for VOUT = 3.3 V] Tj = 25°C RLoad = 33.0 Ω / IOUT = 100 mA* RLoad = 11.0 Ω / IOUT = 300 mA* RLoad = 6.60 Ω / IOUT = 500 mA *. 0 2 4 6 8 10 2000 4000 6000 8000 10000 12000 14000 16000 VIN [V] IGND [µA] [* for VOUT = 1.22 V] Tj = 25°C RLoad = 12.2 Ω / IOUT = 100 mA* RLoad = 4.07 Ω / IOUT = 300 mA* RLoad = 2.44 Ω / IOUT = 500 mA *.

Data Sheet 18 Rev. 1.1, 2014-10-30 IFX1763 Typical Performance Characteristics GND Current IGND versus Output Current IOUT EN Pin Threshold (On-to-Off) versus Junction Temperature TJ EN Pin Threshold (Off-to-On) versus Junction Temperature TJ EN Pin Input Current versus EN Pin Voltage VEN 0 100 200 300 400 500 IOUT [mA] IGND [mA] VIN = VOUT,nom + 1 V Tj = 25 ° C −50 0 50 1000 0.2 0.4 0.6 0.8 1.2 Tj [°C] VEN,th [V] 1 mA 500 mA −50 0 50 1000 0.2 0.4 0.6 0.8 1.2 Tj [°C] VEN,th [V] 1 mA 500 mA 0 5 10 15 200 0.2 0.4 0.6 0.8 1.2 1.4 VEN [V] IEN [µA] Tj = 25 °C VIN = 20 V

Typical Performance Characteristics Data Sheet 19 Rev. 1.1, 2014-10-30 EN Pin Input Current versus Junction Temperature TJ Current Limit versus Input Voltage VIN Current Limit versus Junction Temperature TJ Reverse Output Current versus Output Voltage VOUT −50 0 50 100 0.2 0.4 0.6 0.8 1.2 1.4 1.6 Tj [°C] IEN [µA] VEN = 20 V 0 1 2 3 4 5 6 7 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VIN [V] IOUT,max [A] VOUT = 0 V Tj = 25 ° C −50 0 50 1000 0.2 0.4 0.6 0.8 1.2 Tj [°C] IOUT,max [A] VIN = 7 V VOUT = 0 V 0 2 4 6 8 10 VOUT [V] IOUT,rev [µA] VIN = 0 V Tj = 25 °C VOUT.nom = 1.22 V (ADJ) VOUT.nom = 3.3 V (V33)

Data Sheet 20 Rev. 1.1, 2014-10-30 IFX1763 Typical Performance Characteristics Reverse Output Current versus Junction Temperature TJ Minimum Input Voltage1) versus Junction Temperature TJ 1) VIN,min is referred here as the minimum input voltage for which the requested current is provided and VOUT reaches 1 V. Load Regulation versus Junction Temperature TJ Adjust Pin Bias current IADJ versus Junction Temperature TJ −50 0 50 100 Tj [°C] IOUT,rev [µA] VIN = 0 V VOUT.nom = 1.22 V (ADJ) VOUT.nom = 3.3 V (V33) −50 0 50 100 0.5 1.5 2.5 Tj [°C] VIN,min [V] IOUT = 100 mA IOUT = 500 mA −50 0 50 100 −25 −20 −15 −10 Tj [°C] ΔVLoad [mV] ΔILoad = 1 mA to 500 mA V33: VIN = 4.3 V VOUT.nom = 3.3 V ADJ: VIN = 2.3 V VOUT.nom = 1.22 V −50 0 50 100 100 120 140 Tj [°C] IADJ [nA]

Typical Performance Characteristics Data Sheet 21 Rev. 1.1, 2014-10-30 ESR Stability versus Output Current IOUT (for COUT =3 . 3µ F ) ESR(COUT) with CBYP = 10 nF versus Output Capacitance COUT Input Ripple Rejection PSRR versus Frequency f Input Ripple Rejection PSRR versus Junction Temperature TJ ESRmax CByp = 0 nF ESRmin CByp = 0 nF ESRmax CByp = 10 nF ESRmin CByp = 10 nF 0 100 200 300 400 500 IOUT [mA] ESR(COUT) [Ω] COUT = 3.3 µF (0.06 Ω is measurement limit) 2 3 4 5 6 7 0.5 1.5 2.5 COUT [µF] ESR(COUT) [Ω] stable region above blue line CByp = 10 nF measurement limit IOUT =500mA CBYP =0 nF IOUT =500mA CBYP =10nF IOUT =50mA CBYP =0 nF IOUT =50mA CBYP =10nF 10 100 1k 10k 100k 100 f [Hz] PSRR [dB] VIN = VOUTnom + 1.5 V Vripple = 0.5 Vpp COUT = 10 µF −50 0 50 100 Tj [°C] PSRR [dB] VIN = VOUTnom + 1.5 V Vripple = 0.5 Vpp fripple = 120 Hz COUT = 10 µF IOUT =500mA CBYP =0 nF IOUT =500mA CBYP =10nF

Data Sheet 22 Rev. 1.1, 2014-10-30 IFX1763 Typical Performance Characteristics Output Noise Spectral Density (ADJ) versus Frequency (COUT =1 0µ F , IOUT =5 0m A1)) 1) Load condition 50mA is representing a worst case co ndition with regard to output voltage noise performance. Output Noise Spectral Density (ADJ) versus Frequency (COUT = 22 µF, IOUT =5 0m A1)) Output Noise Spectral Density (3.3 V) versus Frequency (COUT =1 0µ F , IOUT =5 0m A1)) Output Noise Spectral Density (3.3 V) versus Frequency (COUT = 22µF, IOUT =5 0 m A1)) CByp = 0 nF; ESR(COUT)=0 CByp = 10 nF; ESR(COUT)=0 CByp = 10 nF; ESR(COUT)=250mΩ f [Hz] Output Spectral Noise DensityμV/ Hz COUT = 10 µF IOUT = 50 mA CByp = 0 nF; ESR(COUT)=0 CByp = 10 nF; ESR(COUT)=0 CByp = 10 nF; ESR(COUT)=250mΩ f [Hz] Output Spectral Noise DensityμV/ Hz COUT = 22 µF IOUT = 50 mA CByp = 0 nF; ESR(COUT)=0 CByp = 10 nF; ESR(COUT)=0 CByp = 10 nF; ESR(COUT)=250mΩ f [Hz] Output Spectral Noise DensityμV/ Hz COUT = 10 µF IOUT = 50 mA CByp = 0 nF; ESR(COUT)=0 CByp = 10 nF; ESR(COUT)=0 CByp = 10 nF; ESR(COUT)=250mΩ f [Hz] Output Spectral Noise DensityμV/ Hz COUT = 22 µF IOUT = 50 mA

Typical Performance Characteristics Data Sheet 23 Rev. 1.1, 2014-10-30 Transient Response CBYP = 0nF (IFX1763XEJ V33) Transient Response CBYP = 10nF (IFX1763XEJ V33) -0,3 -0,2 -0,1 0,1 0,2 0,3 0 100 200 300 400 500 600 700 800 900 1000 VOUT Deviation / [V] Time (μs) COUT = 10 µF CBYP = 0 nF VIN = 6 V 100 200 300 400 500 600 0 100 200 300 400 500 600 700 800 900 1000 Load Step / [mA] Time (μs) IOUT : 100 to 500mA -0,15 -0,1 -0,05 0,05 0,1 0,15 0 1 02 03 04 05 06 07 08 09 0 1 0 0 VOUT Deviation / [V] Time / [μs] COUT = 10 µF CBYP = 10 nF VIN = 6V 100 200 300 400 500 600 0 1 02 03 04 05 06 07 08 09 0 1 0 0 Load Step / [V] Time / [μs] IOUT : 100 to 500mA

Data Sheet 24 Rev. 1.1, 2014-10-30 IFX1763

Application Information

7 Application Information

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 5 Typical Application Circuit IFX1763 (fixed voltage version) Figure 6 Typical Application Circ uit IFX1763 (adjustable version) Note: This is a very simplified example of an application circuit. The function must be verified in the real application1)2). 1) Please note that in case a non-negligible inductance at IN pin is present, e.g. due to long cables, traces, parasitics, etc, a bigger input capacitor CIN may be required to filter its influence. As a rule of thumb if the IN pin is more than six inches away from the main input filter capacitor an input capacitor value of CIN = 10 µF is recommended. 2) For specific needs a small optional resistor may be placed in series to very low ESR output capacitors COUT for enhanced noise performance (for details please see “Bypass Capacitance and Low Noise Performance” on Page 25). RLoadCBYP COUT CIN IN GND OUT EN SENSE BYP IFX1763 VIN GND 10nF 10µF 1µF VOUT RLoad CBYP CIN IN GND OUT EN ADJ BYP IFX1763 ADJ VIN GND 10nF 10µF 1µF COUT VOUT Calculation of V OUT: VOUT = 1.22V x (1 + R2 / R1) + (IADJ x R2)

Data Sheet 25 Rev. 1.1, 2014-10-30 The IFX1763 is a 500 mA low dropout regulator with very low quiescent current and Enable-functionality. The device is capable of supplying 500 m A at a dropout voltage of 320 mV. Ou tput voltage noise numbers down to 24 µVRMS can be achieved over a 10 Hz to 100 kHz bandwi dth with the addition of a 10 nF reference bypass capacitor. The usage of a reference bypass capacitor will additionally improve transient response of the regulator, lowering the settling time for transient load conditions. The device has a low operating quiescent current of typical 30 µA that drops to less than 1 µA in shutdown (EN-pin pulled to low level). The device also incorporates several protection features which makes it idea l for battery-powered systems. It is protected against bo th reverse input and reverse output voltages. In battery backup applications where the output can be held up by a backup battery when the input is pulled to ground the device behaves li ke it has a diode in series with its output and prevents reverse current flow.

7.1 Adjustable Operation

The adjustable version of the IFX1763 has an output voltage range of 1.22 V to 20 V - VDR. The output voltage is set by the ratio of two external resistors, as it can be seen in Figure 6 (for the calculation of VOUT the formula given in the figure can be used). The device controls the output to maintain the ADJ pin at 1.22 V referenced to ground. The current in R1 is then equal 1.22 V / R1 and the current in R2 equals the current in R1 plus the ADJ pin bias current. The ADJ pin bias current, which is ~ 60 nA @ 25°C, flows through R2 into the ADJ pin. The value of R1 should be not greater than 250 k Ω in order to minimize errors in the output voltage caused by the ADJ pin bias current. Note that when the device is shutdown (i.e. low level applied to EN pin) the output is turned off and consequently the divider current will be zero. For details of the ADJ pin bias current see also the corresponding typical performance graph Figure “Adjust Pin Bias current IADJ versus Junction Temperature TJ” on Page 20.

7.2 Kelvin Sense Connection

For the fixed voltage version of the IFX1763 the SENSE pi n is the input to the error amplifier. An optimum regulation will be obtained at the point where the SENSE pin is connected to the OUT pin of the regulator. In critical applications however small voltage drops can be caused by the resistance Rp of the PC-traces and thus may lower the resulting voltage at the load. This effect may be eliminated by connecting the SENSE pin to the output as close as possible at the load (see Figure 7). Please note that the voltage drop across the external PC trace will add up to the dropout voltage of the regulator. Figure 7 Kelvin Sense Connection

7.3 Bypass Capacitance and Low Noise Performance

The IFX1763 regulator may be used in combination with a bypass capacitor connecting the OUT pin to the BYP pin in order to minimize output voltage noise1).This capacitor will bypass the reference of the regulator, providing 1) a good quality low leakage capacitor is recommended. CIN IN GND OUT EN SENSE BYP IFX1763 VIN RLoadCOUT RP RP

Data Sheet 26 Rev. 1.1, 2014-10-30 IFX1763 a low frequency noise pole. The noise pole provided by such a bypass capacitor will lower the output voltage noise in the considered bandwidth. For a given output volt age actual numbers of the out put voltage noise will - next to the bypass capacitor itself - be dependent on the capacitance of the applied output capacitor and its ESR: In case of the IFX1763XEJ V applied with unity gain (i.e. VOUT = 1.22 V) the usage of a bypass capacitor of 10 nF in combination with a (low ESR) ceramic COUT of 10 µF will result in output voltage noise numbers of typical 41 µVRMS. This Output Noise level ca n be reduced to typical 28 µVRMS under the same conditions by adding a small resistor of ~250 mΩ in series to the 10 µF ceramic output capacitor acting as additional ESR. A reduction of the output voltage noise can also be achieved by increasing capacitance of the output capacitor. For COUT =2 2µ F (ceramic low ESR) the output voltage noise will be typically around 29 µVRMS and can again be further lowered to 24 µVRMS by adding a small resistance of ~250 mΩ in series to COUT. In case of the fix voltage version IFX1763XEJ V33 the output voltage noise for the described cases vary from 45 µVRMS down to 30 µVRMS. For further details please also see “Output Voltage Noise11)” on Page 12,, of the Electrical Characteristics. Please note that next to reducing the output voltage noise level the usage of a bypass capacitor has the additional benefit of improving transient response which will be also explained in the next chapter. However one needs to take into consideration that on the other hand the regulator start-up time is proportional to the size of the bypass capacitor and slows down to values around 15 ms when using a 10 nF bypass capacitor in combination with a 10 µF COUT output capacitor.

7.4 Output Capacitance Requirements and Transient Response

The IFX1763 is designed to be stable with a wide range of output capacitors. The ESR of the output capacitor is an essential parameter with regard to stability, most notably with small capacitors. A minimum output capacitor of 3.3 µF with an ESR of 3 Ω or less is recommended to prevent oscilla tions. Like in general for LDO’s the output transient response of the IFX1763 will be a function of the output capacitance. Larger values of output capacitance decrease peak deviations and thus improve transient response for larger load current changes. Bypass capacitors, used to decoupl e individual components pow ered by the IFX1763 will in crease the ef fective output capacitor value. Please note that with the usage of bypass capacitors for low noise operation either larger values of output capacitors are needed or a minimum ESR requirement of COUT may have to be considered (see also Figure “ESR( COUT) with CBYP = 10 nF versus Output Capacitance COUT” on Page 21 as example). In conjunction with the usage of a 10 nF bypass capacitor an output capacitor COUT ≥ 6.8 µF is recommended. The benefit of a bypass capacitor to the transient response performance is impressive and illustrated as one example in Figure 8 where the transient response of the IFX1763XEJ V33 to one and the same load step from 100 mA to 500 mA is shown with and without a 10 nF bypa ss capacitor: for the given configuration of COUT =1 0µ F w i t h n o bypass capacitor the load step will settle in the range of less than 100 µs while for COUT = 10 µF in conjunction with a 10 nF bypass capacitor the same load step will settle in the range of 10 µs. Due to the shorter reaction time of the regulator by adding the bypa ss capacitor not only the settling ti me improves but also output voltage deviations due to load steps are sharply reduced. Figure 8 Influence of CBYP: example of transient response to one and the same load step with and without CBYP of 10 nF (IOUT 100 mA to 500 mA, IFX1763XEJ V33) -0,3 -0,2 -0,1 0,1 0,2 0,3 0 100 200 300 400 500 600 700 800 900 1000 VOUT Deviation / [V] Time (μs) C_BYP = 0nF C_BYP = 10nF COUT = 10 µF CBYP = 0 vs 10nF VIN = 6 V

Data Sheet 27 Rev. 1.1, 2014-10-30

7.5 Protection Features

The IFX1763 regulators incorporate several protection fe atures which make them ideal for usage in battery- powered circuits. In addition to normal protection features associated with monolithic regulators like current limiting and thermal limiting the device is protected against reve rse input voltage, reverse output voltage and reverse voltages from output to input. Current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. For normal operation the junction temperature must not exceed 125°C. The input of the device will withstand reverse voltages of 20 V. Current fl owing into the device will be limited to less than 1 mA (typically less than 100 µA) and no negative voltage will appear at th e output. The device will protect both itself and the load. This provides protection against batteries being plugged backwards. The output of the IFX1763 can be pulled below ground without damaging the device. If the input is left open-circuit or grounded, the output can be pulled below ground by 20 V. Under such conditions the output of the device by itself behaves like an open circuit with practically no current flowing out of the pin 1). In more application relevant cases however where the output is either connected to the SENSE pin (fix voltage variant) or tied either via an external voltage divider or directly to the ADJ pin (adjustable variant) a small current will be present from this origin. In the case of the fixed voltage version this current will typically be below 100 µA while for the adjustable version it depends on the magnitude of the top resistor of the external voltage divider2). If the input is powered by a voltage source the output will source the short circuit current of the device and will protect itself by thermal limiting. In this case grounding the EN pin will turn off the device and stop the output from sourcing the short-circuit current. The ADJ pin of the adjustable device can be pulled above or below ground by as much as 7 V without damaging the device. If the input is grounded or left open-circuit, the ADJ pin will act inside this voltage range like a large resistor (typically 100 kΩ) when being pulled above ground and like a resistor (typically 5 kΩ) in series with a diode when being pulled below ground. In situations where the ADJ pin is at risk of being pulled outside its absolute maximum ratings ±7 V the ADJ pin current must be limited to 1 mA (e.g. in cases where the ADJ pin is connected to a resistor divider that would pull the ADJ pin above its 7 V clamp voltage). Let’s consider for example the case where a resistor divider is used to provide a 1.5 V out put from the 1.22 V reference and the output is forced to 20 V. The top resistor of the resistor divider must then be chosen to limit the current into the ADJ pin to 1 mA or less when the ADJ pin is at 7 V. The 13 V difference between output and ADJ pin divided by the 1 mA maximum current into the ADJ pin requires a minimum resistor value of 13 kΩ. In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open-circuit. Current flow back into the output will follow the curve as shown in Figure 9 below. When the IN pin of the fixed voltage version is forced below the OUT pin, or the OUT pin is pulled above the IN pin, the input current will drop to very small values – typically down to less than 2 µA, once VOUT exceeds VIN by some 300 mV or more. This can happen if the input of th e device is connected to a discharged battery and the output is held up by either a backup battery or a second regulator circuit. The state of the EN pin will have no effect on the reverse output current when the output is pulled above the input. 1) typically < 1 µA for the mentioned conditions, VOUT being pulled below ground with other pins either grounded or open. 2) In case there is no external voltage divider applied i.e. th e ADJ pin is directly connected to the output and the output is pulled below ground by 20 V the current flowing out of the ADJ pin will be typically ~ 4 mA. Please ensure in such cases that the absolute maximum ratings of the ADJ pin are respected.

Data Sheet 28 Rev. 1.1, 2014-10-30 IFX1763 Figure 9 Reverse Output Current 0 2 4 6 8 10 VOUT [V] IOUT,rev [µA] VIN = 0 V Tj = 25 °C VOUT.nom = 1.22 V (ADJ) VOUT.nom = 3.3 V (V33)

Data Sheet 29 Rev. 1.1, 2014-10-30

8 Package Outlines

Figure 10 PG-DSO-8 Exposed Pad package outlines Figure 11 PG-TSON-10 Package Outlines Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). PG-DSO-8-27-PO V01 8x0.41±0.09 2) M0.2 DC A-B 1.27 C Stand Off -0.10.1 (1.45) 1.7 MAX. 0.08 Seating Plane C A B 3) JEDEC reference MS-012 variation BA 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width Bottom View ±0.23 ±0.22.65 0.2±0.2 D 6 M D 8x 0.64±0.25 3.9±0.11) 0.1 0.35 x 45˚ CD2 x +0.06 0.1 8˚ MAX. Index Marking Pin 1 Marking Pin 1 Marking PG-TSON-10-2-PO V02 ±0.10.2 ±0.10.25 ±0.10.55 0.96 ±0.1 2.58±0.1 0 +0.05 ±0.1 ±0.1 0.25 0.5 ±0.13.3 ±0.13.3 ±0.1 1±0.1 0.71±0.1 1.63±0.1 1.48±0.1 Z 0.05 0.07 MIN. Z (4:1) For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Dimensions in mm

Data Sheet 30 Rev. 1.1, 2014-10-30 IFX1763

Revision History

9 Revision History

1.1 2014-10-30 Updated Data Sheet includin g additional package type PG-TSON-10:

PG-TSON-10 package variants added: Product Overview, Pin Configuration Thermal Resistance, Wording, etc added / updated accordingly.
Typical Performance Graphs: some l egends entries updated and corrected (Figure “Minimum Input Voltage versus Junction Temperature TJ” on Page 20 and Figure “Input Ripple Rejection PSRR versus Junction Temperature TJ” on Page 21).
Application Information updated: Clari fication and correction of wording. Typical values updated and footnotes added.
Editorial changes throughout the document. 1.0 2014-02-13 Data Sheet - Initial Release

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© 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. The Infineon Technologies component described in this Data Sheet may be used in life-support devices or systems and/or automotive, aviation and aerospace applications or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life- support automotive, aviation and aerospace device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Summary

Wide Input Range Low Noise 500mA LDO Rev. 1.1, 2014-10-30

Description