FSIDM-9 RHOMBUS-IND | Alldatasheet
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Technical content
15801 Chemical Lane, Huntington Beach, CA 92649-1595
Phone: (714) 898-0960 • FAX: (714) 896-0971 www.rhombus-ind.com • email: sales@rhombus-ind.com Rhombus Industries Inc. For other values & Custom Designs, contact factory. Specifications subject to change without notice. FAMDM 9901 8-Pin SIP Package FAST/TTL Logic Buffered
5 Equal Delay Taps
8-Pin DIP Versions: see FAMDM Series 14-Pin DIP Versions: see FAIDM Series Low Voltage CMOS Versions refer to LVMDM / LVIDM Series Electrical Specifications at 25O C ** These part numbers do not have 5 equal taps. Tap-to-Tap Delays reference Tap 1. FSIDM Series FAST / TTL Buffered 5-T ap Delay Modules IN 5 67 Vcc GND 23 4 Tap1 Tap2 Tap3 Tap4 Tap5 FSIDM 8-Pin SIP Schematic OPERATING SPECIFICATIONS TEST CONDITIONS -- FAST / TTL 1. Measurements made at 25 O C 2. Delay Times measured at 1.50V level of leading edge. 3. Rise Times measured from 0.75V to 2.40V. 4. 10pf probe and fixture load on output under test. P/N Description FSIDM - XXX X 74F Buffered 5 Tap Delay Molded Package Series: 8-pin SIP: FSIDM Total Delay in nanoseconds (ns) Lead Style: Blank = Thru-hole Examples: FSIDM-25 = 25ns (5ns per tap) 74F, 8-Pin SIP FSIDM-100 = 100ns (20ns per tap) 74F, 8-Pin SIP .810 (20.57) MAX. .280 (7.11) MAX. .050 (1.27) TYP. .020 (0.51) TYP. .100 (2.54) TYP. .015 (0.38) TYP. MIN. .120 (3.05) .155 (3.94) .145 (3.68) .010 (0.25) TYP. .180 (4.57) MAX. Dimensions in Inches (mm) FAST 5 Tap 8-Pin SIP P/N Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <13ns)Tap-to-Tap (ns)Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5 FSIDM Series Molded 8-Pin SIP Package