ACMDM-30 RHOMBUS-IND | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 1
Technical content
/G36/G53/G48/G46/G4C/G49/G4C/G46/G44/G57/G4C/G52/G51/G56 /G56/G58/G45/G4D/G48/G46/G57 /G57/G52 /G46/G4B/G44/G51/G4A/G48 /G5A/G4C/G57/G4B/G52/G58/G57 /G51/G52/G57/G4C/G46/G48/G11 /G29/G52/G55 /G52/G57/G4B/G48/G55 /G59/G44/G4F/G58/G48/G56 /G09 /G26/G58/G56/G57/G52/G50 /G27/G48/G56/G4C/G4A/G51/G56/G0F /G46/G52/G51/G57/G44/G46/G57 /G49/G44/G46/G57/G52/G55/G5C/G11 /G55/G4B/G52/G50/G45/G58/G56 /G4C/G51/G47/G58/G56/G57/G55/G4C/G48/G56 /G4C/G51/G46/G11 ACMDM 2001-01 www.rhombus-ind.com TEL: (714) 898-0960sales@rhombus-ind.com FAX: (714) 896-0971 P/N Description ACMDM - XXX X 74ACT Buffered 5 Tap Delay Molded Package Series: 8-pin DIP: ACMDM Total Delay in nanoseconds (ns) Lead Style: Blank = Thru-hole G = “Gull Wing” SMD J = “J” Bend SMD Examples: ACMDM-25G = 25ns (5ns per tap) 74ACT, 8-Pin G-SMD ACMDM-100 = 100ns (20ns per tap) 74ACT, 8-Pin DIP ACMDM Series Advanced CMOS Logic Buffered 5-T ap Delay Modules .505 (12.83) MAX. .120 MIN. (3.05) MAX. .250 (6.35) .100 (2.54) TYP. .050 (1.27) TYP. .020 (0.51) TYP. .020 (0.51) TYP. .300 (7.62) .285 (7.24) MAX. .010 (0.25) TYP. .365 (9.27) MAX. .250 (6.35) MAX. .015 (0.38) TYP. .400 (10.16) .430 (10.92) .030 (0.76) TYP. .008 R (0.20) .100 (2.54) TYP. .050 (1.27) TYP. .020 (0.51) TYP. .010 (0.25) TYP. .505 (12.83) MAX. .285 (7.24) MAX. MAX. .265 (6.73) .030 (0.76) TYP. .330 (8.38) MAX. .020 R (0.51) .285 (7.24) .260 (6.60) .100 (2.54) TYP. .050 (1.27) TYP. .020 (0.51) TYP. .505 (12.83) MAX. .285 (7.24) MAX. Dimensions in Inches (mm) G-SMD G-SMD J-SMD J-SMD DIP DIP 74ACT type input is compatible with TTL Outputs can Source / Sink 24 mA Electrical Specifications at 25O CLow Profile 8-Pin Package Two Surface Mount Versions Available in Low Voltage CMOS 74LVC Logic version LVMDM Series
5 Equal Delay Taps
Operating Temp. -40O C to +85O C ACMDM 8-Pin Schematic Vcc IN 567 GND Tap4 Tap5Tap1 Tap3 Tap2 TEST CONDITIONS -- Advanced CMOS, 74ACT 1. Measurements made at 25 O C 2. Delay Times measured at 1.50V level of input to +2.50V level of Output on leading edge. 3. Rise Times measured from 10% to 90% points. 4. 50pf probe and fixture load on output under test. OPERATING SPECIFICATIONS 74ACT 5 Tap 8-Pin DIP P/N Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <13ns)Tap-to-Tap (ns)Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5