FPD4000AF

FPD4000AF FILTRONIC | Alldatasheet

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Technical content

Phone: +1 408 850-5790 http:// www.filcs.com Revised: 08/09/04 Fax: +1 408 850-5766 Email: sales@filcsi.com

• PERFORMANCE (1.8 GHz) ♦ 36.5 dBm Output Power (P1dB) ♦ 10.5 dB Power Gain (G1dB) ♦ 49 dBm Output IP3 ♦ 10V Operation ♦ 45% Power-Added Efficiency ♦ Evaluation Boards Available ♦ Additional Design Data Available on Website ♦ Usable Gain to 4GHz
• DESCRIPTION AND APPLICATIONS The FPD4000AF is a packaged depletion mode AlGaAs/InGaAs pseudo morphic High Electron Mobility Transistor (pHEMT), optimized for power applications in L-Band. The high power flange- mount package has been optimized for low electrical parasitics and optimal heatsinking. Typical applications include drivers or output stages in PCS/Cellular base station transmitter amplifiers, as well as other power applications in WLL/WLAN amplifiers.
• ELECTRICAL SPECIFICATIONS AT 22°C Parameter Symbol Test Conditions Min Typ Max Units RF SPECIFICATIONS MEASURED AT f = 1.8 GHz USING CW SIGNAL Power at 1dB Gain Compression P1dB V DS = 10V; IDQ = 720 mA ΓS and ΓL tuned for Optimum IP3 35.5 36.5 dBm Power Gain at dB Gain Compression G 1dB V DS = 10V; IDQ = 720 mA ΓS and ΓL tuned for Optimum IP3 9.5 10.5 Maximum Stable Gain S21/S12 MSG V DS = 10 V; IDQ = 720 mA PIN = 0dBm, 50Ω system 19 dB Power-Added Efficiency at 1dB Gain Compression PAE V DS = 10V; IDQ = 720 mA ΓS and ΓL tuned for Optimum IP3 45 % 3rd-Order Intermodulation Distortion IP3 V DS = 10V; IDQ = 720 mA ΓS and ΓL tuned for Optimum IP3 POUT = 25.5 dBm (single-tone level) -47 -44 dBc Saturated Drain-Source Current I DSS V DS = 1.3 V; VGS = 0 V 1.9 2.3 2.65 A Maximum Drain-Source Current I MAX VDS = 1.3 V; VGS ≅ +1 V 3.6 A Transconductance G M VDS = 1.3 V; VGS = 0 V 2.4 S Gate-Source Leakage Current I GSO V GS = -3 V 70 170 µA Pinch-Off Voltage |V P| V DS = 1.3 V; IDS = 8 mA 0.7 0.9 1.4 V Gate-Source Breakdown Voltage |V BDGS| I GS = 8 mA 6 8 V Gate-Drain Breakdown Voltage |V BDGD| I GD = 8 mA 20 22 V Thermal Resistivity (channel-to-case) ΘCC See Note on following page 12 °C/W SEE PACKAGE OUTLINE FOR MARKING CODE

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• RECOMMENDED OPERATING BIAS CONDITIONS Drain-Source Voltage: From 5V to 10V Quiescent Current: From 25% I DSS to 55% IDSS
• ABSOLUTE MAXIMUM RATINGS1 Parameter Symbol Test Conditions Min Max Units Drain-Source Voltage V DS -3V < VGS < +0V 12 V Gate-Source Voltage V GS 0V < VDS < +8V -3 V Drain-Source Current I DS For VDS > 2V I DSS mA Gate Current I G Forward / Reverse current +25/-4 mA RF Input Power2 P IN Under any acceptable bias state 1.5 W Channel Operating Temperature T CH Under any acceptable bias state 175 ºC Storage Temperature T STG Non-Operating Storage -40 150 ºC Total Power Dissipation P TOT See De-Rating Note below 12 W Gain Compression Comp. Under any bias conditions 5 dB Simultaneous Combination of Limits3 2 or more Max. Limits 80 % 1TAmbient = 22°C unless otherwise noted 2Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3Users should avoid exceeding 80% of 2 or more Limits simultaneously Notes:
• Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device.
• Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where: P DC: DC Bias Power PIN: RF Input Power POUT: RF Output Power
• Total Power Dissipation to be de-rated as follows above 22°C: PTOT= 12 - (0.083W/°C) x TPACK where TPACK = source tab lead temperature above 22°C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 55 °C source lead temperature: PTOT = 12 - (0.083 x (55 – 22)) = 9.3W
• Note on Thermal Resistivity: The nominal value of 12 °C/W is measured with the package mounted on a large heatsink with thermal compo und to ensure adequate contact. The pack age temperature is referred to the Source flange.
• HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised duri ng handling. Proper Electrostatic Discharge (ESD) precautions should be observed at al l stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A per ESD-STM5.1- 1998, Human Body Model. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.

Phone: +1 408 850-5790 http:// www.filcs.com Revised: 08/09/04 Fax: +1 408 850-5766 Email: sales@filcsi.com

• BIASING GUIDELINES ¾ Active bias circuits provide good performance stab ilization over variations of operating temperature, but require a larger number of com ponents compared to self -bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is ap plied before Drain bias, otherwise the pHEMT may be indu ced to self-oscillate. Contact your Sales Representative for additional information. ¾ Dual-bias circuits are relatively simple to im plement, but will requir e a regulated negative voltage supply for depletion-mode devices such as the FPD4000AF. ¾ Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source bias voltage, and such circuits provide some temperature stabilization for the device. A nominal value for circuit de velopment is 0.7 Ω for the recommended 720m A operating point. This approach will require a DC Source resistor capable of at least 365mW dissipation. ¾ The recommended 720mA bias point is nominally a Class AB mode. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point.
• PACKAGE OUTLINE (dimensions in millimeters – mm) All information and specifications subject to change without notice. PACKAGE MARKING CODE Example: f1ZD P2F f = Filtronic 1ZD = Lot and Date Code P2F = Status, Part Code, Part Type Status: D=Development P = Production Part Code denotes model (e.g. FPD4000AF) Part Type: F = FET (pHEMT)

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• TYPICAL RF PERFORMANCE (VDS = 10V IDQ = 720 mA f = 2000 MHz): Power Transfer Characteristic 22.0 24.0 26.0 28.0 30.0 32.0 34.0 36.0 Input Power (dBm) Output Power (dBm) -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Gain Compression (dB) Pout Comp Point Drain Efficiency and PAE .0% 10.0% 20.0% 30.0% 40.0% 50.0% 60.0% 70.0% Input Power (dBm) PAE (%) .0% 10.0% 20.0% 30.0% 40.0% 50.0% 60.0% 70.0% Drain Efficiency (5) PAE Eff.

Phone: +1 408 850-5790 http:// www.filcs.com Revised: 08/09/04 Fax: +1 408 850-5766 Email: sales@filcsi.com Note: Graph above shows Input and Output power as single carrier or single-tone levels. IM Products vs. Input Power 22.0 24.0 26.0 28.0 30.0 32.0 Input Power (dBm) Output Power (dBm) -55.0 -50.0 -45.0 -40.0 -35.0 -30.0 -25.0 -20.0 -15.0 IM Products (dBc) Pout Im3, dBc 1.0 1.0-1.0 10.0 10.0 -10.0 5.0 5.0 -5.0 2.0 2.0 -2.0 3.0 3.0 -3.0 4.0 4.0 -4.0 0.2 0.2 -0.2 0.4 0.4 -0.4 0.6 0.6 -0.6 0.8 0.8 -0.8 FPD4000AF IP3 CONTOURS 2 GHz Swp Max 189 Swp Min IP3_dBm = 58 dBm IP3_dBm = 56 dBm IP3_dBm = 54 dBm IP3_dBm = 52 dBm IP3_dBm = 50 dBm IP3_dBm = 48 dBm IP3_dBm = 46 dBm IP3_dBm = 44 dBm IP3_dBm = 42 dBm NOTE: IP3 contours generated with P IN = 11dB back-off from P 1dB. Local maximum for best linearity located at: ΓS = 15 – j12 Ω and ΓL ≈ 15 – j15 Ω (IP3 value labels on contours are fitted values, and do not represent actual device performance.)

Phone: +1 408 850-5790 http:// www.filcs.com Revised: 08/09/04 Fax: +1 408 850-5766 Email: sales@filcsi.com ACPR measurement at 4 dB back-off from P 1dB with WCDMA BTS Forward modulation: FPD4000AF ADJACENT AND ALTERNATE CHANNEL POWER RATIOS WCDMA BTS FORWARD 10.15 dB Pk/Avg 0.001% f = 2.5 GHz STD. BIAS -70 -60 -50 -40 -30 -20 -10 9 1 01 11 21 31 41 51 61 71 81 92 02 12 2 Input Power (dBm) ACPR (dBc) Output Power (dBm) ADJ CHANNEL (5 MHz) ALT CHANNEL (10 MHz) OUTPUT POWER

Phone: +1 408 850-5790 http:// www.filcs.com Revised: 08/09/04 Fax: +1 408 850-5766 Email: sales@filcsi.com 1.0 1.0-1.0 10.0 10.0 -10.0 5.0 5.0 -5.0 2.0 2.0 -2.0 3.0 3.0 -3.0 4.0 4.0 -4.0 0.2 0.2 -0.2 0.4 0.4 -0.4 0.6 0.6 -0.6 0.8 0.8 -0.8 FPD4000AF P1dB CONTOURS 2 GHz Swp Max 194 Swp Min Pout_dBm = 36 dBm Pout_dBm = 34 dBm Pout_dBm = 32 dBm Pout_dBm = 30 dBm Pout_dBm = 28 dBm Pout_dBm = 26 dBm NOTE: Power contours measured at constant input power, level set to meet nominal P 1dB rating at optimum match point. Optimum match: ΓS = 3 – j11.5 Ω and ΓL = 15 – j6.5 Ω FPD4000AF I-V Curves 0.0 0.5 1.0 1.5 2.0 2.5 Drain-Source Voltage (V) Drain-Source Current (A) VGS = 0V VGS = -0.25V VGS = -0.50V VGS = -0.75V VGS = -1.0V

Phone: +1 408 850-5790 http:// www.filcs.com Revised: 08/09/04 Fax: +1 408 850-5766 Email: sales@filcsi.com

• RF PERFORMANCE OVER FREQUENCY: Note: The FPD4000AF is suitable for applications up to 4 GHz. 123456789 1 0 1 1 1 2 Frequency (GHz) Max Stable Gain FPD4000AF -20 -10 MSG S21

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• STANDARD EVALUATION BOARD (1.70-1.85 GHZ): NOTE: AutoCAD drawing available on Website Bill of Materials for Evaluation Board, FPD4000AF EV-BL-000026-002-A Designator Part Number Description Quantity C1 ATC600S0R9JW250 Capacitor, 0.9 pF, 0603, ATC 600, tol. + 5% 1 C2 ATC600S3R0JW250 Capacitor, 3.0 pF, 0603, ATC 600, tol. + 5% 1 C3 ATC600S1R8JW250 Capacitor, 1.8 pF, 0603, ATC 600, tol. + 5% 1 C4 ATC600S1R0JW250 Capacitor, 1.0 pF, 0603, ATC 600, tol. + 5% 1 C5 ATC600S330JW250 Capacitor, 33 pF, 0603, ATC 600, tol. + 5% 1 C6 T491B105M035AS7015 Capacitor, 1 µF, SMD-B, Kemet, tol. +20% 1 C7 ATC600S1R5JW250 Capacitor, 1.5 pF, 0603, ATC 600, tol. + 5% 1 C8 ATC600S330JW250 Capacitor, 33 pF, 0603, ATC 600, tol. + 5% 1 C9 ATC600S330JW250 Capacitor, 33 pF, 0603, ATC 600, tol. + 5% 1 C10 T491B105M035AS7015 Capacitor, 1 µF, SMD-B, Kemet, tol. +20% 1 R1 RCI-0603-10R1J Resistor, 100 Ω, 0603, IMS, tol. +5% 1 Q1 FPD4000AF Packaged Discrete pHEMT, Filtronic 1 PC-SP-000022-002 PCB, FPD4000AF Eval Board, 2 GHz 1 142-0711-841 Connector, RF, SMA End Launch, Jack Assy, Johnson 2 AMP-103185-2 Connector, DC, 0.100 on center, 0.025 sq. posts, Tyco 2 TF-SP-000025 Test Fixture Base, Flange Mount Package, 2 GHz 1 Screw, #2-56 20 C10 C8C7 C4C3 R1C2 RF IN VdVg

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