FPD3000 FILTRONIC | Alldatasheet

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Technical content

Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 11/17/04 Fax: +1 408 850-5766 Email: sales@filcsi.com

  • FEATURES ♦ 32.5 dBm Linear Output Power at 12 GHz ♦ 6.5 dB Power Gain at 12 GHz ♦ 8 dB Maximum Stable Gain at 12 GHz ♦ 42 dBm Output IP3 ♦ 30% Power-Added Efficiency
  • DESCRIPTION AND APPLICATIONS The FPD3000 is an AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (PHEMT), featuring a 0.25 µm by 3000 µm Schottky barrier gate, defined by high-resolution stepper-based photolithography. The recessed and offset Gate st ructure minimizes parasitics to optimize performance. The epitaxial structure and proce ssing have been optimized for reliable high-power applications. The FPD3000 also features Si 3N4 passivation and is available in a P100 flanged ceramic package and in the low cost plastic SOT89 plastic package. Typical applications include commercial and other narrowband and broadband high-performance amplifiers, including SATCOM uplink transmitters, PCS/Cellular low-voltage high-efficiency output amplifiers, and medium-haul digital radio transmitters.
  • ELECTRICAL SPECIFICATIONS AT 22°C Parameter Symbol Test Conditions Min Typ Max Units RF SPECIFICATIONS MEASURED AT f = 12 GHz USING CW SIGNAL Power at 1dB Gain Compression P 1dB V DS = 8 V; IDS = 50% IDSS 31.5 32.5 dBm Maximum Stable Gain (S21/S12) SSG V DS = 8 V; IDS = 50% IDSS 7.0 8.0 dB Power Gain at P1dB G 1dB V DS = 8 V; IDS = 50% IDSS 6.0 6.5 dB Power-Added Efficiency PAE VDS = 8 V; IDS = 50% IDSS; POUT = P1dB 30 % Output Third-Order Intercept Point (from 15 to 5 dB below P1dB) IP3 V DS = 8V; IDS = 50% IDSS Matched for optimal power Tuned for best IP3 dBm Saturated Drain-Source Current I DSS V DS = 1.3 V; VGS = 0 V 750 930 1100 mA Maximum Drain-Source Current I MAX VDS = 1.3 V; VGS ≅ +1 V 1.5 A Transconductance G M VDS = 1.3 V; VGS = 0 V 800 mS Gate-Source Leakage Current I GSO V GS = -5 V 10 µA Pinch-Off Voltage |V P| V DS = 1.3 V; IDS = 3 mA 1.0 V Gate-Source Breakdown Voltage |V BDGS| I GS = 3 mA 12.0 14.0 V Gate-Drain Breakdown Voltage |V BDGD| I GD = 3 mA 14.5 16.0 V Thermal Resistivity (see Notes) θJC VDS > 6V 20 °C/W DRAIN BOND PAD (4X) SOURCE BOND PAD (2x) GATE BOND PAD (4X) DIE SIZE (µm): 830 x 470 DIE THICKNESS: 75 µm BONDING PADS (µm):> 7 5x6 0

Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 11/17/04 Fax: +1 408 850-5766 Email: sales@filcsi.com

  • ABSOLUTE MAXIMUM RATINGS1 Parameter Symbol Test Conditions Min Max Units Drain-Source Voltage V DS -3V < VGS < +0V 8 V Gate-Source Voltage V GS 0V < VDS < +8V -3 V Drain-Source Current I DS For VDS > 2V I DSS mA Gate Current I G Forward or reverse current 25 mA RF Input Power2 P IN Under any acceptable bias state 600 mW Channel Operating Temperature T CH Under any acceptable bias state 175 ºC Storage Temperature T STG Non-Operating Storage -40 150 ºC Total Power Dissipation P TOT See De-Rating Note below 7.3 W Gain Compression Comp. Under any bias conditions 5 dB Simultaneous Combination of Limits3 2 or more Max. Limits 80 % 1TAmbient = 22°C unless otherwise noted 2Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3Users should avoid exceeding 80% of 2 or more Limits simultaneously Notes:
  • Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device.
  • Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib.
  • Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where P DC: DC Bias Power PIN: RF Input Power POUT: RF Output Power
  • Absolute Maximum Power Dissipation to be de-rated as follows above 22°C: PTOT= 7.3W – (0.05W/°C) x THS where THS = heatsink or ambient temperature above 22°C Example: For a 85 °C heatsink temperature: PTOT = 7.3W – (0.05 x (85 – 22)) = 4.2W
  • HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised duri ng handling. Proper Electrostatic Discharge (ESD) precautions should be observed at al l stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A per ESD-STM5.1- 1998, Human Body Model. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.
  • ASSEMBLY INSTRUCTIONS The recommended die attach is gol d/tin eutectic solder under a nitrogen atmosphere. Stage temperature should be 280-290°C; maximum time at temperature is one minute. The recommended wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm) gold wire. Stage temperature should be 250-260°C.
  • APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filt ronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data , and large-signal models are available on the Filtronic web site. All information and specifications are subject to change without notice.