FPD2250DFN

FPD2250DFN FILTRONIC | Alldatasheet

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Technical content

FPD2250DFN LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT

• PERFORMANCE (1850 MHz) ♦ 29 dBm Output Power (P1dB) ♦ 16.5 dB Small-Signal Gain (SSG) ♦ 1.0 dB Noise Figure ♦ 42 dBm Output IP3 ♦ 50% Power-Added Efficiency ♦ Evaluation Boards Available ♦ Featuring Lead Free Finish Package
• DESCRIPTION AND APPLICATIONS The FPD2250DFN is a packaged depletion mode AlGaAs/InGaAs pseudo morphic High Electron Mobility Transistor (pHE MT). It utilizes a 0.25 μm x 1500 μm Schottky barrier Gate, defined by high-resolution stepper-based photol ithography. The recessed and offs et Gate structure minimizes parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a range of bias conditions and input power levels. The FPD2250DFN is available in die form and in other packages. Typical applications include driv ers or output stages in PCS/Cellu lar base station high-intercept- point LNAs, WLL and WLAN systems, and other types of wireless infrastructure systems.
• ELECTRICAL SPECIFICATIONS AT 22°C Parameter Symbol Test Conditions Min Typ Max Units RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL Power at 1dB Gain Compression P1dB VDS = 5 V; IDS = 50% IDSS 28 29 dBm Small-Signal Gain SSG VDS = 5 V; IDS = 50% IDSS 15 16.5 dB Power-Added Efficiency PAE VDS = 5 V; IDS = 50% IDSS; POUT = P1dB 50 % Noise Figure NF VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 25% IDSS 1.0 0.8 1.75 dB Output Third-Order Intercept Point (from 15 to 5 dB below P1dB) IP3 VDS = 5V; IDS = 50% IDSS Matched for optimal power Matched for best IP3 dBm Saturated Drain-Source Current IDSS VDS = 1.3 V; VGS = 0 V 560 700 825 mA Maximum Drain-Source Current IMAX VDS = 1.3 V; VGS ≅ +1 V 1.1 A Transconductance GM VDS = 1.3 V; VGS = 0 V 600 mS Gate-Source Leakage Current IGSO VGS = -5 V 1 10 μA Gate-Source Breakdown Voltage |VBDGS| IGS = 2.25 mA 12 16 V Gate-Drain Breakdown Voltage |VBDGD| IGD = 2.25 mA 12 16 V Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis.com Revised: 11/14/05 Fax: +1 408 850-5766 Email: sales@filcsi.com

FPD2250DFN LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis.com Revised: 11/14/05 Fax: +1 408 850-5766 Email: sales@filcsi.com

• ABSOLUTE MAXIMUM RATINGS1 Parameter Symbol Test Conditions Min Max Units Drain-Source Voltage VDS -3V < VGS < +0V 8 V Gate-Source Voltage VGS 0V < VDS < +8V -3 V Drain-Source Current IDS For VDS > 2V IDSS mA Gate Current IG Forward or reverse current 22 mA RF Input Power2 PIN Under any acceptable bias state 525 mW Channel Operating Temperature TCH Under any acceptable bias state 175 ºC Storage Temperature TSTG Non-Operating Storage -40 150 ºC Total Power Dissipation PTOT See De-Rating Note below 3.0 W Gain Compression Comp. Under any bias conditions 5 dB Simultaneous Combination of Limits3 2 or more Max. Limits 80 % 1TAmbient = 22°C unless otherwise noted 2Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3Users should avoid exceeding 80% of 2 or more Limits simultaneously Notes:
• Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device.
• Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where: PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power
• Total Power Dissipation to be de-rated as follows above 22°C: PTOT= 3.0W – (0.025W/°C) x TPACK where TPACK = package lead temperature above 22°C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65 °C package lead temperature: PTOT = 3.0W – (0.025 x (65 – 22)) = 1.93W
• The use of a filled via-hole directly be neath the exposed heatsink tab on the bottom of the package is strongly recommended to provide for adequate thermal management. Ideally the bo ttom of the circuit board is affixed to a heatsink or thermal radiator.
• HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised duri ng handling. Proper Electrostatic Discharge (ESD) precautions should be observed at al l stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A per ESD-STM5.1- 1998, Human Body Model. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.
• APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filt ronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. Evaluation Boards available upon request.

FPD2250DFN LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT

• BIASING GUIDELINES ¾ Active bias circuits provide good performance stab ilization over variations of operating temperature, but require a larger number of com ponents compared to self -bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is ap plied before Drain bias, otherwise the pHEMT may be indu ced to self-oscillate. Contact your Sales Representative for additional information. ¾ Dual-bias circuits are relatively simple to im plement, but will requir e a regulated negative voltage supply for depletion-mode devices such as the FPD2250DFN. ¾ For standard Class A operation, a 50% of I DSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. Note that pHEMTs, since they are “quasi- E/D mode” devices , exhibit Class AB tra its when operated at 50% of IDSS. To achieve a larger separation between P 1dB and IP3, an operating point in the 25% to 33% of I DSS range is suggested. Such Class AB operation will not degrade the IP3 performance.
• PACKAGE OUTLINE (dimensions in mm) All information and specifications subject to change without notice. Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis.com Revised: 11/14/05 Fax: +1 408 850-5766 Email: sales@filcsi.com

FPD2250DFN LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT

• PCB FOOT PRINT
• TYPICAL I-V CHARACTERISTICS DC IV Curves FPD2250SOT89 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 Drain-Source Voltage (V) Drain-Source Current (A) VG=-1.50V VG=-1.25V VG=-1.00V VG=-0.75V VG=-0.50V VG=-0.25V VG=0V Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis.com Revised: 11/14/05 Fax: +1 408 850-5766 Email: sales@filcsi.com

FPD2250DFN LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis.com Revised: 11/14/05 Fax: +1 408 850-5766 Email: sales@filcsi.com Note: The recommended method for measuring IDSS, or any particular IDS, is to set the Drain-Source voltage (VDS) at 1.3V. This measurement point avoids th e onset of spurious self-oscillation which would normally distort the current measurement (thi s effect has been filtered from the I-V curves presented above). Setting the V DS > 1.3V will generally cause errors in the current measurements, even in stabilized circuits. Recommendation: Traditionally a device’s IDSS rating (IDS at VGS = 0V) was used as a predictor of RF power, and for MESFETs there is a correlation between I DSS and P 1dB (power at 1dB gain compression). For pHEMTs it ca n be shown that there is no meaningful statistical correlation between IDSS and P 1dB; specifically a linear regr ession analysis shows r 2 < 0.7, and the regression fails the F-statistic test. I DSS is sometimes useful as a guide to circuit tuning, since the S 22 does vary with the quiescent operating point IDS.