FPD1500SOT89

FPD1500SOT89_1 FILTRONIC | Alldatasheet

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LOW NOISE HIGH LINEARITY PACKAGED PHEMT Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Tel: +44 (0) 1325 301111 Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com Datasheet v3.0 FPD1500SOT89 FEATURES (1850MHZ):

• 27.5 dBm Output Power (P1dB)
• 17 dB Small-Signal Gain (SSG)
• 1.2 dB Noise Figure
• 42 dBm Output IP3
• 50% Power-Added Efficiency
• FPD1500SOT89E - RoHS compliant GENERAL DESCRIPTION: The FPD1500SOT89 is a packaged depletion mode AlGa As/InGaAs p seudomorphic Hig h Electron M obility Tr ansistor (pHEMT). It utilizes a 0.25 µm x 15 00 µm Schottky barrier gate, defined by high-resolution stepper-based photolithography. The d ouble recessed gat e structure minimize s pa rasitics to optimize performance, with a n epitaxial structure designed for improved linearity over a range of bias conditions and i/p power levels. PACKAGE: RoHS TYPICAL APPLICATIONS:
• Drivers or output stages in PCS/Cellular base station transmitter amplifiers
• High intercept-point LNAs
• WLL and WLAN systems, and other types of wireless infrastructure systems. ELECTRICAL SPECIFICATIONS: PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power at 1dB Gain Compression P1dB VDS = 5 V; IDS = 50% IDSS 26.0 27.5 dBm Small-Signal Gain SSG VDS = 5 V; IDS = 50% IDSS 15.5 17 dB Power-Added Efficiency PAE VDS = 5 V; IDS = 50% IDSS; POUT = P1dB 50 % Noise Figure NF VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 25% IDSS 1.0 1.2 dB Output Third-Order Intercept Point (from 15 to 5 dB below P1dB) IP3 VDS = 5V; IDS = 50% IDSS Matched for optimal power Matched for best IP3 dBm Saturated Drain-Source Current IDSS VDS = 1.3 V; VGS = 0 V 375 465 550 mA Maximum Drain-Source Current IMAX VDS = 1.3 V; VGS ≅ +1 V 750 mA Transconductance GM VDS = 1.3 V; VGS = 0 V 400 mS Gate-Source Leakage Current IGSO VGS = -5 V 1 15 µA Gate-Source Breakdown Voltage |VBDGS| IGS = 1.5 mA 12 16 V Gate-Drain Breakdown Voltage |VBDGD| IGD = 1.5 mA 12 16 V Thermal Resistance RθJC 60 °C/W Note: TAMBIENT = 22°; RF specification measured at f = 1850 MHz using CW signal (except as noted)

Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Tel: +44 (0) 1325 301111 Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com Datasheet v3.0 FPD1500SOT89 ABSOLUTE MAXIMUM RATING1: Notes: PARAMETER SYMBOL TEST CONDITIONS ABSOLUTE MAXIMUM Drain-Source Voltage VDS -3V < VGS < +0V 8V Gate-Source Voltage VGS 0V < VDS < +8V -3V Drain-Source Current IDS For VDS < 2V IDSS Gate Current IG Forward or reverse current 15mA RF Input Power PIN Under any acceptable bias state 350mW Channel Operating Temperature TCH Under any acceptable bias state 175°C Storage Temperature TSTG Non-Operating Storage -55°C to 150°C Total Power Dissipation PTOT See De-Rating Note below 2.3W Gain Compression Comp. Under any bias conditions 5dB Simultaneous Combination of Limits 2 or more Max. Limits 1TAmbient = 22°C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause permanent damage to the device 2Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3Users should avoid exceeding 80% of 2 or more Limits simultaneously 4Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power Total Power Dissipation to be de-rated as follows above 22°C: PTOT= 2.3 - (0.016W/°C) x TPACK w here TPACK= source tab lead temperature above 22°C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65°C carrier temperature: PTOT = 2.3W – (0.016 x (65 – 22)) = 1.61W BIASING GUIDELINES:

• Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias.
• Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices.
• For standard class A operation, a 50% of IDSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. A class A/B Bias of 25-33% of IDSS to achieve better OIP3, and Noise Figure performance is suggested.

Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Tel: +44 (0) 1325 301111 Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com Datasheet v3.0 FPD1500SOT89 FREQUENCY RESPONSE: Note: Device tuned for minimum noise figure Frequency (GHz) Biased @ 5V 50%IDSS 35Mag S21 & MSG MSG S21 Biased @ 5V, 200mA 0.2 0.4 0.6 0.8 1.2 1.4 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 5.7 Frequency (GHz) Noise FIgure (dB) N.F. (dB) TEMPERATURE RESPONSE: Biased @ 5V, 50%IDSS Data taken on Eval Board at 1.85GHz 12.0 13.0 14.0 15.0 16.0 17.0 18.0 -20 -10 Temperature (C) SSG (dB) 20.0 21.0 22.0 23.0 24.0 25.0 26.0 27.0 28.0 29.0 30.0 P1dB (dBm) SSG (dB) P1dB (dBm) Biased @ 5V, 33%IDSS Data taken on Eval board @ 1.85GHz .00 .10 .20 .30 .40 .50 .60 .70 -20 -10 Temperature (C) Noise Figure (dB) N.F. (dB) Note: Evaluation board tuned for maximum power

Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Tel: +44 (0) 1325 301111 Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com Datasheet v3.0 FPD1500SOT89 TYPICAL TUNED RF PERFORMANCE: Drain Efficiency and PAE .00% 10.00% 20.00% 30.00% 40.00% 50.00% 60.00% 70.00% Input Power (dBm) PAE (%) .00% 10.00% 20.00% 30.00% 40.00% 50.00% 60.00% 70.00% Drain Efficiency (%) PAE Eff. Power Transfer Characteristic 13.00 15.00 17.00 19.00 21.00 23.00 25.00 27.00 29.00 Input Power (dBm) Output Power (dBm) -.50 .00 .50 1.00 1.50 2.00 2.50 3.00 3.50 Gain Compression (dB) Pout Comp Point NOTE: Typical power and efficiency is shown above. The devices were biased nominally at VDS = 5V, IDS = 50% of IDSS, at a test freq uency of 1.85 GHz. T he test devices were tuned (input and output tuning) for maximum output power at 1dB gain compression. Typical Intermodulation Performance VDS = 5V IDS = 50% IDSS at f = 1.85GHz 15.00 17.00 19.00 21.00 23.00 25.00 Input Power (dBm) Output Power (dBm) -55.00 -50.00 -45.00 -40.00 -35.00 -30.00 -25.00 -20.00 -15.00 -10.00 3rd Oder IM Poroducts (dBc) Pout Im3, dBc Note: pH EMT devices have enhanced intermodulation performa nce. This yields OIP3 values of about P 1dB + 14dBm. T his IMD enhancement is affected by the quiescent bias and the matching applied to the device. TYPICAL I-V CHARACTERISTICS DC IV Curves FPD1500SOT89 0.00 0.10 0.20 0.30 0.40 0.50 0.60 Drain-Source Voltage (V) Drain-Source Current (A) VG=-1.5V VG-1.25V VG=-1.00V VG=-0.75V VG=-0.5V VG=-0.25V VG=0V Note: The recommended method for meas uring IDSS, or any particular IDS, is to set the Drain-Source voltage (VDS) at 1.3V. T his measur ement poi nt avoi ds the ons et o f spurious self-oscillation which would normally distort the current me asurement (this ef fect has bee n filtered from the I-V curves presented above). Setting the VDS > 1.3V will generally cause errors in the current me asurements, even in stabilized circuits.

Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Tel: +44 (0) 1325 301111 Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com Datasheet v3.0 FPD1500SOT89 TYPICAL OUTPUT PLANE POWER CONTOURS (VDS = 5v, IDS = 50%IDSS) : TYPICAL SCATTERING PARAMETERS (50Ω SYSTEM):

1850 MHz

Contours swept with a constant input power, set so that optimum P1dB is achieved at the point of output match. Input (Source plane) Γs: 0.74 ∠ 168.2º 0.15 + j0.1 (normalized) 7.5 + j5.0 Ω Nominal IP3 performance is obtained with this input plane match, and the output plane match as shown.

900 MHz

Contours swept with a constant input power, set so that optimum P1dB is achieved at the point of output match. Input (Source plane) Γs: 0.67 ∠ 103.6º 0.30 + j0.74 (normalized) 15 + j37.0 Ω Nominal IP3 performance is obtained with this input plane match, and the output plane match as shown. 10.0 -10.0 5.0 -5.0 3.0 -3.0 4.0 -4.0 0.2 -0.2 0.4 -0.4 Swp Max 123 Swp Min 28dBm 26dBm 25dBm 24dBm 23dBm 22dBm 27dBm 10.0 -10.0 5.0 -5.0 3.0 -3.0 4.0 -4.0 0.2 -0.2 0.4 -0.4 Swp Max 159 Swp Min 28dBm 26dBm 25dBm 24dBm 23dBm 22dBm 27dBm 1.0 1.0-1.0 10.0 10.0 -10.0 5.0 5.0 -5.0 2.0 2.0 -2.0 3.0 3.0 -3.0 4.0 4.0 -4.0 0.2 0.2 -0.2 0.4 0.4 -0.4 0.6 0.6 -0.6 0.8 0.8 -0.8 FPD1500SOT89 5V / 50%IDSS Swp Max 8GHz Swp Min 0.5GHz S11

1 GHz

1.5 GHz

2 GHz

2.5 GHz

3 GHz

3.5 GHz

4 GHz

5 GHz 6 GHz

7 GHz

10.0 -10.0 5.0 -5.0 3.0 -3.0 4.0 -4.0 0.2 -0.2 0.4 -0.4 FPD1500SOT89 5V / 50%IDSS Swp Max 8GHz Swp Min 0.5GHz S22

5 GHz 6 GHz 7 GHz

Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Tel: +44 (0) 1325 301111 Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com Datasheet v3.0 FPD1500SOT89 STATISTICAL SAMPLE OF RF PERFORMANCE: Noise Figure 1000 2000 3000 4000 5000 6000 NF (dB) Count Small Signal Gain 2000 4000 6000 8000 10000 12000 14000 13 14 15 16 17 18 Gain (dB) Count Output 3 rd -Order Intercept Point 1000 2000 3000 4000 5000 6000 30 32 34 36 38 40 42 44 IP3 (dBm) Count Output Power at 1dB Gain Compression 2000 4000 6000 8000 10000 12000 14000 23 24 25 26 27 28 P1dB (dBm) Count Note: T he d evices were tested by a h igh-speed automatic test s ystem, in a m atched circuit based on 2GHz Evaluation Board. This circuit is a dua l-bias single-pole lowpass topology, and the d evices were biased at V DS = 4.5V, IDS = 120mA, Test Frequency = 2.0GHz. The performance data is summarized below: Parameter Median Standard Deviation Test Limit CPK Small-Signal Gain 15.5 0.20 14.5 1.7 Noise Figure 0.91 0.03 1.20 3.2 Output Power (P1dB) 25.2 0.25 24.5 0.93 rd -Order Intercept 38.7 1.1 36.5 0.67

Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Tel: +44 (0) 1325 301111 Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com Datasheet v3.0 FPD1500SOT89 REFERENCE DESIGN 0.9GHZ FREQUENCY GHZ 0.9 Gain dB 20 P1dB dBm 27 OIP31 dBm 39 N.F. dB 0.7 S11 dB -5 S22 dB -15 Vd V 5 Vg V -0.4 to -0.6 Id mA 200 1. Measured at 15dBm per tone Board Layout 33pF Lg 33pF L1 0.01uF 20O + 1.0uF Q1 C1 33pF Ld 33pF 0.01uF + Vg Vd 1.45" 0.63" Component Values Eval board material - 31mil thick FR4 with 1/2 Ounce Cu on both sides Component Value Description Lg 47nH LL1608 Toko chip inductor Ld 47nH LL1608 Toko chip inductor L1 12nH LL1005 Toko chip inductor L2 4.7nH LL1005 Toko chip inductor C1 5.6pF ATC 600S chip capacitor 33pF 33pF

20 Ohm

0.01uF 0.01uF 1.0uF Vd-Vg 47 nH 47 nH C1RF IN RF OUT Schematic other capacitors are 0603 and 0805 standard chip capacitors. A 0603 size 20 Ohm Chip resistor from Vishay is used on the gate D.C. bias line for stability.

Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Tel: +44 (0) 1325 301111 Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com Datasheet v3.0 FPD1500SOT89 REFERENCE DESIGN 1.85GHZ FREQUENCY GHZ 1.85 Gain dB 16 P1dB dBm 27 OIP31 dBm 41 N.F. dB 0.9 S11 dB -9 S22 dB -14 Vd V 5 Vg V -0.4 to -0.6 Id mA 200 1. Measured 15dBm per tone Board Layout Component Values Eval b material - 31mil thioard ck FR4 with 1/2 Ounce Cu on both sides Component Value Description Lg 27nH LL160 ductor8 Toko chip in Ld 27nH LL1608 Toko chip inductor L1 1.5nH LL1005 Toko chip inductor L2 4.7nH LL1005 Toko chip inductor C1 2.2pF ATC 600S chip capacitor 33pF 33pF 0.01uF 0.01uF 1.0uF Vd-Vg 27 nH 27 nH C1RF IN RF OUT 33pF Lg 33pF L1 0.01uF 20O + 1.0uF Q1 C1 33pF Ld 33pF 0.01uF + Vg Vd 1.45" 0.63" Schematic D.C. Blocking capacitors are ATC series 600S. A t the drain terminal. All tantalum 1.0µF is used a other capacitors are 0603 and 0805 standard chip capacitors. A 0603 size 20 Ohm Chip resistor from Vishay is used on the gate D.C. bias line for stability.

Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Tel: +44 (0) 1325 301111 Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com Datasheet v3.0 FPD1500SOT89 REFERENCE DESIGN 2.4 TO 2.6GHZ FREQUENCY GHZ 2.4 2.6 Gain dB 12.5 12.4 P1dB d Bm 28 28 OIP31 dBm 39 40 N.F. dB 1.0 0.9 S11 dB -14 -16 S22 dB -5 -6 Vd V 5 5 Id mA 200 200 1. Measured at 1 per 5dBm tone 20O 33pF 0.01uF Lg L1 33pFC2 33pF 33pF Ld 0.01uF + 1.0uF Vg Vd 1.45" 0.63" Component Values Ev ter il th n al board ma ial - 31m ick FR4 with 1/2 Ounce Cu o both sides Component Value Description Lg 18nH LL1608 ductor Toko chip in Ld 18nH LL1608 Toko chip inductor L1 0.0nH No Component (Cu Tab) L2 3.9nH L L1005 Toko chip inductor C1 2 & C 1.0pF ATC 600S chip capacitor 33pF 33pF 0.01uF 0.01uF 1.0uF Vd-Vg 18 nH 18 nH C2RF IN RF OUT Board Layout Schematic other capacitors are 0603 and 0805 standard chip capacitors. A 0603 size 20 Ohm Chip resistor from Vishay is used on the gate D.C. bias line for stability. D

Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Tel: +44 (0) 1325 301111 Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com Datasheet v3.0 FPD1500SOT89 S-PARAMETERS: BIASED @ 5V, 50%IDSS: FREQ[GHz] S11m S11a S21m S21a S12m S12a S22m S22a 0.500 0.865 -91.9 18.828 121

Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Tel: +44 (0) 1325 301111 Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com Datasheet v3.0 FPD1500SOT89 PACKAGE OUTLINE: (dimensions in millimeters – mm) FWYN

• Also available with horizontal part orientation
• Hub diameter = 80mm
• Devices per reel = 1000 TAPE DIMENSIONS AND PART ORIENTATION:

Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Tel: +44 (0) 1325 301111 Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com Datasheet v3.0 FPD1500SOT89 DEVICE FOOT PRINT: This package is compatible with both lead free and leaded solder reflow processes as defined within IPC/JEDEC J-STD-020C. The maximum package te mperature should not exceed 260°C. HANDLING PRECAUTIONS: To avoid d amage to the device s ca re should b e exercised during han dli Proper El ectrostatic Di scharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. ESD/MSL RATING: These devices should be treated as Class 0 (0-

250 V ) u sing the h uman body model a s

defined in JEDEC Standard No. 22-A114. The device h as a MSL ra ting of Level 2. To determine this ratin g, pre conditioning wa s performed to the device per, the Pb-free solder defined within IPC/JEDEC J-STD-020C, oisture / Reflow sensitivity classification for non-hermatic solid stat e surfa ce mount devices. APPLICATION NOTES & DESIGN DATA: Application Notes and design data including S- parameters, noise parameters and device model are available on request. RELIABILITY: A MTTF of 7.4 million h ours at a channel temperature of 150° C is a chieved for the process used to manufacture this device. DISCLAIMERS: This product is not designed for use in any space based or life sustaining/supporting equipment. ORDERING INFORMATION: NOTE: Drawing available on Website PREFERRED ASSEMBLY INSTRUCTIONS: ng. PART NUMBER DESCRIPTION FPD1500SOT89 Packaged pHEMT FPD1500SOT89E RoHS Compliant Packaged pHEMT FPD1500SOT89CE RoHS Compliant Packaged pHEMT with enhanced passivation (Recommended for New Designs) EB1500SOT89(E)-BB 0.9 GHz evaluation board EB1500SOT89(E)-BA 1.85 GHz evaluation board EB1500SOT89(E)-BC 2.0 GHz evaluation board EB1500SOT89(E)-BD 2.2 GHz evaluation board EB1500SOT89(E)-BE 2.4 GHz evaluation board EB1500SOT89(E)-BG 2.6 GHz evaluation board EB1500SOT89(E)-AJ 5.3-5.75 GHz evaluation board Units in inches profile M