FLGA STATSCHIP | Alldatasheet

Document overview

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Technical content

www.statschippac.com

FEATURES

  • Low profile  Flexible body sizes range from 4 x 4mm to 13 x 13mm  Flip chip and discrete passive options (SiP)  Minimum 0.50mm pitch (array and peripheral land pads)  Flexible land pattern arrangement  Pb-free and halogen-free compatible materials available  JEDEC standard compliant

APPLICATIONS

 Handheld devices  Wireless RF  Analog  ASIC  Memory  Simple PLDs

  • Array molded, cost effective, space-saving packaging solution  Available in 1.20mm (TFLGA), 1.00mm (VFLGA), and 0.80mm (WFLGA) maximum thickness  Thinner than FBGA  Exposed thermal/mechanical lands available  Laminate substrate based enabling 2 and 4 layers of routing flexibility

DESCRIPTION

STATS ChipPAC’s FLGA is a laminate substrate based package with plastic overmolded encapsulation. Unlike a standard FBGA, second level interconnect is achieved on the LGA by connecting “lands” on the package directly onto the PCB through solder re-flow. The elimination of solder balls brings better electrical performance and lower package profile without using the more expensive thinner BT core material. It also offers the flexibility of land pattern arrangement in the form of signal lands or heat spreader/ground pads to suit the thermal and electrical requirements of various devices. The FLGA package’s reduced outline and thickness make it an ideal advanced technology packaging solution for high performance and/or portable applications. STATS ChipPAC’s FLGA is available in a broad range of JEDEC standard body sizes including TFLGA (<1.20mm), VFLGA (<1.00mm) and WFLGA (<0.80mm) package thickness. FLGA Fine Pitch Land Grid Array

The STATS ChipPAC logo is a registered trademark of ST ATS ChipPAC Ltd. All other product names and other company names herein are for identification purposes only and may be the trademarks or r egistered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warr anty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice. ©Copyright 2006. STATS ChipPAC Ltd. All rights reserved. May 2006 Corporate Office 10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 Global Offices USA 510-979-8000 JAPAN 81-3-5789-5850 CHINA 86-21-5976-5858 MALAYSIA 603-4257-6222 KOREA 82-31-639-8911 TAIWAN 886-3-593-6565 UK 44-1483-413-700 NETHERLANDS 3 1-38-333-2023 FLGA Fine Pitch Land Grid Array SPECIFICATIONS Die Thickness 75–300µm (3-12 mils) Mold Cap Thickness 0.25-0.90mm Marking Laser Packing Options Tape & reel/JEDEC tray RELIABILITY Moisture Sensitivity Level JEDEC Level 2A, 260°C Reflow Temperature Cycling Condition C (–65°C to 150°C), 1000 cycles High Temp Storage 150°C, 1000 hrs Pressure Cooker Test 121°C/100%RH/2atm, 168 hrs Temperature/Humidity Test 85°C/85% RH, 1000 hrs Unbiased HAST 130°C/85% RH/2 atm, 96 hrs CROSS-SECTION PACKAGE CONFIGURATIONS Body Sizes (mm) 4x4 to 13x13 Terminal Count 8 to 200 Terminal Pitch (mm) 0.50 to 0.80 Typ. Pkg. Thickness TFLGA: 1.20mm VFLGA: 1.00mm max. WFLGA: 0.80mm max. ELECTRICAL PERFORMANCE Electrical parasitic data is highly dependent on the package layout. 3D electrical simulation can be used on the specific packa ge design to provide the best prediction of electrical behavior. First order approximations can be calculated using parasitics per unit length for the constituents of the signal path. Data below is for a frequency of 100MHz and assumes 1.0 mil gold bonding wire. Conductor Length Resistance Inductance Inductance Capacitance Capacitance Component (mm) (mOhms) (nH) Mutual (nH) (pF) Mutual (pF) Note: Net = Total Trace Length + Via FLGA THERMAL PERFORMANCE, θθθθθja (°C/W) Thermal performance is highly dependent on package size, die size, substrate layers and thickness, and land configuration. Simulation for specific applications should be performed to obtain maximum accuracy. Package Body Size (mm) Pin Count Die Size PCB Vias Thermal Performance θja(ºC/W) VFLGA 9 x 9 (4L) 112 4.1 x 4.1 16 36.1 Note: Simulation data for package mounted on 4 layer PCB (per JEDEC JESD51-9) under natural convection as defined in JESD51-2.