FBGA-SD STATSCHIP | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 2
Technical content
www.statschippac.com
FEATURES
- 2 die to 7 die stack with spacer capability 5 x 5mm to 23 x 23mm body size Flexible die stacking options (“pyramid,” “same die,” etc.) 0.5mm to 1.0mm ball pitch, Eutectic and Lead-free solder ball Flash/SRAM/PSRAM/Logic/Analog combinations JEDEC standard package outlines Die thinning to 75um (3mils) capability Low loop wire bonding; reverse and die to die Up to 2mm die overhang per side Halogen-free and Low-K wafer compatible BOM Ball counts up to 450 balls
- FBGA-SD: Laminate substrate based enabling 2 & 4 layers of routing flexibility FBGA-T-SD: Single metal layer tape based substrate with dense routing & good electrical performance Available in 1.4mm (LFBGA-SD), 1.2mm (TFBGA- SD/TFBGA-T-SD), 1.0mm (VFBGA-SD/VFBGA-T- SD) & 0.80mm (WFBGA-SD) maximum package thickness Stacking of die allows for more functionality in an array molded, cost effective, space saving package solution
DESCRIPTION
STATS ChipPAC’s Fine Pitch Ball Grid Array Stacked Die (FBGA-SD) offering includes LFBGA-SD, TFBGA-SD, VFBGA-SD and WFBGA-SD packages. Tape versions of VFBGA-SD and TFBGA-SD are also available. STATS ChipPAC’s chip stack technology offers the flexibility of stacking 2 to 7 die in a single package. Die to die bonding capability enables device and signal integration to improve electrical performance and reduce overall package I/O requirements. Wafer thinning technology, overhang wire bond technology and the use of spacers between stacked die provide the flexibility to stack almost any desirable configuration of die in one package. This capability uses existing assembly infrastructure, which results in more functional integration with lower overall package cost. The use of the latest packaging materials allows this package to meet JEDEC Moisture Resistance Test Level 2a with Lead-free reflow conditions. This is an ideal package for cell phone applications where Digital, Flash, SRAM, PSRAM and Logic are stacked into a single package. FBGA-SD Fine Pitch Ball Grid Array - Stacked Die
APPLICATIONS
Suitable for a variety of applications including memory integration (ASIC or Logic) Chipset integration (Analog/Digital), mixed technologies integration (Baseband/RF) Handheld products (Cellular Phones, Pagers, MP3 Players, GPS) Consumer electronics (Internet applications, Digital Cameras/Camcorders) Computers (Network PCs) PC peripherals (Disk Drivers, DC-R/RW, Mini Disk, DVD Drivers)
The STATS ChipPAC logo is a registered trademark of ST ATS ChipPAC Ltd. All other product names and other company names herein are for identification purposes only and may be the trademarks or r egistered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warr anty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice. ©Copyright 2006. STATS ChipPAC Ltd. All rights reserved. May 2006 Corporate Office 10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 Global Offices USA 510-979-8000 JAPAN 81-3-5789-5850 CHINA 86-21-5976-5858 MALAYSIA 603-4257-6222 KOREA 82-31-639-8911 TAIWAN 886-3-593-6565 UK 44-1483-413-700 NETHERLANDS 3 1-38-333-2023 FBGA-SD Fine Pitch Ball Grid Array - Stacked Die SPECIFICATIONS Die Thickness 75-165µm (3-6.5 mils) Mold Cap Thickness 0.45-0.9mm Marking Laser Packing Options JEDEC tray/tape and reel RELIABILITY Moisture Sensitivity Level JEDEC Level 2A, 260°C reflow Temperature Cycling Condition C (-65°C to 150°C, 1000 cycles High Temperature Storage 150°C, 1000 hrs Pressure Cooker Test 121°C/100% RH/2 atm, 168 hrs Temperature/Humidity Test 85°C/85% RH, 1000 hrs Unbiased HAST 130°C/85% RH, 2 atm, 96 hrs CROSS-SECTION Mold compound Solder ballsWire bonds Die Substrate PACKAGE CONFIGURATIONS Package Pkg Th ickness Body Size Ball Ball Pitch Type (typical) mm (mm) Count (mm) LFBGA-SD 1.7, 1.4 max Range: 4x4 ~ 23x23 TFBGA-SD 1.2 max Common Sizes: 5x10, 7x9, 8x10, VFBGA-SD 1.0 max 8x11, 8x14, 10x12, 10x14, WFBGA-SD 0.8 max 13x13, 15x15, 16x16, 17x17 TFBGA-T-SD 1.2 max VFBGA-T-SD 1.0 max 0.5 - 0.840-450 40-280 0.5 - 0.84x4 ~ 16x16 ELECTRICAL PERFORMANCE Electrical parasitic data is highly dependent on the package layout. 3D electrical simulation can be used on the specific packa ge design to provide the best prediction of electrical behavior. First order approximations can be calculated using parasitics per unit length for the constituents of the signal path. Data below is for a frequency of 100MHz and assumes 1.0 mil gold bonding wire. Conductor Length Resistance Inductance Inductance Capacitance Capacitance Component (mm) (mOhms) (nH) Mutual (nH) (pF) Mutual (pF) Note: Net = Total Trace Length + Via + Solder Ball. 2 die 3 die (2 functional die + 1 spacer die) 4 die (3 functional die + 1 spacer die) 5 die (3 functional die + 2 spacer die)* (4 functional die + 1 spacer die) 6 die (4 functional die + 2 spacer die)* (5 functional die +1 spacer die) 7 die (4 functional die + 3 spacer die)* (5 functional die + 2 spacer die) * Shown in illustration.