FLEX6000

FLEX6000 ALTERA | Alldatasheet

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Technical content

March 2001, ver. 4.1 Data Sheet Typical gates (1) 10,00016,00016,00024,000 Logic elements (LEs)8801,3201,3201,960 Maximum I/O pins102204171218 Supply voltage (VCCINT)3.3 V5.0 V3.3 V3.3 V

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FLEX 6000 Programmable Logic Device Family Data Sheet EPF6010A71102 EPF6016117171199204 EPF6016A8181117171171 EPF6024A117171199218219

FLEX 6000 Programmable Logic Device Family Data Sheet 16-bit loadable counter16172153133MHz 16-bit accumulator16172153133MHz 24-bit accumulator24136123108MHz 16-to-1 multiplexer (pin-to-pin) (1) 1012.113.416.6ns 16 multiplier with a 4-stage pipeline592846758MHz

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FLEX 6000 Programmable Logic Device Family Data Sheet 8-bit, 16-tap parallel finite impulse response (FIR) filter 599948072MSPS 8-bit, 512-point fast Fourier transform (FFT) function 1,18275 109 S MHz universal asynchronous receiver/transmitter (UART) 487363025MHz PCI bus target with zero wait states609564942MHz

FLEX 6000 Programmable Logic Device Family Data Sheet

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FLEX 6000 Programmable Logic Device Family Data Sheet

FLEX 6000 Programmable Logic Device Family Data Sheet

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FLEX 6000 Programmable Logic Device Family Data Sheet LABCTRL1/ SYNCLR LABCTRL2 CLK1/SYNLOAD CLK2 LE 1 Dedicated Inputs

FLEX 6000 Programmable Logic Device Family Data Sheet Chip-Wide Reset Carry-In Clock Select Carry-Out Look-Up Table (LUT) Clear/ Preset Logic Carry Chain Cascade Chain Cascade-In Cascade-Out LE-Out PRN CLRN DQ data1 data2 data3 data4 labctrl1 labctrl2 labctrl3 labctrl4

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FLEX 6000 Programmable Logic Device Family Data Sheet

FLEX 6000 Programmable Logic Device Family Data Sheet LUTa1 Carry Chain LE 2 Register Carry Chain LE 3 Register Carry Chain snRegisteran bn Carry Chain Carry-Out LE n + 2 LE n + 1 Register Carry-In LUT LUT LUT

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FLEX 6000 Programmable Logic Device Family Data Sheet

FLEX 6000 Programmable Logic Device Family Data Sheet d[3..0] LE 2 LUT d[7..4] LE 3 LUT LE + 1LE + 1 LUT d[3..0] LUT d[7..4] LUT LUT LE 2 LE 3 d[(4 -1)..4( -1)] d[(4 -1)..4( -1)]

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FLEX 6000 Programmable Logic Device Family Data Sheet PRN CLRN DQ4-Input LUT Carry-In Cascade-Out Cascade-In LE-Out PRN CLRN DQ Cascade-Out LE-Out Cascade-In 3-Input LUT Carry-In 3-Input LUT Carry-Out data1 data2 PRN CLRN DQ Carry-In LE-OutLUT 3-Input 3-Input LUT Carry-Out data3 (data) Cascade-Out Cascade-In LAB-Wide Synchronous Load LAB-Wide Synchronous Clear data1 data2 data1 data2 data3 data4

FLEX 6000 Programmable Logic Device Family Data Sheet

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FLEX 6000 Programmable Logic Device Family Data Sheet

FLEX 6000 Programmable Logic Device Family Data Sheet PRN DQ labctrl1 or labctrl2 CLRN DQ Chip-Wide Reset labctrl1 or labctrl2 Chip-Wide Reset

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FLEX 6000 Programmable Logic Device Family Data Sheet 5555 To/From Adjacent LAB LE 1 through LE 5 LE 6 through LE 10 LE 1 through LE 5 LE 6 through LE 10 22 22 105 5 5 5 555 To/From Adjacent LAB 5 10 10 105

FLEX 6000 Programmable Logic Device Family Data Sheet

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FLEX 6000 Programmable Logic Device Family Data Sheet From Adjacent Local Interconnect LE LE

FLEX 6000 Programmable Logic Device Family Data Sheet EPF6010A41442220 EPF6016 EPF6016A 61442220 EPF6024A71862830

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FLEX 6000 Programmable Logic Device Family Data Sheet LAB C1 LAB (Repeated Across Device) LAB D1LAB D22 LAB C22

FLEX 6000 Programmable Logic Device Family Data Sheet From LAB Local Interconnect Slew-Rate Control From LAB Local Interconnect To Row or Column Interconnect Chip-Wide Output Enable Delay

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FLEX 6000 Programmable Logic Device Family Data Sheet IOE IOE LAB

FLEX 6000 Programmable Logic Device Family Data Sheet IOE IOE LAB

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FLEX 6000 Programmable Logic Device Family Data Sheet Designed for 256-Pin FineLine BGA Package Printed Circuit Board 100-Pin FineLine BGA Package (Reduced I/O Count or Logic Requirements) 256-Pin FineLine BGA Package (Increased I/O Count or Logic Requirements) 100-Pin FineLine BGA 256-Pin FineLine BGA EPF6016A EPF6024A

FLEX 6000 Programmable Logic Device Family Data Sheet 3.32.5 3.33.3 (1) 5.03.3 5.05.0

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FLEX 6000 Programmable Logic Device Family Data Sheet SAMPLE/PRELOADAllows a snapshot of the signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. EXTESTAllows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test result at the input pins. BYPASSPlaces the 1-bit bypass register between the and pins, which allows the BST data to pass synchronously through the selected device to adjacent devices during normal device operation.

FLEX 6000 Programmable Logic Device Family Data Sheet EPF6010A522 EPF6016621 EPF6016A522 EPF6024A666 TDO TCK tJPZX tJPCO tJPH t JPXZ tJCP tJPSU t JCL tJCH TDI TMS Signal to Be Captured Signal to Be Driven tJSZX tJSSU tJSH tJSCO tJSXZ

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FLEX 6000 Programmable Logic Device Family Data Sheet tJCP clock period 100ns tJCH clock high time 50ns tJCL clock low time 50ns tJPSU JTAG port setup time 20ns tJPH JTAG port hold time 45ns tJPCO JTAG port clock-to-output25ns tJPZX JTAG port high impedance to valid output25ns tJPXZ JTAG port valid output to high impedance25ns tJSSU Capture register setup time20ns tJSH Capture register hold time45ns tJSCO Update register clock-to-output35ns tJSZX Update register high impedance to valid output 35ns tJSXZ Update register valid output to high impedance 35ns VCC To Test System C1 (includes JIG capacitance) Device input rise and fall times < 3 ns 464 (703 Device Output (8.06 k [521 [481 250

FLEX 6000 Programmable Logic Device Family Data Sheet VCC Supply voltageWith respect to ground (2) –2.07.0V VI DC input voltage –2.07.0V IOUT DC output current, per pin –2525mA TSTG Storage temperatureNo bias –65150 ° C TAMB Ambient temperatureUnder bias –65135 ° C TJ Junction temperaturePQFP, TQFP, and BGA packages135 ° C VCCINT Supply voltage for internal logic and input buffers VCCIO Supply voltage for output buffers, 5.0-V operation Supply voltage for output buffers, 3.3-V operation VI Input voltage –0.5V CCINT + 0.5V VO Output voltage0V CCIO V TJ Operating temperatureFor commercial use085 ° C For industrial use –40100 ° C tR Input rise time 40ns tF Input fall time 40ns

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FLEX 6000 Programmable Logic Device Family Data Sheet VIH High-level input voltage2.0V CCINT + 0.5V VIL Low-level input voltage –0.50.8V VOH 5.0-V high-level TTL output voltage IOH = –8 mA DC, VCCIO = 4.75 V (7) 2.4V 3.3-V high-level TTL output voltage IOH = –8 mA DC, VCCIO = 3.00 V (7) 2.4V 3.3-V high-level CMOS output voltage IOH = –0.1 mA DC, VCCIO = 3.00 V (7) VCCIO –0.2V VOL 5.0-V low-level TTL output voltage IOL = 8 mA DC, VCCIO = 4.75 V (8) 0.45V 3.3-V low-level TTL output voltage IOL = 8 mA DC, VCCIO = 3.00 V (8) 0.45V 3.3-V low-level CMOS output voltage IOL = 0.1 mA DC, VCCIO = 3.00 V (8) 0.2V II Input pin leakage currentV I = VCC or ground (8) –1010 µA IOZ Tri-stated I/O pin leakage currentV O = VCC or ground (8) –4040 µA ICC0 VCC supply current (standby)V I = ground, no load0.55mA CIN Input capacitance for I/O pinV IN = 0 V, f = 1.0MHz 8pF CINCLK Input capacitance for dedicated inputV IN = 0 V, f = 1.0MHz 12pF COUT Output capacitanceV OUT = 0 V, f = 1.0MHz 8pF

FLEX 6000 Programmable Logic Device Family Data Sheet VCC Supply voltageWith respect to ground (2) –0.54.6V VI DC input voltage –2.05.75V IOUT DC output current, per pin –2525mA TSTG Storage temperatureNo bias –65150 ° C TAMB Ambient temperatureUnder bias –65135 ° C TJ Junction temperaturePQFP, PLCC, and BGA packages135 ° C VCCINT Supply voltage for internal logic and input buffers VCCIO Supply voltage for output buffers, 3.3-V operation Supply voltage for output buffers, 2.5-V operation VI Input voltage –0.55.75V VO Output voltage0V CCIO V TJ Operating temperatureFor commercial use085 ° C For industrial use –40100 ° C tR Input rise time 40ns tF Input fall time 40ns

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FLEX 6000 Programmable Logic Device Family Data Sheet VIH High-level input voltage1.75.75V VIL Low-level input voltage –0.50.8V VOH 3.3-V high-level TTL output voltage IOH = –8 mA DC, VCCIO = 3.00 V (7) 2.4V 3.3-V high-level CMOS output voltage IOH = –0.1 mA DC, VCCIO = 3.00 V (7) VCCIO –0.2V 2.5-V high-level output voltageI OH = –100 µA DC, VCCIO = 2.30 V (7) 2.1V IOH = –1 mA DC, VCCIO = 2.30 V (7) 2.0V IOH = –2 mA DC, VCCIO = 2.30 V (7) 1.7V VOL 3.3-V low-level TTL output voltage IOL = 8 mA DC, VCCIO = 3.00 V (8) 0.45V 3.3-V low-level CMOS output voltage IOL = 0.1 mA DC, VCCIO = 3.00 V (8) 0.2V 2.5-V low-level output voltageI OL = 100 µA DC, VCCIO = 2.30 V (8) 0.2V IOL = 1 mA DC, VCCIO = 2.30 V (8) 0.4V IOL = 2 mA DC, VCCIO = 2.30 V (8) 0.7V II Input pin leakage currentV I = 5.3 V to ground (8) –1010 µA IOZ Tri-stated I/O pin leakage currentV O = 5.3 V to ground (8) –1010 µA ICC0 VCC supply current (standby)V I = ground, no load0.55mA CIN Input capacitance for I/O pinV IN = 0 V, f = 1.0MHz 8pF CINCLK Input capacitance for dedicated inputV IN = 0 V, f = 1.0MHz 12pF COUT Output capacitanceV OUT = 0 V, f = 1.0MHz 8pF

FLEX 6000 Programmable Logic Device Family Data Sheet VO Output Voltage (V) 12345

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VCCINT = 3.3 V VCCIO = 3.3 V Room Temperature EPF6010A EPF6016A 100 EPF6010A EPF6016A VO Output Voltage (V) 12345 VCCINT = 3.3 V VCCIO = 2.5 V Room Temperature 100 VO Output Voltage (V) 12345 IOL IOH VCCINT = 3.3 V VCCIO = 3.3 V Room Temperature EPF6024A 100 VO Output Voltage (V) 12345 IOL IOH VCCINT = 3.3 V VCCIO = 2.5 V Room Temperature EPF6024A 100 VO Output Voltage (V) 12345 150 120 IOL IOH VCCINT = 5.0 V VCCIO = 5.0 V Room Temperature VO Output Voltage (V) 12345 150 120 IOL IOH 3.3 VCCINT = 5.0 V VCCIO = 3.3 V Room Temperature EPF6016EPF6016 Typical IO Output Current (mA) Typical IO Output Current (mA) Typical IO Output Current (mA) Typical IO Output Current (mA) Typical IO Output Current (mA) Typical IO Output Current (mA)

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FLEX 6000 Programmable Logic Device Family Data Sheet

FLEX 6000 Programmable Logic Device Family Data Sheet Carry-out to Next LE in Same LAB Carry-out to Next LE in Next LAB Cascade-out to Next LE in Same LAB Cascade-out to Next LE in Next LAB Carry-In from Previous LE Cascade-In from Previous LE IOE LE I/O Pin

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FLEX 6000 Programmable Logic Device Family Data Sheet tREG_TO_REG LUT delay for LE register feedback in carry chain tCASC_TO_REG Cascade-in to register delay tCARRY_TO_REG Carry-in to register delay tDATA_TO_REG LE input to register delay tCASC_TO_OUT Cascade-in to LE output delay tCARRY_TO_OUT Carry-in to LE output delay tDATA_TO_OUT LE input to LE output delay tREG_TO_OUT Register output to LE output delay tSU LE register setup time before clock; LE register recovery time after asynchronous clear tH LE register hold time after clock tCO LE register clock-to-output delay tCLR LE register clear delay tC LE register control signal delay tLD_CLR Synchronous load or clear delay in counter mode tCARRY_TO_CARRY Carry-in to carry-out delay tREG_TO_CARRY Register output to carry-out delay tDATA_TO_CARRY LE input to carry-out delay tCARRY_TO_CASC Carry-in to cascade-out delay tCASC_TO_CASC Cascade-in to cascade-out delay tREG_TO_CASC Register-out to cascade-out delay tDATA_TO_CASC LE input to cascade-out delay tCH LE register clock high time tCL LE register clock low time

FLEX 6000 Programmable Logic Device Family Data Sheet tOD1 Output buffer and pad delay, slow slew rate = off, V CCIO = VCCINT C1=35 pF (2) tOD2 Output buffer and pad delay, slow slew rate = off, V CCIO = low voltageC1=35 pF (3) tOD3 Output buffer and pad delay, slow slew rate = onC1=35 pF (4) tXZ Output buffer disable delayC1=5 pF tZX1 Output buffer enable delay, slow slew rate = off, V CCIO = VCCINT C1=35 pF (2) tZX2 Output buffer enable delay, slow slew rate = off, V CCIO = low voltageC1=35 pF (3) tZX3 IOE output buffer enable delay, slow slew rate = onC1=35 pF (4) tIOE Output enable control delay tIN Input pad and buffer to FastTrack Interconnect delay tIN_DELAY Input pad and buffer to FastTrack Interconnect delay with additional delay turned on tLOCAL LAB local interconnect delay tROW Row interconnect routing delay (5) tCOL Column interconnect routing delay (5) tDIN_D Dedicated input to LE data delay (5) tDIN_C Dedicated input to LE control delay tLEGLOBAL LE output to LE control via internally-generated global signal delay (5) tLABCARRY Routing delay for the carry-out of an LE driving the carry-in signal of a different LE in a different LAB tLABCASC Routing delay for the cascade-out signal of an LE driving the cascade-in signal of a different LE in a different LAB t1 Register-to-register test pattern (6) tDRR Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local interconnects (7)

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FLEX 6000 Programmable Logic Device Family Data Sheet tINSU Setup time with global clock at LE register (8) tINH Hold time with global clock at LE register (8) tOUTCO Clock-to-output delay with global clock with LE register using FastFLEX I/O pin (8) REG_TO_REG 1.21.31.7ns CASC_TO_REG 0.91.01.2ns CARRY_TO_REG 0.91.01.2ns DATA_TO_REG 1.11.21.5ns CASC_TO_OUT 1.31.41.8ns CARRY_TO_OUT 1.61.82.3ns DATA_TO_OUT 1.72.02.5ns REG_TO_OUT 0.40.40.5ns SU 0.91.01.3ns H 1.41.72.1ns

FLEX 6000 Programmable Logic Device Family Data Sheet CO 0.30.40.4ns CLR 0.40.40.5ns C 1.82.12.6ns LD_CLR 1.82.12.6ns CARRY_TO_CARRY 0.10.10.1ns REG_TO_CARRY 1.61.92.3ns DATA_TO_CARRY 2.12.53.0ns CARRY_TO_CASC 1.01.11.4ns CASC_TO_CASC 0.50.60.7ns REG_TO_CASC 1.41.72.1ns DATA_TO_CASC 1.11.21.5ns CH 2.53.03.5ns CL 2.53.03.5ns OD1 1.92.22.7ns OD2 4.14.85.8ns OD3 5.86.88.3ns XZ 1.41.72.1ns XZ1 1.41.72.1ns XZ2 3.64.35.2ns XZ3 5.36.37.7ns IOE 0.50.60.7ns IN 3.64.15.1ns IN_DELAY 4.85.46.7ns

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FLEX 6000 Programmable Logic Device Family Data Sheet LOCAL 0.70.71.0ns ROW 2.93.23.2ns COL 1.21.31.4ns DIN_D 5.45.76.4ns DIN_C 4.35.06.1ns LEGLOBAL 2.63.03.7ns LABCARRY 0.70.80.9ns LABCASC 1.31.41.8ns t1 EPF6010A37.643.653.7ns EPF6016A38.044.054.1ns

FLEX 6000 Programmable Logic Device Family Data Sheet tREG_TO_REG 2.22.8ns tCASC_TO_REG 0.91.2ns tCARRY_TO_REG 1.62.1ns tDATA_TO_REG 2.43.0ns tCASC_TO_OUT 1.31.7ns tCARRY_TO_OUT 2.43.0ns tDATA_TO_OUT 2.73.4ns tREG_TO_OUT 0.30.5ns tSU 1.11.6ns tH 1.82.3ns tCO 0.30.4ns tCLR 0.50.6ns tC 1.21.5ns tLD_CLR 1.21.5ns tCARRY_TO_CARRY 0.20.4ns tREG_TO_CARRY 0.81.1ns tDATA_TO_CARRY 1.72.2ns tCARRY_TO_CASC 1.72.2ns tCASC_TO_CASC 0.91.2ns tREG_TO_CASC 1.62.0ns tDATA_TO_CASC 1.72.1ns tCH 4.04.0ns tCL 4.04.0ns tOD1 2.32.8ns tOD2 4.65.1ns

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FLEX 6000 Programmable Logic Device Family Data Sheet tOD3 4.75.2ns tXZ 2.32.8ns tZX1 2.32.8ns tZX2 4.65.1ns tZX3 4.75.2ns tIOE 0.50.6ns tIN 3.34.0ns tIN_DELAY 4.65.6ns tLOCAL 0.81.0ns tROW 2.93.3ns tCOL 2.32.5ns tDIN_D 4.96.0ns tDIN_C 4.86.0ns tLEGLOBAL 3.13.9ns tLABCARRY 0.40.5ns tLABCASC 0.81.0ns t1 53.065.0ns tDRR 16.020.0ns

FLEX 6000 Programmable Logic Device Family Data Sheet tINSU 3.24.1ns tINH 0.00.0ns tOUTCO 2.07.92.09.9ns tREG_TO_REG 1.21.31.6ns tCASC_TO_REG 0.70.81.0ns tCARRY_TO_REG 1.61.82.2ns tDATA_TO_REG 1.31.41.7ns tCASC_TO_OUT 1.21.31.6ns tCARRY_TO_OUT 2.02.22.6ns tDATA_TO_OUT 1.82.12.6ns tREG_TO_OUT 0.30.30.4ns tSU 0.91.01.2ns tH 1.31.41.7ns tCO 0.20.30.3ns tCLR 0.30.30.4ns tC 1.92.12.5ns tLD_CLR 1.92.12.5ns tCARRY_TO_CARRY 0.20.20.3ns tREG_TO_CARRY 1.41.61.9ns tDATA_TO_CARRY 1.31.41.7ns tCARRY_TO_CASC 1.11.21.4ns tCASC_TO_CASC 0.70.81.0ns tREG_TO_CASC 1.41.61.9ns tDATA_TO_CASC 1.01.11.3ns tCH 2.53.03.5ns tCL 2.53.03.5ns

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FLEX 6000 Programmable Logic Device Family Data Sheet tOD1 1.92.12.5ns tOD2 4.04.45.3ns tOD3 7.07.89.3ns tXZ 4.34.85.8ns tXZ1 4.34.85.8ns tXZ2 6.47.18.6ns tXZ3 9.410.512.6ns tIOE 0.50.60.7ns tIN 3.33.74.4ns tIN_DELAY 5.35.97.0ns tLOCAL 0.80.81.1ns tROW 3.03.13.3ns tCOL 3.03.23.4ns tDIN_D 5.45.66.2ns tDIN_C 4.65.16.1ns tLEGLOBAL 3.13.54.3ns tLABCARRY 0.60.70.8ns tLABCASC 0.30.30.4ns 45.050.060.0ns

FLEX 6000 Programmable Logic Device Family Data Sheet EPF6010A14 EPF601688 EPF6016A14 EPF6024A14

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FLEX 6000 Programmable Logic Device Family Data Sheet

FLEX 6000 Programmable Logic Device Family Data Sheet Frequency (MHz) Frequency (MHz) 50 100 200 250 150 100 Frequency (MHz) 50 100 400 300 200 100 0 50 100 200 150 100 Frequency (MHz) 30 60 800 1000 600 400 200 ICC Supply Current (mA) ICC Supply Current (mA) ICC Supply Current (mA) ICC Supply Current (mA)

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FLEX 6000 Programmable Logic Device Family Data Sheet Configuration deviceEPC1 or EPC1441 configuration device Passive serial (PS)BitBlaster TM, ByteBlasterMVTM, or MasterBlasterTM download cables, or serial data source Passive serial asynchronous (PSA) BitBlaster, ByteBlasterMV, or MasterBlaster download cables, or serial data source

FLEX 6000 Programmable Logic Device Family Data Sheet

FLEX 6000 Programmable Logic Device Family Data Sheet

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