FLEX10K

EPF10K40RC240-4N ALTERA | Alldatasheet

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Table 1. FLEX 10K Device Features

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FLEX 10K Embedded Programmable Logic Device Family Data Sheet Note to tables: (1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum system gates. ...and More

Features

– Devices are fabricated on advanced processes and operate with a 3.3-V or 5.0-V supply voltage (see Table 3 – In-circuit reconfigurability (ICR) via external configuration device, intelligent controller, or JTAG port – ClockLock TM and ClockBoostTM options for reduced clock delay/skew and clock multiplication – Built-in low-skew clock distribution trees –1 0 0 % functional testing of all devices; test vectors or scan chains are not required Table 2. FLEX 10K Device Features Table 3. Supply Voltages for FLEX 10K & FLEX 10KA Devices

FLEX 10K Embedded Programmable Logic Device Family Data Sheet ■ Flexible interconnect –F a s t T r a c k® Interconnect continuous routing structure for fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) – Tri-state emulation that implements internal tri-state buses – Up to six global clock signals and four global clear signals ■ Powerful I/O pins – Individual tri-state output enable control for each pin – Open-drain option on each I/O pin – Programmable output slew-rate control to reduce switching noise – FLEX 10KA devices support hot-socketing ■ Peripheral register for fast setup and clock-to-output delay ■ Flexible package options – Available in a variety of packages with 84 to 600 pins (see Tables 4 and 5) – Pin-compatibility with other FLEX 10K devices in the same package – FineLine BGA TM packages maximize board space efficiency ■ Software design support and automatic place-and-route provided by Altera development systems for Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800 workstations ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), DesignWare components, Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic

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Table 4. FLEX 10K Package Options & I/O Pin Count Note (1) Table 5. FLEX 10K Package Options & I/O Pin Count (Continued) Note (1)

FLEX 10K Embedded Programmable Logic Device Family Data Sheet Notes to tables: (1) FLEX 10K and FLEX 10KA device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), pin-grid array (PGA), and FineLine BGATM packages. (2) This option is supported with a 256-pin FineLine BGA package. By using SameFrame pin migration, all FineLine BGA packages are pin compatible. For example, a board can be designed to support both 256-pin and 484-pin FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration is set. General

Description

Altera’s FLEX 10K devices are the industry’s first embedded PLDs. Based on reconfigurable CMOS SRAM elements, the Flexible Logic Element MatriX (FLEX) architecture incorporates all features necessary to implement common gate array megafunctions. With up to 250,000 gates, the FLEX 10K family provides the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device. FLEX 10K devices are reconfigurable, which allows 100% testing prior to shipment. As a result, the designer is not required to generate test vectors for fault coverage purposes. Additionally, the designer does not need to manage inventories of different ASIC designs; FLEX 10K devices can be configured on the board for the specific functionality required. Table 6 shows FLEX 10K performance for some common designs. All performance values were obtained with Synopsys DesignWare or LPM functions. No special design technique was required to implement the applications; the designer simply inferred or instantiated a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file. Notes: (1) The speed grade of this application is limited because of clock high and low specifications. (2) This application uses combinatorial inputs and outputs. (3) This application uses registered inputs and outputs. Table 6. FLEX 10K & FLEX 10KA Performance

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FLEX 10K Embedded Programmable Logic Device Family Data Sheet The FLEX 10K architecture is similar to that of embedded gate arrays, the fastest-growing segment of the gate array market. As with standard gate arrays, embedded gate arrays implement general logic in a conventional “sea-of-gates” architecture. In addition, embedded gate arrays have dedicated die areas for implementing large, specialized functions. By embedding functions in silicon, embedded gate arrays provide reduced die area and increased speed compared to standard gate arrays. However, embedded megafunctions typically cannot be customized, limiting the designer’s options. In contrast, FLEX 10K devices are programmable, providing the designer with full control over embedded megafunctions and general logic while facilitating iterative design changes during debugging. Each FLEX 10K device contains an embedded array and a logic array. The embedded array is used to implement a variety of memory functions or complex logic functions, such as digital signal processing (DSP), microcontroller, wide-data-path manipulation, and data-transformation functions. The logic array performs the same function as the sea-of-gates in the gate array: it is used to implement general logic, such as counters, adders, state machines, and multiplexers. The combination of embedded and logic arrays provides the high performance and high density of embedded gate arrays, enabling designers to implement an entire system on a single device. FLEX 10K devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers the EPC1, EPC2, EPC16, and EPC1441 configuration devices, which configure FLEX 10K devices via a serial data stream. Configuration data can also be downloaded from system RAM or from Altera’s BitBlaster TM serial download cable or ByteBlasterMVTM parallel port download cable. After a FLEX 10K device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Because reconfiguration requires less than 320 ms, real-time changes can be made during system operation. FLEX 10K devices contain an optimized interface that permits microprocessors to configure FLEX 10K devices serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat a FLEX 10K device as memory and configure the device by writing to a virtual memory location, making it very easy for the designer to reconfigure the device.

FLEX 10K Embedded Programmable Logic Device Family Data Sheet f For more information, see the following documents: ■ Configuration Devices for APEX & FLEX Devices Data Sheet ■ BitBlaster Serial Download Cable Data Sheet ■ ByteBlasterMV Parallel Port Download Cable Data Sheet ■ Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000 Devices) FLEX 10K devices are supported by Altera development systems; single, integrated packages that offer schematic, text (including AHDL), and waveform design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, and device configuration. The Altera software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX workstation-based EDA tools. The Altera software works easily with common gate array EDA tools for synthesis and simulation. For example, the Altera software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the Altera software contains EDA libraries that use device- specific features such as carry chains which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the Altera development systems include DesignWare functions that are optimized for the FLEX 10K architecture. The Altera development systems run on Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations. f See the MAX+PLUS II Programmable Logic Development System & Software Data Sheet for more information. Functional Each FLEX 10K device contains an embedded array to implement memory and specialized logic functions, and a logic array to implement general logic. The embedded array consists of a series of EABs. When implementing memory functions, each EAB provides 2,048 bits, which can be used to create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions. When implementing logic, each EAB can contribute 100 to 600 gates towards complex logic functions, such as multipliers, microcontrollers, state machines, and DSP functions. EABs can be used independently, or multiple EABs can be combined to implement larger functions.

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FLEX 10K Embedded Programmable Logic Device Family Data Sheet The logic array consists of logic array blocks (LABs). Each LAB contains eight LEs and a local interconnect. An LE consists of a 4-input look-up table (LUT), a programmable flipflop, and dedicated signal paths for carry and cascade functions. The eight LEs can be used to create medium-sized blocks of logic—8-bit counters, address decoders, or state machines—or combined across LABs to create larger logic blocks. Each LAB represents about 96 usable gates of logic. Signal interconnections within FLEX 10K devices and to and from device pins are provided by the FastTrack Interconnect, a series of fast, continuous row and column channels that run the entire length and width of the device. Each I/O pin is fed by an I/O element (IOE) located at the end of each row and column of the FastTrack Interconnect. Each IOE contains a bidirectional I/O buffer and a flipflop that can be used as either an output or input register to feed input, output, or bidirectional signals. When used with a dedicated clock pin, these registers provide exceptional performance. As inputs, they provide setup times as low as 1.6 ns and hold times of 0 ns; as outputs, these registers provide clock-to-output times as low as 5.3 ns. IOEs provide a variety of features, such as JTAG BST support, slew-rate control, tri-state buffers, and open-drain outputs. Figure 1 shows a block diagram of the FLEX 10K architecture. Each group of LEs is combined into an LAB; LABs are arranged into rows and columns. Each row also contains a single EAB. The LABs and EABs are interconnected by the FastTrack Interconnect. IOEs are located at the end of each row and column of the FastTrack Interconnect.

Figure 1. FLEX 10K Device Block Diagram signal that clears many registers in the device.

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with linked LEs or field-programmable gate array (FPGA) RAM blocks. can automatically take advantage of the EAB. of RAM that eliminate these timing and routing concerns. specifications of the global clock. Figure 2. EAB Memory Configurations

Figure 3. Examples of Combining EABs EABs to meet a designer’s RAM specifications. EABs provide flexible options for driving and controlling clock signals.

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Figure 4. FLEX 10K Embedded Array Block

22 EAB local interconnect channels; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, and EPF10K250A devices

efficient routing with optimum device utilization and high performance. Figure 5. FLEX 10K LAB and EPF10K250A devices have 26.

30 LAB local interconnect channels; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, and EPF10K250A devices

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addition, the global control signals can be generated from LE outputs. Figure 6. FLEX 10K Logic Element

FLEX 10K Embedded Programmable Logic Device Family Data Sheet The programmable flipflop in the LE can be configured for D, T, JK, or SR operation. The clock, clear, and preset control signals on the flipflop can be driven by global signals, general-purpose I/O pins, or any internal logic. For combinatorial functions, the flipflop is bypassed and the output of the LUT drives the output of the LE. The LE has two outputs that drive the interconnect; one drives the local interconnect and the other drives either the row or column FastTrack Interconnect. The two outputs can be controlled independently. For example, the LUT can drive one output while the register drives the other output. This feature, called register packing, can improve LE utilization because the register and the LUT can be used for unrelated functions. The FLEX 10K architecture provides two types of dedicated high-speed data paths that connect adjacent LEs without using local interconnect paths: carry chains and cascade chains. The carry chain supports high- speed counters and adders; the cascade chain implements wide-input functions with minimum delay. Carry and cascade chains connect all LEs in an LAB and all LABs in the same row. Intensive use of carry and cascade chains can reduce routing flexibility. Therefore, the use of these chains should be limited to speed-critical portions of a design. Carry Chain The carry chain provides a very fast (as low as 0.2 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit drives forward into the higher-order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature allows the FLEX 10K architecture to implement high-speed counters, adders, and comparators of arbitrary width efficiently. Carry chain logic can be created automatically by the Compiler during design processing, or manually by the designer during design entry. Parameterized functions such as LPM and DesignWare functions automatically take advantage of carry chains. Carry chains longer than eight LEs are automatically implemented by linking LABs together. For enhanced fitting, a long carry chain skips alternate LABs in a row. A carry chain longer than one LAB skips either from even-numbered LAB to even-numbered LAB, or from odd- numbered LAB to odd-numbered LAB. For example, the last LE of the first LAB in a row carries to the first LE of the third LAB in the row. The carry chain does not cross the EAB at the middle of the row. For instance, in the EPF10K50 device, the carry chain stops at the eighteenth LAB and a new one begins at the nineteenth LAB.

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be used as a general-purpose signal. Figure 7. Carry Chain Operation (n-bit Full Adder)

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FLEX 10K Embedded Programmable Logic Device Family Data Sheet LE Operating Modes The FLEX 10K LE can operate in the following four modes: ■ Normal mode ■ Arithmetic mode ■ Up/down counter mode ■ Clearable counter mode Each of these modes uses LE resources differently. In each mode, seven available inputs to the LE—the four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous LE—are directed to different destinations to implement the desired logic function. Three inputs to the LE provide clock, clear, and preset control for the register. The Altera software, in conjunction with parameterized functions such as LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers. If required, the designer can also create special-purpose functions which use a specific LE operating mode for optimal performance. The architecture provides a synchronous clock enable to the register in all four modes. The Altera software can set DATA1 to enable the register synchronously, providing easy implementation of fully synchronous designs. Figure 9 shows the LE operating modes.

Figure 9. FLEX 10K LE Operating Modes (1) Packed registers cannot be used with the cascade chain.

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FLEX 10K Embedded Programmable Logic Device Family Data Sheet Normal Mode The normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in are inputs to a four-input LUT. The Compiler automatically selects the carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal. Either the register or the LUT can be used to drive both the local interconnect and the FastTrack Interconnect at the same time. The LUT and the register in the LE can be used independently; this feature is known as register packing. To support register packing, the LE has two outputs; one drives the local interconnect and the other drives the FastTrack Interconnect. The DATA4 signal can drive the register directly, allowing the LUT to compute a function that is independent of the registered signal; a three-input function can be computed in the LUT, and a fourth independent signal can be registered. Alternatively, a four-input function can be generated, and one of the inputs to this function can be used to drive the register. The register in a packed LE can still use the clock enable, clear, and preset signals in the LE. In a packed LE, the register can drive the FastTrack Interconnect while the LUT drives the local interconnect, or vice versa. Arithmetic Mode The arithmetic mode offers 2 three-input LUTs that are ideal for implementing adders, accumulators, and comparators. One LUT computes a three-input function, and the other generates a carry output. As shown in Figure 9 on page 19, the first LUT uses the carry-in signal and two data inputs from the LAB local interconnect to generate a combinatorial or registered output. For example, in an adder, this output is the sum of three signals: a, b, and carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports simultaneous use of the cascade chain.

FLEX 10K Embedded Programmable Logic Device Family Data Sheet Up/Down Counter Mode The up/down counter mode offers counter enable, clock enable, synchronous up/down control, and data loading options. These control signals are generated by the data inputs from the LAB local interconnect, the carry-in signal, and output feedback from the programmable register. The Up/down counter mode uses 2 three-input LUTs: one generates the counter data, and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading. Data can also be loaded asynchronously with the clear and preset register control signals, without using the LUT resources. Clearable Counter Mode The clearable counter mode is similar to the up/down counter mode, but supports a synchronous clear instead of the up/down control. The clear function is substituted for the cascade-in signal in the up/down counter mode. Clearable counter mode uses 2 three-input LUTs: one generates the counter data, and the other generates the fast carry bit. Synchronous loading is provided by a 2-to-1 multiplexer. The output of this multiplexer is ANDed with a synchronous clear signal. Internal Tri-State Emulation Internal tri-state emulation provides internal tri-stating without the limitations of a physical tri-state bus. In a physical tri-state bus, the tri-state buffers’ output enable (OE) signals select which signal drives the bus. However, if multiple OE signals are active, contending signals can be driven onto the bus. Conversely, if no OE signals are active, the bus will float. Internal tri-state emulation resolves contending tri-state buffers to a low value and floating buses to a high value, thereby eliminating these problems. The Altera software automatically implements tri-state bus functionality with a multiplexer. Clear & Preset Logic Control Logic for the programmable register’s clear and preset functions is controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The clear and preset control structure of the LE asynchronously loads signals into a register. Either LABCTRL1 or LABCTRL2 can control the asynchronous clear. Alternatively, the register can be set up so that LABCTRL1 implements an asynchronous load. The data to be loaded is driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the register.

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FLEX 10K Embedded Programmable Logic Device Family Data Sheet During compilation, the Compiler automatically selects the best control signal implementation. Because the clear and preset functions are active- low, the Compiler automatically assigns a logic high to an unused clear or preset. The clear and preset logic is implemented in one of the following six modes chosen during design entry: ■ Asynchronous clear ■ Asynchronous preset ■ Asynchronous clear and preset ■ Asynchronous load with clear ■ Asynchronous load with preset ■ Asynchronous load without clear or preset In addition to the six clear and preset modes, FLEX 10K devices provide a chip-wide reset pin that can reset all registers in the device. Use of this feature is set during design entry. In any of the clear and preset modes, the chip-wide reset overrides all other signals. Registers with asynchronous presets may be preset when the chip-wide reset is asserted. Inversion can be used to implement the asynchronous preset. Figure 10 shows examples of how to enter a section of a design for the desired functionality.

Figure 10. LE Clear & Preset Modes mode, the preset signal is tied to VCC to deactivate it.

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FLEX 10K Embedded Programmable Logic Device Family Data Sheet Asynchronous Preset An asynchronous preset is implemented as either an asynchronous load, or with an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRL1 asynchronously loads a one into the register. Alternatively, the Altera software can provide preset control by using the clear and inverting the input and output of the register. Inversion control is available for the inputs to both LEs and IOEs. Therefore, if a register is preset by only one of the two LABCTRL signals, the DATA3 input is not needed and can be used for one of the LE operating modes. Asynchronous Preset & Clear When implementing asynchronous clear and preset, LABCTRL1 controls the preset and LABCTRL2 controls the clear. DATA3 is tied to V CC, therefore, asserting LABCTRL1 asynchronously loads a one into the register, effectively presetting the register. Asserting LABCTRL2 clears the register. Asynchronous Load with Clear When implementing an asynchronous load in conjunction with the clear, LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear. LABCTRL2 implements the clear by controlling the register clear; LABCTRL2 does not have to feed the preset circuits. Asynchronous Load with Preset When implementing an asynchronous load in conjunction with preset, the Altera software provides preset control by using the clear and inverting the input and output of the register. Asserting LABCTRL2 presets the register, while asserting LABCTRL1 loads the register. The Altera software inverts the signal that drives DATA3 to account for the inversion of the register’s output. Asynchronous Load without Preset or Clear When implementing an asynchronous load without preset or clear, LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear.

FLEX 10K Embedded Programmable Logic Device Family Data Sheet FastTrack Interconnect In the FLEX 10K architecture, connections between LEs and device I/O pins are provided by the FastTrack Interconnect, which is a series of continuous horizontal and vertical routing channels that traverse the device. This global routing structure provides predictable performance, even in complex designs. In contrast, the segmented routing in FPGAs requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. The FastTrack Interconnect consists of row and column interconnect channels that span the entire device. Each row of LABs is served by a dedicated row interconnect. The row interconnect can drive I/O pins and feed other LABs in the device. The column interconnect routes signals between rows and can drive I/O pins. A row channel can be driven by an LE or by one of three column channels. These four signals feed dual 4-to-1 multiplexers that connect to two specific row channels. These multiplexers, which are connected to each LE, allow column channels to drive row channels even when all eight LEs in an LAB drive the row interconnect. Each column of LABs is served by a dedicated column interconnect. The column interconnect can then drive I/O pins or another row’s interconnect to route the signals to other LABs in the device. A signal from the column interconnect, which can be either the output of an LE or an input from an I/O pin, must be routed to the row interconnect before it can enter an LAB or EAB. Each row channel that is driven by an IOE or EAB can drive one specific column channel. Access to row and column channels can be switched between LEs in adjacent pairs of LABs. For example, an LE in one LAB can drive the row and column channels normally driven by a particular LE in the adjacent LAB in the same row, and vice versa. This routing flexibility enables routing resources to be used more efficiently. See Figure 11.

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Figure 11. LAB Connections to Row & Column Interconnect

saving the other half of the channel for the other half of the row. are available as control signals for all LABs and IOEs in the device. because they can feed the local interconnect of each LAB in the device. additional delay into the control signal network. Table 7. FLEX 10K FastTrack Interconnect Resources

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LAB B3 is in row B, column 3. Figure 12. Interconnect Resources

FLEX 10K Embedded Programmable Logic Device Family Data Sheet I/O Element An I/O element (IOE) contains a bidirectional I/O buffer and a register that can be used either as an input register for external data that requires a fast setup time, or as an output register for data that requires fast clock- to-output performance. In some cases, using an LE register for an input register will result in a faster setup time than using an IOE register. IOEs can be used as input, output, or bidirectional pins. For bidirectional registered I/O implementation, the output register should be in the IOE and, the data input and output enable register should be LE registers placed adjacent to the bidirectional pin. The Compiler uses the programmable inversion option to invert signals from the row and column interconnect automatically where appropriate. Figure 13 shows the bidirectional I/O registers.

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Figure 13. Bidirectional I/O Registers

2 Dedicated

4 Dedicated

FLEX 10K Embedded Programmable Logic Device Family Data Sheet Each IOE selects the clock, clear, clock enable, and output enable controls from a network of I/O control signals called the peripheral control bus. The peripheral control bus uses high-speed drivers to minimize signal skew across devices; it provides up to 12 peripheral control signals that can be allocated as follows: ■ Up to eight output enable signals ■ Up to six clock enable signals ■ Up to two clock signals ■ Up to two clear signals If more than six clock enable or eight output enable signals are required, each IOE on the device can be controlled by clock enable and output enable signals driven by specific LEs. In addition to the two clock signals available on the peripheral control bus, each IOE can use one of two dedicated clock pins. Each peripheral control signal can be driven by any of the dedicated input pins or the first LE of each LAB in a particular row. In addition, an LE in a different row can drive a column interconnect, which causes a row interconnect to drive the peripheral control signal. The chip-wide reset signal will reset all IOE registers, overriding any other control signals. Tables 8 and 9 list the sources for each peripheral control signal, and the rows that can drive global signals. These tables also show how the output enable, clock enable, clock, and clear signals share 12 peripheral control signals.

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Table 8. EPF10K10, EPF10K20, EPF10K30, EPF10K40 & EPF10K50 Peripheral Bus Sources Table 9. EPF10K70, EPF10K100, EPF10K130V & EPF10K250A Peripheral Bus Sources

known logic state (such as ground) and not be allowed to float. each row channel. See Figure 14. Figure 14. FLEX 10K Row-to-IOE Connections The values for m and n are provided in Table 10.

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Table 10 lists the FLEX 10K row-to-IOE interconnect resources. IOE can access is different for each IOE. See Figure 15. Table 10. FLEX 10K Row-to-IOE Interconnect Resources

Figure 15. FLEX 10K Column-to-IOE Connections Table 11 lists the FLEX 10K column-to-IOE interconnect resources. The values for m and n are provided in Table 11. Table 11. FLEX 10K Column-to-IOE Interconnect Resources

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count packages form a subset of the higher-ball-count packages. take advantage of this migration (see Figure 16). Figure 16. SameFrame Pin-Out Example

FLEX 10K Embedded Programmable Logic Device Family Data Sheet ClockLock & ClockBoost To support high-speed designs, selected FLEX 10K devices offer optional ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL) that is used to increase design speed and reduce resource usage. The ClockLock circuitry uses a synchronizing PLL that reduces the clock delay and skew within a device. This reduction minimizes clock-to-output and setup times while maintaining zero hold times. The ClockBoost circuitry, which provides a clock multiplier, allows the designer to enhance device area efficiency by sharing resources within the device. The ClockBoost feature allows the designer to distribute a low-speed clock and multiply that clock on-device. Combined, the ClockLock and ClockBoost features provide significant improvements in system performance and bandwidth. The ClockLock and ClockBoost features in FLEX 10K devices are enabled through the Altera software. External devices are not required to use these features. The output of the ClockLock and ClockBoost circuits is not available at any of the device pins. The ClockLock and ClockBoost circuitry locks onto the rising edge of the incoming clock. The circuit output can only drive the clock inputs of registers; the generated clock cannot be gated or inverted. The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and ClockBoost circuitry. When the dedicated clock pin is driving the ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device. In designs that require both a multiplied and non-multiplied clock, the clock trace on the board can be connected to GCLK1. With the Altera software, GCLK1 can feed both the ClockLock and ClockBoost circuitry in the FLEX 10K device. However, when both circuits are used, the other clock pin (GCLK0) cannot be used. Figure 17 shows a block diagram of how to enable both the ClockLock and ClockBoost circuits in the Altera software. The example shown is a schematic, but a similar approach applies for designs created in AHDL, VHDL, and Verilog HDL. When the ClockLock and ClockBoost circuits are used simultaneously, the input frequency parameter must be the same for both circuits. In Figure 17, the input frequency must meet the requirements specified when the ClockBoost multiplication factor is two.

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Figure 17. Enabling ClockLock & ClockBoost in the Same Design can also be used to limit overshoot in other systems. devices to bridge between a 3.3-V PCI bus and a 5.0-V device.

FLEX 10K Embedded Programmable Logic Device Family Data Sheet Slew-Rate Control The output buffer in each IOE has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A slower slew rate reduces system noise and adds a maximum delay of approximately 2.9 ns. The fast slew rate should be used for speed-critical outputs in systems that are adequately protected against noise. Designers can specify the slew rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a device-wide basis. The slow slew rate setting affects only the falling edge of the output. Open-Drain Output Option FLEX 10K devices provide an optional open-drain (electrically equivalent to an open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired-OR plane. Additionally, the Altera software can convert tri-state buffers with grounded data inputs to open- drain pins automatically. Open-drain output pins on FLEX 10K devices (with a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a V IH of 3.5 V. When the open-drain pin is active, it will drive low. When the pin is inactive, the trace will be pulled up to 5.0 V by the resistor. The open-drain pin will only drive low or tri-state; it will never drive high. The rise time is dependent on the value of the pull-up resistor and load impedance. The I OL current specification should be considered when selecting a pull-up resistor. Output pins on 5.0-V FLEX 10K devices with VCCIO = 3.3 V or 5.0 V (with a pull-up resistor to the 5.0-V supply) can also drive 5.0-V CMOS input pins. In this case, the pull-up transistor will turn off when the pin voltage exceeds 3.3 V. Therefore, the pin does not have to be open-drain. MultiVolt I/O Interface The FLEX 10K device architecture supports the MultiVolt I/O interface feature, which allows FLEX 10K devices to interface with systems of differing supply voltages. These devices have one set of VCC pins for internal operation and input buffers (VCCINT) and another set for I/O output drivers (VCCIO).

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(1) 240-pin QFP packages do not support the MultiVolt I/O features, so they do not have separate V CCIO pins. FLEX 10KA devices operate as specified by the user. performed before or after configuration, but not during configuration. FLEX 10K devices support the JTAG instructions shown in Table 13. Table 12. Supply Voltages & MultiVolt I/O Support Levels

Table 13. FLEX 10K JTAG Instructions normal device operation, and permits an initial data pattern output at the device pins. test pattern at the output pins and capturing test results at the input pins. TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. to be serially shifted out of TDO. (.jam) or Jam Byte-Code File (.jbc) via an embedded processor. Table 14. FLEX 10K Boundary-Scan Register Length

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(1) The most significant bit (MSB) is on the left. (2) The least significant bit (LSB) for all JTAG IDCODEs is 1. FLEX 10K devices include weak pull-ups on JTAG pins. Table 15. 32-Bit FLEX 10K Device IDCODE Note (1)

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configurable SRAM bit and all logic functionality ensures 100% yield. to configure devices during all stages of the production flow. Figure 19. FLEX 10K AC Test Conditions capacitance for 5.0-V FLEX 10K devices. not be performed under AC conditions. outputs discharge the load capacitances. parentheses are for 5.0-V devices or outputs. Table 17. FLEX 10K 5.0-V Device Absolute Maximum Ratings Note (1)

Table 18. FLEX 10K 5.0-V Device Recommended Operating Conditions

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Table 19. FLEX 10K 5.0-V Device DC Operating Conditions Notes (5), (6) Table 20. 5.0-V Device Capacitance of EPF10K10, EPF10K20 & EPF10K30 Devices Note (10) Table 21. 5.0-V Device Capacitance of EPF10K40, EPF10K50, EPF10K70 & EPF10K100 Devices Note (10)

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capacitance for EPF10K50V and EPF10K130V devices. Table 22. EPF10K50V & EPF10K130V Device Absolute Maximum Ratings Note (1) Table 23. EPF10K50V & EPF10K130V Device Recommended Operating Conditions

(1) See the Operating Requirements for Altera Devices Data Sheet . for input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. CC rise time is 100 ms. V CC must rise monotonically. (5) EPF10K50V and EPF10K130V device inputs may be driven before V CCINT and VCCIO are powered. (6) Typical values are for T A = 25° C and VCC = 3.3 V. (8) The I OH parameter refers to high-level TTL or CMOS output current. (10) This value is specified for normal device operation. The value may vary during power-up. devices, and -2 speed grade EPF10K130V devices. (12) Capacitance is sample-tested only. Table 24. EPF10K50V & EPF10K130V Device DC Operating Conditions Notes (6), (7) Table 25. EPF10K50V & EPF10K130V Device Capacitance (12)

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Figure 21. Output Drive Characteristics of EPF10K50V & EPF10K130V Devices capacitance for 3.3-V FLEX 10K devices. Table 26. FLEX 10KA 3.3-V Device Absolute Maximum Ratings Note (1)

Table 27. FLEX 10KA 3.3-V Device Recommended Operating Conditions

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Table 28. FLEX 10KA 3.3-V Device DC Operating Conditions Notes (6), (7)

(1) See the Operating Requirements for Altera Devices Data Sheet . for input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. CC rise time is 100 ms, and V CC must rise monotonically. (5) FLEX 10KA device inputs may be driven before V CCINT and VCCIO are powered. (6) Typical values are for T A = 25° C and VCC = 3.3 V. (7) These values are specified under the Recommended Operating Conditions shown in Table 27 on page 51. (8) The I OH parameter refers to high-level TTL, PCI, or CMOS output current. (10) This value is specified for normal device operation. The value may vary during power-up. industrial-temperature devices. (12) Capacitance is sample-tested only. Table 29. 3.3-V Device Capacitance of EPF10K10A & EPF10K30A Devices Note (12) Table 30. 3.3-V Device Capacitance of EPF10K100A Devices Note (12) Table 31. 3.3-V Device Capacitance of EPF10K250A Devices Note (12)

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drive a 5.0-V PCI bus with eight or fewer loads. Figure 22. Output Drive Characteristics for EPF10K10A, EPF10K30A & EPF10K100A Devices EPF10K250A device with 3.3-V and 2.5-V VCCIO.

Figure 23. Output Drive Characteristics for EPF10K250A Device LEs between the source and destination LEs.

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device-wide performance analysis. to and from the various elements of the FLEX 10K device. Figure 24. FLEX 10K Device Timing Model

and functions within the LE, IOE, and EAB timing models. Figure 25. FLEX 10K Device LE Timing Model

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Figure 26. FLEX 10K Device IOE Timing Model Figure 27. FLEX 10K Device EAB Timing Model Figures 28 shows the timing model for bidirectional I/O pin timing.

Figure 28. Synchronous Bidirectional Pin External Timing Model Table 32. LE Timing Microparameters (Part 1 of 2) Note (1)

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Table 33. IOE Timing Microparameters Note (1) Table 32. LE Timing Microparameters (Part 2 of 2) Note (1)

Table 34. EAB Timing Microparameters Note (1)

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Table 35. EAB Timing Macroparameters Notes (1), (6)

Table 36. Interconnect Timing Microparameters Note (1) Table 37. External Timing Parameters Notes (8), (10) Table 38. External Bidirectional Timing Parameters Note (10)

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(2) Operating conditions: V CCIO = 5.0 V ± 5% for commercial use in FLEX 10K devices. VCCIO = 5.0 V ± 10% for industrial use in FLEX 10K devices. VCCIO = 3.3 V ± 10% for commercial or industrial use in FLEX 10KA devices. (3) Operating conditions: V CCIO = 3.3 V ± 10% for commercial or industrial use in FLEX 10K devices. VCCIO = 2.5 V ± 0.2 V for commercial or industrial use in FLEX 10KA devices. (4) Operating conditions: V CCIO = 2.5 V, 3.3 V, or 5.0 V. (5) Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered. these parameters are calculated by summing selected microparameters. analysis are required to determine actual worst-case performance. subset of signal paths is tested to approximate typical device applications. (9) Contact Altera Applications for test circuit specifications and test conditions. (10) These timing parameters are sample-tested only. waveforms, respectively, for the EAB macroparameters in Table 34. Figure 29. EAB Asynchronous Timing Waveforms

Figure 30. EAB Synchronous Timing Waveforms

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Table 39. EPF10K10 & EPF10K20 Device LE Timing Microparameters Note (1)

Table 40. EPF10K10 & EPF10K20 Device IOE Timing Microparameters Note (1)

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Table 41. EPF10K10 & EPF10K20 Device EAB Internal Microparameters Note (1)

Table 42. EPF10K10 & EPF10K20 Device EAB Internal Timing Macroparameters Note (1)

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Table 43. EPF10K10 Device Interconnect Timing Microparameters Note (1) Table 44. EPF10K20 Device Interconnect Timing Microparameters Note (1)

(1) All timing parameters are described in Tables 32 through 38 in this data sheet. (2) Using an LE to register the signal may provide a lower setup time. (3) This parameter is specified by characterization. Table 45. EPF10K10 & EPF10K20 Device External Timing Parameters Note (1) Table 46. EPF10K10 Device External Bidirectional Timing Parameters Note (1) Table 47. EPF10K20 Device External Bidirectional Timing Parameters Note (1)

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internal and external timing parameters. Table 48. EPF10K30, EPF10K40 & EPF10K50 Device LE Timing Microparameters Note (1)

Table 49. EPF10K30, EPF10K40 & EPF10K50 Device IOE Timing Microparameters Note (1)

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Table 50. EPF10K30, EPF10K40 & EPF10K50 Device EAB Internal Microparameters Note (1)

Table 51. EPF10K30, EPF10K40 & EPF10K50 Device EAB Internal Timing Macroparameters Note (1)

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Table 52. EPF10K30 Device Interconnect Timing Microparameters Note (1) Table 53. EPF10K40 Device Interconnect Timing Microparameters Note (1)

Table 54. EPF10K50 Device Interconnect Timing Microparameters Note (1) Table 55. EPF10K30, EPF10K40 & EPF10K50 Device External Timing Parameters Note (1) Table 56. EPF10K30, EPF10K40 & EPF10K50 Device External Bidirectional Timing Parameters Note (1)

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(1) All timing parameters are described in Tables 32 through 38 in this data sheet. (2) Using an LE to register the signal may provide a lower setup time. (3) This parameter is specified by characterization. Table 57. EPF10K70 Device LE Timing Microparameters Note (1)

Table 58. EPF10K70 Device IOE Timing Microparameters Note (1)

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Table 59. EPF10K70 Device EAB Internal Microparameters Note (1)

Table 60. EPF10K70 Device EAB Internal Timing Macroparameters Note (1)

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Table 61. EPF10K70 Device Interconnect Timing Microparameters Note (1) Table 62. EPF10K70 Device External Timing Parameters Note (1) Table 63. EPF10K70 Device External Bidirectional Timing Parameters Note (1)

(1) All timing parameters are described in Tables 32 through 38 in this data sheet. (2) Using an LE to register the signal may provide a lower setup time. (3) This parameter is specified by characterization. Table 64. EPF10K100 Device LE Timing Microparameters Note (1)

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Table 65. EPF10K100 Device IOE Timing Microparameters Note (1)

Table 66. EPF10K100 Device EAB Internal Microparameters Note (1)

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Table 67. EPF10K100 Device EAB Internal Timing Macroparameters Note (1)

Table 68. EPF10K100 Device Interconnect Timing Microparameters Note (1)

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(1) All timing parameters are described in Tables 32 through 38 in this data sheet. (2) Using an LE to register the signal may provide a lower setup time. (3) This parameter is specified by characterization. (4) This parameter is measured without the use of the ClockLock or ClockBoost circuits. (5) This parameter is measured with the use of the ClockLock or ClockBoost circuits. Table 69. EPF10K100 Device External Timing Parameters Note (1) Table 70. EPF10K100 Device External Bidirectional Timing Parameters Note (1)

Table 71. EPF10K50V Device LE Timing Microparameters Note (1)

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Table 72. EPF10K50V Device IOE Timing Microparameters Note (1)

Table 73. EPF10K50V Device EAB Internal Microparameters Note (1)

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Table 74. EPF10K50V Device EAB Internal Timing Macroparameters Note (1)

Table 75. EPF10K50V Device Interconnect Timing Microparameters Note (1) Table 76. EPF10K50V Device External Timing Parameters Note (1) Table 77. EPF10K50V Device External Bidirectional Timing Parameters Note (1)

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(1) All timing parameters are described in Tables 32 through 38 in this data sheet. (2) Using an LE to register the signal may provide a lower setup time. (3) This parameter is specified by characterization. Table 78. EPF10K130V Device LE Timing Microparameters Note (1)

Table 79. EPF10K130V Device IOE Timing Microparameters Note (1)

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Table 80. EPF10K130V Device EAB Internal Microparameters Note (1)

Table 81. EPF10K130V Device EAB Internal Timing Macroparameters Note (1)

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Table 82. EPF10K130V Device Interconnect Timing Microparameters Note (1) Table 83. EPF10K130V Device External Timing Parameters Note (1) Table 84. EPF10K130V Device External Bidirectional Timing Parameters Note (1)

(1) All timing parameters are described in Tables 32 through 38 in this data sheet. (2) Using an LE to register the signal may provide a lower setup time. (3) This parameter is specified by characterization. Table 85. EPF10K10A Device LE Timing Microparameters Note (1) Table 86. EPF10K10A Device IOE Timing Microparameters Note (1) (Part 1 of 2)

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Table 86. EPF10K10A Device IOE Timing Microparameters Note (1) (Part 2 of 2)

Table 87. EPF10K10A Device EAB Internal Microparameters Note (1)

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Table 88. EPF10K10A Device EAB Internal Timing Macroparameters Note (1)

Table 89. EPF10K10A Device Interconnect Timing Microparameters Note (1) Table 90. EPF10K10A External Reference Timing Parameters Note (1) Table 91. EPF10K10A Device External Bidirectional Timing Parameters Note (1)

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(1) All timing parameters are described in Tables 32 through 38 in this data sheet. (2) Using an LE to register the signal may provide a lower setup time. (3) This parameter is specified by characterization. Table 92. EPF10K30A Device LE Timing Microparameters Note (1) Table 93. EPF10K30A Device IOE Timing Microparameters Note (1) (Part 1 of 2)

Table 93. EPF10K30A Device IOE Timing Microparameters Note (1) (Part 2 of 2)

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Table 94. EPF10K30A Device EAB Internal Microparameters Note (1)

Table 95. EPF10K30A Device EAB Internal Timing Macroparameters Note (1)

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Table 96. EPF10K30A Device Interconnect Timing Microparameters Note (1) Table 97. EPF10K30A External Reference Timing Parameters Note (1) Table 98. EPF10K30A Device External Bidirectional Timing Parameters Note (1)

(1) All timing parameters are described in Tables 32 through 38 in this data sheet. (2) Using an LE to register the signal may provide a lower setup time. (3) This parameter is specified by characterization. Table 99. EPF10K100A Device LE Timing Microparameters Note (1)

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Table 100. EPF10K100A Device IOE Timing Microparameters Note (1)

Table 101. EPF10K100A Device EAB Internal Microparameters Note (1)

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Table 102. EPF10K100A Device EAB Internal Timing Macroparameters Note (1)

Table 103. EPF10K100A Device Interconnect Timing Microparameters Note (1) Table 104. EPF10K100A Device External Timing Parameters Note (1) Table 105. EPF10K100A Device External Bidirectional Timing Parameters Note (1)

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(1) All timing parameters are described in Tables 32 through 38 in this data sheet. (2) Using an LE to register the signal may provide a lower setup time. (3) This parameter is specified by characterization. Table 106. EPF10K250A Device LE Timing Microparameters Note (1)

Table 107. EPF10K250A Device IOE Timing Microparameters Note (1)

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Table 108. EPF10K250A Device EAB Internal Microparameters Note (1)

Table 109. EPF10K250A Device EAB Internal Timing Macroparameters Note (1)

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Table 110. EPF10K250A Device Interconnect Timing Microparameters Note (1) Table 111. EPF10K250A Device External Reference Timing Parameters Note (1) Table 112. EPF10K250A Device External Bidirectional Timing Parameters Note (1)

(1) All timing parameters are described in Tables 32 through 37 in this data sheet. (2) Using an LE to register the signal may provide a lower setup time. (3) This parameter is specified by characterization. Figure 31. Specifications for the Incoming & Generated Clocks nominal output clock period. Table 113 summarizes the ClockLock and ClockBoost parameters. Table 113. ClockLock & ClockBoost Parameters (Part 1 of 2)

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during device operation. Simulation does not reflect this parameter. LOCK value is less than the time required for configuration. (3) The tJITTER specification is measured under long-term observation. guidelines given in Application Note 74 (Evaluating Power for Altera Devices).

1 Compared to the rest of the device, the embedded array

Table 113. ClockLock & ClockBoost Parameters (Part 2 of 2)

and the environmental operating conditions. an actual design in a segmented interconnect FPGA. frequency of FLEX 10K devices. Table 114. FLEX 10K K Constant Values Table 115. FLEX 10KA K Constant Values

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Figure 32. ICCACTIVE vs. Operating Frequency (Part 1 of 3)

Figure 32. ICCACTIVE vs. Operating Frequency (Part 2 of 3)

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Figure 32. ICCACTIVE vs. Operating Frequency (Part 3 of 3) require configuration data to be loaded every time the circuit powers up. for configuration. The FLEX 10K POR time does not exceed 50 µs.

FLEX 10K Embedded Programmable Logic Device Family Data Sheet SRAM configuration elements allow FLEX 10K devices to be reconfigured in-circuit by loading new configuration data into the device. Real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different configuration data, reinitializing the device, and resuming user-mode operation. The entire reconfiguration process may be completed in less than 320 ms using an EPF10K250A device with a DCLK frequency of 10 MHz. This process can be used to reconfigure an entire system dynamically. In-field upgrades can be performed by distributing new configuration files.

1 Refer to the configuration device data sheet to obtain the POR

delay when using a configuration device method. Programming Files Despite being function- and pin-compatible, FLEX 10KA and FLEX 10KE devices are not programming- or configuration-file compatible with FLEX 10K devices. A design should be recompiled before it is transferred from a FLEX 10K device to an equivalent FLEX 10KA or FLEX 10KE device. This recompilation should be performed to create a new programming or configuration file and to check design timing on the faster FLEX 10KA or FLEX 10KE device. The programming or configuration files for EPF10K50 devices can program or configure an EPF10K50V device. However, Altera recommends recompiling a design for the EPF10K50V device when transferring it from the EPF10K50 device. Configuration Schemes The configuration data for a FLEX 10K device can be loaded with one of five configuration schemes (see Table 116), chosen on the basis of the target application. An EPC1, EPC2, EPC16, or EPC1441 configuration device, intelligent controller, or the JTAG port can be used to control the configuration of a FLEX 10K device, allowing automatic configuration on system power-up.

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configuration enable output (nCEO) pins on each device. Library for pin-out information. Programmable Logic Device Family Data Sheet: updated Figure 13. Embedded Programmable Logic Device Family Data Sheet. Table 116. Data Sources for Configuration

FLEX 10K Embedded Programmable Logic Device Family Data Sheet Altera Corporation 127 Notes:

Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services

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San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com FLEX 10K Embedded Programmable Logic Device Family Data Sheet

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