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Technical content
Features
- Infineon thin-film-SOI-technology
- Fully operational to +600 V
- Integrated Ultra-fast, low RDS(ON) Bootstrap Diode
- Floating channel designed for bootstrap operation
- Output source/sink current capability +1.8 A/-2.5 A
- Tolerant to negative transient voltage up to -100 V (Pulse width is up 300 ns) given by SOI-technology
- Interlock, Enable, Fault, and over current protection
- 10 ns typ., 60 ns max. propagation delay matching
- dV/dt immune ±50 V
- Undervoltage lockout for both channels
- 3.3 V, 5 V and 15 V input logic compatible
- RoHS compliant Product summary VOFFSET = 620 V max. IO+/- (typ.) = 1.8 A/2.5 A VOUT = 10 V - 17.5 V Delay Matching = 60 ns max. tf/tr (typ. CL=4.9 nF) = 37 ns/48 ns Package DSO-14 Potential applications
- Motor drives, general purpose inverters
- Refrigeration compressors, home appliance
- Half-bridge and full-bridge converters in offline AC-DC power supplies for telecom and lighting Product validation Qualified for industrial applications according to the relevant tests of JEDEC47/20/22.
Description
The 2EDL family contains devices, which control power devices like MOS-transistors or IGBTs with a maximum blocking voltage of +600 V in half bridge configurations. Based on the used SOI-technology there is an excellent ruggedness on transient voltages. No parasitic thyristor structures are present in the device. Hence, no parasitic latch up may occur at all temperature and voltage conditions. The two independent driver outputs are controlled at the low-side using two different CMOS resp. LSTTL compatible signals, down up to 3.3 V logic. The device includes an under-voltage detection unit with hysteresis characteristic which are optimised either for IGBT or MOSFET. Those parts, which are designed for IGBT have asymmetric undervoltage lockout levels, which support strongly the integrated ultra-fast bootstrap diode. Additionally, the offline gate clamping function provides an inherent protection of the transistors for parasitic turn-on by floating gate conditions, when the IC is not supplied via VDD. LIN HO VS LO PGND To Load GND HIN + DC-Bus GND - DC-Bus 2EDL23x06PJ EN- /FLT To Opamp / Comparator VDD VB EN /CTRAP PWM_H PWM_L GND +5 V Figure 1 Typical application diagram Refer to lead assignments for correct pin configuration. This diagram show electrical connections only. Please refer to our application notes and design tips for proper circuit board layout.
2EDL23 family Datasheet 2 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
Ordering information
Sales Name Special function output current Target transistor typ. Level Shift UVLO thresholds Bootstrap diode Package Evaluation board 2EDL23I06PJ Deadtime, Interlock, Enable, Fault, Over Current Protection 2.3 A IGBT 12.5 V / 11.6 V Yes DSO-14 EVAL-2EDL23I06PJ 2EDL23N06PJ 2.3 A MOSFET 9.1 V / 8.3 V Yes DSO-14 EVAL-2EDL23N06PJ Table of contents
2EDL23 family Datasheet 3 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family
1 Block diagram
Figure 2 Functional block diagram
2 Lead definitions
Table 1 2EDL23 family lead definitions Pin no. Name Function
1 VDD Low-side and logic supply voltage
2 HIN Logic input for high-side gate driver output (HO), in phase. Schmitt trigger inputs with hysteresis and pull down 3 LIN Logic input for low-side gate driver output (LO), in phase. Schmitt trigger inputs with hysteresis and pull down
4 EN-/FLT Enable input and Fault indication output
5 GND Logic ground
6 PGND Low-side gate drive return
7 LO Low-side driver output
8,9,13,14 nc Not connected
10 VS High voltage floating supply return
11 HO High-side driver output
12 VB High-side gate drive floating supply
Figure 3 2EDL23 family lead assignments (top view)
2EDL23 family Datasheet 4 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family
3 Functional description
3.1 Low Side and High Side Control Pins (LIN, HIN)
3.1.1 Input voltage range
All input pins have the capability to process input voltages up to the supply voltage of the IC. The inputs are therefore internally clamped to VDD and GND by diodes. An internal pull-down resistor is high ohmic, so that it can keep the IC in a safe state in case of PCB crack.
3.1.2 Switching levels
The Schmitt trigger input threshold is such to guarantee LSTTL and CMOS compatibility down to 3.3 V controller outputs. The input Schmitt trigger and noise filter provide beneficial noise rejection to short input pulses according to Figure 4 and Figure 5. Please note, that the switching levels of the input structures remain constant even though they can accept amplitudes up to the IC supply level. Figure 4 Input pin structure
3.1.3 Input filter time
Figure 5 Input filter timing diagram Short pulses are suppressed by means of an input filter. The MOSFET version (2EDL23N06PJ) has an input filter time of tFILIN = 100 ns typ. for high side and 150 ns typ. for low side. The IGBT version (2EDL23I06PJ) has filter times of 190 ns typ.
3.2 VDD, GND and PGND (Low Side Supply)
VDD is the low side supply and it provides power to both the input logic and the low side output power stage. The input logic is referenced to GND ground as well as the under-voltage detection circuit. Output power stage is referenced to PGND ground. PGND ground is floating respect to GND ground with an absolute maximum range of operation of +/-5.7 V. A back-to-back zener structure protects grounds from noise spikes. The undervoltage lockout circuit enables the device to operate at power on when a typical supply voltage higher than VDDUV+ is present. Please see section 3.5 “Undervoltage lockout”” for further information.
2EDL23 family Datasheet 5 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family A filter time of typ. 1.5 µs1 helps to suppress noise from the UVLO circuit, so that negative going voltage spikes at the supply pins will avoid parasitic UVLO events.
3.3 VB and VS (High Side Supplies)
VB to VS is the high side supply voltage. The high side circuit can float with respect to GND following the external high side power device emitter/source voltage. Due to the low power consumption, the floating driver stage can be supplied by bootstrap topology connected to VDD. A filter time of typ. 1.3 µs helps to suppress noise from the UVLO circuit, so that negative going voltage spikes at the supply pins will avoid parasitic UVLO events. The under-voltage circuit enables the device to operate at power on when a typical supply voltage higher than VDDUV+ is present. Please see section 3.5 “Undervoltage lockout” for further information. Details on bootstrap supply section and transient immunity can be found in application note EiceDRIVER™ 2EDL family: Technical description.
3.4 LO and HO (Low and High Side Outputs)
Low side and high side power outputs are specifically designed for pulse operation such as gate drive for IGBT and MOSFET devices. Low side output is state triggered by the respective inputs, while high side output is edge triggered by the respective inputs. In particular, after an undervoltage condition of the VBS supply, a new turn- on signal (edge) is necessary to activate the high side output. In contrast, the low side outputs switch to the state of their respective inputs after an undervoltage condition of the VDD supply. The output current specification IO+ and IO- is defined in a way, which considers the power transistors miller voltage.This helps to design the gate drive better in terms of the application needs. Nevertheless, the devices are also characterised for the value of the pulse short circuit value IOpk+ and IOpk–.
3.5 Undervoltage lockout (UVLO)
Two different UVLO options are required for IGBT and MOSFET. The types 2EDL23I06PJ are designed to drive IGBT. There are higher levels of undervoltage lockout for the low side UVLO than for the high side. This supports an improved start up of the IC, when bootstrapping is used. The thresholds for the low side are typically VDDUV+ = 12.5 V (positive going) and VDDUV– = 11.6 V (negative going). The thresholds for the high side are typically VBSUV+ = 11.6 V (positive going) and VBSUV– = 10.7 V (negative going). The types 2EDL23N06PJ are designed to drive power MOSFET. A similar distinction for the high side and low side UVLO threshold as for IGBT is not realised here. The IC shuts down all the gate drivers power outputs, when (min. / max. = 8.3 V / 9.9 V)
3.6 Bootstrap diode (BSD)
An ultra fast bootstrap diode is monolithically integrated for establishing the high side supply. The differential resistor of the diode helps to avoid extremely high inrush currents when charging the bootstrap capacitor initially.
1 Not subject of production test, verified by characterisation
2EDL23 family Datasheet 6 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family
3.7 Deadtime and interlock function
The IC provides a hardware fixed deadtime. The deadtime is different for the MOSFET type (2EDL23N06PJ) and for the IGBT type (2EDL23I06PJ). The deadtimes are particularly typ. 380 ns for IGBT and typ. 75 ns for MOSFET. An additional interlock function prevents the two outputs from being activated simultaneously.
3.8 EN-/FL T (fault indication and enable function)
The types 2EDL23x06PJ provide a pin, which can either be used to shut down the IC or to read out a failure status of the IC. The signal applied to pin EN controls directly the output stages. All outputs are set to LOW, if EN is at LOW logic level. An integrated pull down resistor shuts down the IC in case of a floating input. The internal structure of the pin is given in Figure 6. The switching levels of the Schmitt-Trigger are here VEN,TH+ = 2.1 V and VEN,TH- = 0.9 V. The typical propagation delay time is tEN = 550 ns. The input is clamped by diodes to VDD and GND. The input voltage range is the same as the input control pins with a max. of 20 V. The /FAULT function is an active low open-drain output indicating the status of the gate driver (see Figure 6). The pin is active (i.e. forces LOW voltage level) when one of the following conditions occur:
- Under-voltage condition of VDD supply: In this case the fault condition is released as soon as the supply voltage condition returns in the normal operation range (please refer to VDD pin description for more details). The fault signal is activate as long as UVLO is given during power up.
- Overcurrent detection (ITRIP): The fault condition is latched until the overcurrent trigger condition is finished and additional typ. 230 µs are elapsed. The interface to the microcontroller can be realised by using an open collector / drain configured output pin for enabling the driver IC and a GPIO pin for monitoring the /FAULT. The external pull-up resistor will pull-up the voltage to +5V, when the IC is set for operation. Figure 6 EN-/FLT pin structures and interface to microcontroller (µC)
3.9 Power ground / over current protection
A power ground (PGND) connects directly the emitter or source of the low side transistor with the gate drive IC. No other components, such as shunts, etc., are between this connection and the emitter or source. This enables the routing of smallest gate circuit loops and therefore smallest gate inductances. A potential shunt resistor is between the power ground (PGND) connection and the gound connection (GND), which leads to a voltage drop between these two pins. The voltage drop between PGND and GND can be seen sensed by means of a comparator with a threshold of Vth,ITRIP = 0.46 V. If the voltage drop is larger than Vth,ITRIP , then the output of the comparator is triggered and the /FLT output is activated. Simultaneously, the IC shuts down both gate outputs for the period of the fault indication, which is 230 µs. Several influences, such as reverse recovery currents, parasitic inductances and other noise sources, make the need of a signal filter necessary. The filter has a time constant of typically 1.8 µs to ensure good noise quality.
2EDL23 family Datasheet 7 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family
3.10 Tolerant to negative transient voltage on VS pin (-VS)
A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage as the power switches transition on and off quickly while carrying a large current. A typical three phase inverter circuit is shown in Figure 7; here we define the power switches and diodes of the inverter. If the high-side switch (e.g., the IGBT Q1 in Figures 8 and 9) switches off, while the U phase current is flowing to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC bus voltage to the negative DC bus voltage. Figure 7 Three phase inverter Figure 8 Q1 conducting Figure 9 D2 conducting Also when the V phase current flows from the inductive load back to the inverter (see Figures 10 and 11), and Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, V S2, swings from the positive DC bus voltage to the negative DC bus voltage.
2EDL23 family Datasheet 8 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family Figure 10 D3 conducting Figure 11 Q4 conducting However, in a real inverter circuit the VS voltage swing does not stop at the level of the negative DC bus but instead swings below the level of the negative DC bus. This undershoot voltage is called “negative transient voltage”. The circuit shown in Figure 12 depicts one leg of the three phase inverter; Figures 13 and 14 show a simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch is on, V S1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in the low-side freewheeling diode due to the inductive load connected to V S1 (the load is not shown in these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS pin). Figure 12 Parasitic Elements Figure 13 VS positive Figure 14 VS negative In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in normal operation. Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications. An indication of the 2EDL23 family’s robustness can be seen in Figure 15, where the 2EDL23 Safe Operating Area is shown at VBS=15 V based on repetitive negative voltage spikes. A negative transient voltage falling in the grey area DC+ BUS DC- BUS VS1 LC1 LE1 LC2 LE2
2EDL23 family Datasheet 9 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family (outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage to the IC do not appear if negative VS transients fall inside the SOA. Figure 15 Negative transient voltage SOA on VS pin for 2EDL23 family @ VBS=15 V Even though the 2EDL23 family has been shown to be able to handle these large negative transient voltage conditions, it is highly recommended that the circuit designer always limit the negative transient voltage on VS pin as much as possible by careful PCB layout and component use.
2EDL23 family Datasheet 10 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family
4 Electrical parameters
4.1 Absolute maximum ratings
All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta=25°C). Table 2 Absolute maximum ratings Parameter Symbol Min. Max. Unit High side offset voltage1 VS VDD-VBS-6 600 V High side offset voltage (tp<300ns)1 VDD -VBS – 100 – High side offset voltage 1 VB VDD – 6 620 High side offset voltage (tp<300ns)1 VDD – 100 – High side floating supply voltage (VB vs. VS) (internally clamped) VBS -1 20 High side output voltage (VHO vs. VS) VHO -0.5 VB + 0.5 Low side supply voltage (internally clamped) VDD -1 20 Low side supply voltage (VDD vs. VPGND) VDDPGND -0.5 25 Gate driver ground VPGND -5.7 5.7 Low side output voltage (VLO vs. VPGND) VLO -0.5 VPGND + 0.5 Input voltage LIN,HIN, EN VIN -0.5 VDD + 0.5 FAULT output voltage VFLT -0.5 VDD + 0.5 Power dissipation (to package)2 PD – 0.9 W Thermal resistance (junction to ambient, see section 6) Rth(j-a) –
134 K/W
Junction temperature3 TJ – 150 °C Storage temperature TS - 40 150 offset voltage slew rate4 dVS/dt – 50 V/ns 1 In case VDD > VB there is an additional power dissipation in the internal bootstrap diode between pins VDD and VB in case of activated bootstrap diode. Insensitivity of bridge output to negative transient voltage up to –100V is not subject to production test – verified by design / characterization. 2 Consistent power dissipation of all outputs. All parameters are inside operating range. 3 Qualification stress tests cover a max. junction temperature of 150°C for 1000 h. 4 Not subject of production test, verified by characterisation.
2EDL23 family Datasheet 11 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family
4.2 Required operation conditions
All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta=25°C). Table 3 Required Operation Conditions Parameter Symbol Min. Max. Unit High side offset voltage1 VB 7 620 V Low side supply voltage (internally clamped, VDD vs. VPGND) VDDPGND 10 25
4.3 Operating Range
All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta=25°C) Table 4 Operating range Parameter Symbol Min. Max. Unit High side floating supply offset voltage VS VDD - VBS 500 V High side floating supply offset voltage (VB vs. VDD, statically) VBDD -1.0 500 High side floating supply voltage (VB vs. VS)1 IGBT-Types VBS 13 17.5 MOSFET-Types 10 17.5 High side output voltage (VHO vs. VS) VHO 0 VBS Low side output voltage (VLO vs. VPGND) VLO 0 VDD Low side supply voltage IGBT-Types VDD 13 17.5 MOSFET-Types 10 17.5 Low side ground voltage VPGND -2.5 2.5 Logic input voltages LIN,HIN, EN2 VIN 0 17.5 FAULT output voltage VFLT 0 VDD Pulse width for ON or OFF3 IGBT-Types tIN 0.8 – µs MOSFET-Types 0.3 – Ambient temperature Ta -40 105 °C Thermal coefficient (junction to top, see section 6) Ψth(j-top) – 4.8 3.3 K/W 1 Logic operational for VB (VB vs. VGND) > 7.0 V. 2 All input pins (HIN, LIN, EN) are internally clamped (see abs. maximum ratings). 3 The input pulse may not be transmitted properly in case of input pulse width at LIN and HIN below 0.8µs (IGBT types) or 0.3 µs (MOSFET) respectively.
2EDL23 family Datasheet 12 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family
4.4 Static logic function table
VDD VBS ENABLE FAULT PGND LO HO <VDDUV– X X 0 X 0 0 15V <VBSUV– 3.3 V High imp. < Vth,ITRIP LIN 0 15V 15V 3.3 V 0 > Vth,ITRIP 0 0 15V 15V 0 V High imp. X 0 0 15V 15V 3.3 V High imp. < Vth,ITRIP LIN HIN All voltages with reference to GND
4.5 Static parameters
VDD = VBS = 15V and VGND = VPGND unless otherwise specified. (Ta=25°C). Table 5 Static parameters Parameter Symbol Values Unit Test condition Min. Typ. Max. High level input voltage LIN, HIN, EN VIH 1.7 2.1 2.4 V Low level input voltage LIN, HIN, EN VIL 0.7 0.9 1.1 High level output voltage LO HO VOH – VDD -0.32 VB -0.32 VDD -0.7 VB -0.7 IO = - 100 mA Low level output voltage LO HO VOL – VPGND+0.18 VS+0.18 VPGND+0.4 VS +0.4 IO = 100 mA VDD supply undervoltage positive going threshold IGBT-types VDDUV+ 11.8 12.5 13.2 MOSFET types 8.3 9.1 9.9 VBS supply undervoltage positive going threshold IGBT-types VBSUV+ 10.9 11.6 12.4 MOSFET types 8.3 9.1 9.9 VDD supply undervoltage negative going threshold IGBT-types VDDUV– 10.9 11.6 12.4 MOSFET types 7.5 8.3 9 VBS supply undervoltage negative going threshold IGBT-types VBSUV– 10 10.7 11.7 MOSFET types 7.5 8.3 9 VDD and VBS supply UVLO hysteresis IGBT-types VDDUVH VBSUVH 0.5 0.9 – MOSFET types 0.5 0.9 – ITRIP comparator threshold Vth,ITRIP 0.4 0.46 0.53 VITRIP = VPGND - VGND ITRIP comparator hysteresis Vth,ITRIP hys 0.045 0.07 – High side leakage current betw. VS and GND ILVS+ – 1 12.5 µA VS = 600V High side leakage current betw. VS and GND ILVS+1 – 10 – TJ = 125 °C, VS = 600 V Quiescent current VBS supply (VB only) IQBS1 – 180 300 HO = low depending on current types
2EDL23 family Datasheet 13 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family Parameter Symbol Values Unit Test condition Min. Typ. Max. Quiescent current VBS supply (VB only) IQBS2 – 180 300 HO = high depending on current types Quiescent current VDD supply (VDD only) IQDD1 – 0.34 0.8 mA VLIN = float. Quiescent current VDD supply (VDD only) IQDD2 – 0.32 0.8 VLIN = 3.3 V, VHIN=0 Quiescent current VDD supply (VDD only) IQDD3 – 0.32 0.8 VLIN=0 , VHIN=3.3 V Input bias current ILIN+ 15 35 60 µA VLIN = 3.3 V Input bias current ILIN– – 0 – VLIN = 0 Input bias current IHIN+ 15 35 60 VHIN = 3.3 V Input bias current IHIN– – 0 – VHIN = 0 Input bias current (EN=high) IEN+ – 45 100 VENABLE = 3.3 V Mean output current for load capacity charging in range from 4.5 (30%) to 7.5V (50%) IO+ 1.3 1.8 – A CL = 61 nF Peak output current turn on (single pulse) IOpk+1 – 2.3 – RL = 0 Ω, tp <10 µs Mean output current for load capacity discharging in range from 7.5V (50%) to 4.5V (30%) IO– 1.65 2.5 – CL = 61 nF Peak output current turn off (single pulse) IOpk–1 – 2.8 – RL = 0 Ω, tp <10 µs Bootstrap diode forward voltage between VDD and VB VF,BSD – 0.9 1.2 V IF = 0.3 mA Bootstrap diode forward current between VDD and VB IF,BSD 45 82 120 mA VDD – VB = 4 V Bootstrap diode resistance RBSD 15 27 40 Ω VF1 = 4 V, VF2 = 5 V EN-/FLT low on resistance of the pull down transistor Ron,FLT – 35 70 VEN-/FLT = 0.5 V
2EDL23 family Datasheet 14 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family
4.6 Dynamic parameters
VDD = VBS = 15 V, VS = VGND = VPGND, CL = 180 pF unless otherwise specified. (Ta=25°C). Table 6 Dynamic parameters Parameter Symbol Values Unit Test condition Min. Typ. Max. Turn-on propagation delay IGBT types ton 280 420 610 ns VLIN/HIN = 0 or 3.3 V MOSFET types 210 310 460 Turn-off propagation delay IGBT types toff 260 400 590 MOSFET types 200 300 440 Turn-on rise time tr – 48 80 VLIN/HIN = 0 or 3.3 V CL = 4.9 nF Turn-off fall time tf – 37 60 Shutdown propagation delay ENABLE tEN – 550 850 VEN=0.5 V, VLO / VHO = 20% Input filter time at LIN/HIN for turn on and off IGBT types tFILIN 120 190 320 VLIN/HIN = 0 & 3.3 V MOSFET types HIN LIN 100 100 150 170 250 Input filter time EN tFILEN 200 400 – ITRIP filter time tFILITRIP 1.0 1.8 2.7 µs VPGND = 1 V, /FLT=0 Shut down propoagation delay PGND to any output tITRIP 1.1 2.2 3.0 VPGND = 1 V VLO / VHO = 3V Propagation delay ITRIP to FAULT tFLT 1.0 2.1 2.9 VPGND = 1 V, /FLT=0.5 V Fault-clear time tFLTCLR 70 230 – VPGND = 0.1 V, /FLT=2.1 V Dead time IGBT types DT 260 380 540 ns VLIN/HIN = 0 & 3.3 V MOSFET types 30 75 140 Dead time matching abs(DT_LH – DT_HL) for single IC IGBT types MDT – 10 80 ext. dead time 0ns MOSFET types 10 50 Matching delay ON, abs(ton_HS - ton_LS) MTON – 10 60 external dead time > 500 ns Matching delay OFF, abs(toff_HS-toff_LS) MTOFF – 10 60 external dead time >500 ns Output pulse width matching. PWin-PWout IGBT types PM – 20 80 PWin > 1 µs MOSFET types – 20 70
2EDL23 family Datasheet 15 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family
5 Timing diagrams
Figure 16 Timing of short pulse suppression Figure 17 Timing of of internal deadtime Figure 18 Timing of of internal deadtime
2EDL23 family Datasheet 16 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family 1.65V 1.65V 80% 20% 20% 80% PWOUT ton tofftr tf PWIN Figure 19 Input to output propagation delay times and switching times definition Figure 20 Operating areas (IGBT UVLO levels) Figure 21 Operating areas (MOSFET UVLO levels)
2EDL23 family Datasheet 17 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family Figure 23 Output pulse width timing and matching delay timing diagram for positive logic Figure 24 Deadtime and interlock
2EDL23 family Datasheet 18 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family
6 Package information
Max. reflow solder temperature: 265°C acc. JEDEC Max. wave solder temperature: 245°C acc. JEDEC Figure 25 Package outline PG-DSO-14 Figure 26 PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint The thermal coefficient is used to calculate the junction temperature, when the IC surface temperature is measured. The junction temperature is j = Ψth(j-top) ∙ +top Table 7 Data of reference layout Dimensions Material Metal (Copper) 76.2 × 114.3 × 1.5 mm³ FR4 (λtherm = 0.3 W/mK) 70µm (λtherm = 388 W/mK)
2EDL23 family Datasheet 19 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family
7 Qualification information1
Table 8 Qualification information Qualification level Industrial2 Note: This family of ICs has passed JEDEC’s Industrial qualification. Consumer qualification level is granted by extension of the higher Industrial level. Moisture sensitivity level DSO-8/-14 MSL33, 260°C (per IPC/JEDEC J-STD-020) ESD Charged device model Class C3 (> 1.0 kV) (per JESD22-C101) Human body model Class 2 (per JEDEC standard JESD22-A114) IC latch-up test Class II Level A (per JESD78) RoHS compliant Yes
8 Related products
600 V, 3 phase level shift thin-film SOI gate driver with integrated high speed, low RDS(ON) bootstrap
diodes with over-current protection (OCP), 240/420 mA source/sink current drive, Fault reporting, and Enable for MOSFET or IGBT switches. 2EDL05I06 / 2EDL05N06
600 V, Half-bridge thin-film SOI level shift gate driver with integrated high speed, low
RDS(ON) bootstrap diode, 0.36/0.7 A source/sink current driver, 8pins/14pins package, for MOSFET or IGBT switches. Power Switches IKD04N60R / RF 600 V TRENCHSTOP™ IGBT with integrated diode in PG-TO252-3 package IKD06N65ET6 650 V TRENCHSTOP™ IGBT with integrated diode in DPAK IPD65R950CFD 650 V CoolMOS™ CFD2 with integrated fast body diode in DPAK IPN50R950CE 500 V CoolMOS™ CE Superjunction MOSFET in PG-SOT223 package iMOTION™ Controllers IRMCK099 iMOTION™ Motor control IC for variable speed drives utilizing sensor-less Field Oriented Control (FOC) for Permanent Magnet Synchronous Motors (PMSM). IMC101T High performance Motor Control IC for variable speed drives based on field oriented control ( FOC) of permanent magnet synchronous motors (PMSM). 1 Qualification standards can be found at Infineon’s web site www.infineon.com 2 Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon sales representative for further information. 3 Higher MSL ratings may be available for the specific package types listed here. Please contact your Infineon sales representative for further information.
2EDL23 family Datasheet 20 of 21 Version 2.7 www.infineon.com/gdHalfBridge 2020-07-07 2EDL23 family
Revision history
Document version Date of release Description of changes 0.86 2014‐05‐15 Change term VCC in VDD 2.2 2016-06-01 Update maximum Ta from 95oC to 105oC in Table 3 2.3 2016‐08‐18 Updated disclaimer, trademarks. Upated parameter VHO 2.4 2017‐11‐28 Ψth(j-top) change to junction to top 2.5 2018-11-20 Updated ESD HBM information 2.6 2019-01-25 Updated Charpter 3.10 Tolerant to negative transient voltage on VS pin 2.7 2020-07-07 IC latch-up test per JESD78
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