DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 20
Technical content
Features
High Efficiency, Up to 91% Output Voltage Can Track VDDQ to within +/- 1.5% Source and Sink Capability up to 5A 125mm 2 Total Solution Size VDDQ Range (1.0V to 1.8V ) Monotonic Startup With Pre-bias Programmable Soft-Start Time Thermal Shutdown Protection Over Current and Short Circuit Protection Under-Voltage Protection RoHS Compliant, MSL level 3, 260°C reflow
Applications
Bus Termination: DDR2, DDR3, DDR4 & QDR™ Memory General Low V IN Applications VTTVDDQ COUT 1,2 CIN VOUT ENABLE AGND VREF VDDQ AVIN PGND PGND EV1340 CSS RA VCNTRL VFB RB RC RD SW FQADJ RFS CA SCHOTTKY CAVIN Figure 2: Typical VTT Application Schematic (VDDQ is the memory core voltage; VTT is memory termination voltage that tracks VDDQ)
06218 March 24, 2015 Rev C
2 www.altera.com/enpirion
Ordering Information
(°C) Package EV1340QI -40 to +85 54-pin QFN T&R EVB-EV1340QI QFN Evaluation Board Pin Assignments (Top View) Figure 3: Pinout Diagram (Top View). All pins must be soldered to PCB NOTE: There are specific keep-out areas underneath the EV1340 to consider when laying out a PCB for this device. Please see Figures 8, 10, and 11 for more layout details. Pin Description PIN NAME FUNCTION 1-9, 18, 36, 37, 53, NC NO CONNECT: These pins must be soldered to PCB but not electrically connected to each other or to any external signal, voltage, or ground. These pins may be connected internally. Failure to follow this guideline may result in device damage. 10 -17 VOUT Regulated converter output. Decouple with output filter capacitor to PGND. Refer to layout section for specific layout requirements 19, 20, SW These pins are internally connected to the common switching node of the internal MOSFETs. The anode of a Schottky diode needs to be connected to these pins. The cathode of the diode needs to be connected to VDDQ. 21-27 PGND Input and output power ground. Refer to la yout section for specific layout requirements. 28-31 VDDQ In DDR applications the input to this pin is the DDR core voltage. This is the input power supply to the power train which will be divided by two to create an output voltage that tracks with the input voltage applied to this pin. Decouple with input capacitor to PGND. Refer to layout section for specific layout requirements 32 AGND2 Ground for the gate driver supply. Connec t to the GND plane with a via next to the pin. 33, 39 AVIN1, AVIN2 Analog input voltage for the controller circuits. Each of these pins needs to be separately connected to the 3.3V input supply. Decouple with a capacitor to AGND. 34 VDDB Internal regulated voltage used for the internal control circuitry. This pin is reserved for Altera Enpirion testing, and should be left floating. 35 BGND This pin is reserved for Altera Enpirion testing, and should be left floating. 38 ENABLE This is the Device Enable pin. Floating this pin or a high level enables the device while a low level disables the device. 40 AGND This is the quiet ground for the controller. Connect to the GND plane with a via next to the pin.
41 POK
POK is a logical AND of VDDQOK and the internally generated POK of the EV1340. POK is an open drain logic output that requires an external pull-up resistor. This pin guarantees a logic low even when the EV1340 is completely un-powered. This pin can sink a maximum 4mA. The pull-up resistor may be connected to a power supply other than AVIN or VDDQ but the voltage should be <3.6Volts.
42 VFB
This is the feedback input pin which is always active. A resistor divider connects from the output to AGND. The mid-point of the resistor divider is connected to VFB. (A feed-forward capacitor and a resistor are required across the upper resistor.) The output voltage regulates so as to make the VFB node voltage = 600mV.
3 www.altera.com/enpirion PIN NAME FUNCTION 43 EAOUT Optional Error Amplifier Output. A llows for customization of the control loop.
44 VREF
External voltage reference input. A resistor divider connects from VDDQ to AGND. The mid- point of the resistor divider is connected to VREF. The resistor divider has to be chosen to make the voltage applied to this pin 600mV. An optional capacitor (for soft-start) may be connected from VREF to AGND. 45 VSENSE This pin senses the output voltage when the device is in pre-bias (or backfeed) mode. Connect to VOUT if EN_PB is high. Leave this pin floating if EN_PB is pulled to GND. 46 EN_PB Monotonic start-up with pre-bias is enabled by either pulling this pin high or letting it float. A logical low on this pin will disable pre-bias mode operation. 47 FQADJ Optimized frequency adjust pin. Connect a 3.57kΩ resistor from this pin to AGND to optimize on switching frequency.
48 VDDQOK
This is an active high input pin that indicates the externally supplied VDDQ input has reached its POK level. This pin should be tied to the VDDQ regulator POK output. It has an internal pull-up, and can be left floating if not needed. 49-52 NC(SW) No Connect – these pins are internally connected to the common switching node of the internal MOSFETs. They are not to be electrically connected to any external signal, ground, or voltage. Failure to follow these guidelines may result in damage to the device. Thermal Pad (PGND) Not a perimeter pin. Device thermal pad and PGND. Connected to the system ground plane. See Layout Recommendations section.
4 www.altera.com/enpirion Absolute Maximum Ratings CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER SYMBOL MIN MAX UNITS Input Supply Voltage: AVIN1, AVIN2 VIN -0.5 4.0 V Voltages on: ENABLE, EN_PB, VDDQOK -0.5 V IN V Voltages on: VFB, VREF, EAOUT, VDDQ, VOUT, VSENSE, FQADJ -0.5 2.7 V Voltage on: POK 3.6 V Voltage on: SW -0.5 VDDQ+0.5 V Storage Temperature Range TSTG -65 150 °C Maximum Operating Junction Temperature TJ-ABS Max 150 °C Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 °C ESD Rating (based on Human Body Model) 2000 V ESD Rating (based on CDM) 500 V Recommended Operating Conditions PARAMETER SYMBOL MIN MAX UNITS Input Voltage Range: AVIN1, AVIN2 2.9 3.7 V Input Voltage Range: VDDQ 1.0 1.8 V Input Voltage Range: VREF VEXTREF 0.4 0.72 V EN_PB, VDDQOK, EN 0 AVIN V Operating Ambient Temperature TA - 40 +85 °C Operating Junction Temperature TJ - 40 +125 °C Thermal Characteristics PARAMETER SYMBOL TYP UNITS Thermal Resistance: Junction to Ambient (0 LFM) (Note 1) JA 22 °C/W Thermal Resistance: Junction to Case (0 LFM) JC 2 °C/W Thermal Shutdown TSD 150 °C Thermal Shutdown Hysteresis TSDH 20 °C Note 1: Based on 2oz. external copper layers and proper thermal design in line with EIA/JEDEC JESD51-7 standard for high thermal conductivity boards.
5 www.altera.com/enpirion
Electrical Characteristics
NOTE: AVIN1, AVIN2 = 3.3V, over operating temperature range unless otherwise noted. Typical values are at TA = 25°C. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Power Supply Voltage VDDQ 1.0 1.8 V Controller Supply Voltage AVIN 2.9 3.3 3.7 V Under Voltage Lock-out – AVIN Rising V UVLOR Voltage above which UVLO is not asserted 2.3 V Under Voltage Lock-out – AVIN Falling V UVLOF Voltage below which UVLO is asserted 2.1 V Controller Input Current IAVIN AVIN = 3.3V 12 20 mA Shut-Down VDDQ Current I SD_VDDQ ENABLE = 0 150 µA Shut-Down AVIN Current I SD_AVIN ENABLE = 0 900 µA VREF Pin Current 20nA Output Voltage Accuracy – Initial V OUT VOUT =1/2 VDDQ (e.g. @ VDDQ = 1.500V), 0.1% VREF and VOUT resistor dividers) 0.740 0.750 0.760 V VFB Pin Voltage VVFB 2.9V ≤ AVIN ≤ 3.7V, VREF=600mV, 0A ≤ ILOAD ≤ 5A 591 600 609 mV VFB Pin Input Leakage Current IVFB VFB pin input leakage current 20 nA Continuous Output Sourcing Current I OUT_SRC 0 5 A Continuous Output Sinking Current I OUT_SNK 0 5 A Over Current Trip Level I OCPH Sourcing. VDDQ = 1.35V 11 A Switching Frequency F SW R FQADJ = 3.57kOhms 1.5 MHz Frequency Adjust Resistor R FQADJ 3.57 k Ω Pre-Bias Level VPB Allowable pre-bias as a fraction of programmed output voltage for monotonic start up 20 85 % Non-Monotonicity V PB_NM Allowable non-monotonicity under pre- bias start up 50 mV VOUT Range for POK = High Range of output voltage as a fraction of programmed value when P OK is asserted 92 110 % POK Deglitch Delay Falling edge deglitch delay after output crossing 90% level 64 Clock cycles VPOK Output Low Level With 4mA current sink into P OK pin 0.6 V VPOK Output High Level When pulled up to AVIN (3.3V) with RPOK = 100k; VPOK = AVIN * (196k/(RPOK + 196k); 2.2 V POK Current Sink Capability 2.9V ≤ AVIN ≤ 3.7V 4 mA
6 www.altera.com/enpirion PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Enable Threshold V ENABLE 2.9V ≤ AVIN ≤ 3.7 V; Min voltage to ensure the converter is enabled 1.3 V Disable Threshold V DISABLE Max voltage to ensure the converter is disabled 0.8 V Enable Pin Current IEN AVIN = 3.6V 50 A Binary Pin Logic Low Threshold V B-LOW VDDQOK, EN_PB 0.8 V Binary Pin Logic High Threshold V B-HIGH VDDQOK, EN_PB 1.8 V
7 www.altera.com/enpirion Typical Performance Curves 100 EFFICIENCY (%) OUTPUT CURRENT (A) EFFICIENCY vs. OUTPUT CURRENT VOUT = 0.6V CONDITIONS AVIN = 3.3V VDDQ = 2*VOUT CONDITIONS AVIN = 3.3V VDDQ = 1.8V CONDITIONS AVIN = 3.3V VDDQ = 1.5V CONDITIONS AVIN = 3.3V VDDQ = 1.8V 100 EFFICIENCY (%) OUTPUT CURRENT (A) EFFICIENCY vs. OUTPUT CURRENT VOUT = 0.675V CONDITIONS AVIN = 3.3V VDDQ = 2*VOUT CONDITIONS AVIN = 3.3V VDDQ = 1.8V 100 EFFICIENCY (%) OUTPUT CURRENT (A) EFFICIENCY vs. OUTPUT CURRENT VOUT = 0.75V CONDITIONS AVIN = 3.3V VDDQ = 2*VOUT 100 EFFICIENCY (%) OUTPUT CURRENT (A) EFFICIENCY vs. OUTPUT CURRENT VOUT = 1.5V CONDITIONS AVIN = 3.3V VDDQ = 1.8V 100 EFFICIENCY (%) OUTPUT CURRENT (A) EFFICIENCY vs. OUTPUT CURRENT VOUT = 1.2V CONDITIONS AVIN = 3.3V VDDQ = 1.5V CONDITIONS AVIN = 3.3V VDDQ = 1.8V 0.56 0.57 0.58 0.59 0.6 0.61 0.62 0.63 0.64 OUTPUT VOLTAGE (V) OUTPUT CURRENT (A) VOUT vs. IOUT VOUT = 0.6V CONDITIONS VDDQ = 2*VOUT
8 www.altera.com/enpirion Typical Performance Curves (Continued) 0.63 0.645 0.66 0.675 0.69 0.705 0.72 OUTPUT VOLTAGE (V) OUTPUT CURRENT (A) VOUT vs. IOUT VOUT = 0.675V CONDITIONS VDDQ = 2*VOUT CONDITIONS VDDQ = 2*VOUT 0.705 0.72 0.735 0.75 0.765 0.78 0.795 OUTPUT VOLTAGE (V) OUTPUT CURRENT (A) VOUT vs. IOUT VOUT = 0.75V CONDITIONS VDDQ = 2*VOUT 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 OUTPUT VOLTAGE (V) OUTPUT CURRENT (A) VOUT vs. IOUT VOUT = 1.2V CONDITIONS VDDQ = 1.5V AVIN = 3.3V 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 1.54 OUTPUT VOLTAGE (V) OUTPUT CURRENT (A) VOUT vs. IOUT VOUT = 1.5V CONDITIONS VDDQ = 1.8V AVIN = 3.3V 0.635 0.645 0.655 0.665 0.675 0.685 0.695 0.705 0.715 -40 -25 -10 5 20 35 50 65 80 95 110 125 OUTPUT VOLTAGE (V) JUNCTION TEMPERATURE ( C) VOUT vs. TEMPERATURE LOAD = 0A CONDITIONS VOUT = 0.675V VDDQ = 2*VOUT AVIN = 3.3V 0.635 0.645 0.655 0.665 0.675 0.685 0.695 0.705 0.715 -40 -25 -10 5 20 35 50 65 80 95 110 125 OUTPUT VOLTAGE (V) JUNCTION TEMPERATURE ( C) VOUT vs. TEMPERATURE LOAD = 1A CONDITIONS VOUT = 0.675V VDDQ = 2*VOUT AVIN = 3.3V
9 www.altera.com/enpirion Typical Performance Characteristics
10 www.altera.com/enpirion Typical Performance Characteristics (Continued)
11 www.altera.com/enpirion Functional Block Diagram (+) (-) Error Amp VOUT HS-Drive LS-Drive UVLO Thermal Limit Current Limit Soft Start Pre-bias Sawtooth Generator (+) (-) PWM Comp VDDQ ENABLE Compensation Network Bandgap Reference PGND VFB EAOUT VREF Power Good Logic POK EAOUT EN_PB NC(SW) AVIN AVIN VSENSE EV1340QI FQADJ AVINAGND VDDB VDDQOK VDDQ 2.5V 196k 94k 18.8k Figure 4: Functional Block Diagram
12 www.altera.com/enpirion Functional Description Synchronous Buck Converter The EV1340 is a synchronous, programmable buck power supply with integrated power MOSFET switches and integrated inductor. The switching supply uses voltage mode control and a low noise PWM topology. Two power sources are required to operate this device; a power supply for the controller (AVIN) with a nominal input volt age range of 2.9-3.7V. The second supply (VDDQ) is the supply that is tracked - the recommended operating range is 1.0 to 1.8V. With the right choice of input and output dividers, the output voltage of the EV1340 will produce an output voltage which tracks to ½ VDDQ. The EV1340 can continuously source or sink currents up to 5A. The 1.5MHz nominal switching frequency enables small-size input and output capacitors. Enable Operation The ENABLE pin provides a means to enable normal operation or to shut down the device. When the ENABLE pin is asserted (high) the device will undergo a normal soft-start. A logic low on this pin will power the device down. Soft-Start and Soft-Shutdown The EV1340 can operate with the controller power supply (AVIN) ON, ENABLE High, and VDDQ ramped up and down at a relatively slow rate (~1V/ms). It is also expected that VDDQ may be dynamically scaled within a small voltage range. If, however, VDDQ should ramp up at a high rate, or if the device is enabled with a stable VDDQ, a capacitor connected between VREF and AGND provides the soft-start function to limit in-rush current. The soft-start time constant is determined by the input voltage divider and the soft-start capacitor. See Figure 5. Pre-Bias Start-up The EV1340 supports start up into a pre- biased load. A proprietary circuit ensures the output voltage ramps up monotonically from the pre-bias value to the programmed output voltage. Monotonic star t-up is guaranteed for pre-bias voltages in the range of >20% to <85% of the programmed output voltage. Outside of this range, the output voltage may not rise monotonically. T he Pre-Bias feature is controlled by the EN_PB pin. For the pre-Bias feature to function pr operly, VDDQ must be stable, and the device mu st be turned on and off using the ENABLE pin. VDDQOK Operation The VDDQOK pin can be used to indicate that the VDDQ voltage is in r egulation by tying it to an upstream POK signal. The upstream device is assumed to be driving the EV1340QI. VDDQOK is internally pulled up to 2.5V through a 94k resistor and is AND’ed with the POK of the EV1340QI. The VDDQOK’s high logic level voltage is cl amped at a diode drop above 2.5V. VDDQOK signal must be high in order for the POK of the EV1340QI to be high. POK Operation The internal EV1340 PO K is AND’ed with the VDDQOK input. POK is meant to be used with VDDQOK in a tracking application with VDDQ ramping. The VDDQOK input is assumed to be driven by the upstream VDDQ regulator’s POK output. Normally the VDDQOK input indicates that VDDQ has settled to the required level. If VDDQ is dynamically switched, VDDQOK is expected to mask the EV1340 POK during the voltage transition. POK is de-asserted low 64 clock cycles (~43µs at 1.5MHz) after the falling VOUT voltage crosses 45% (nominal) of VDDQ. POK is also de-asserted if VOUT exceeds 55% (nominal) of VDDQ. For proper POK thresholds, the input voltage divider must generate VREF nominally set to 0.4*VDDQ. Over-Current Protection The current limit function is achieved by sensing the current flowing in the hi-Side FET. When the sensed current exceeds the current limit, the PWM pulse is terminated for the rest
13 www.altera.com/enpirion of the switching cycle. If the over-current condition lasts only a few switching cycles, normal PWM operation is resumed. If the over- current condition persists, the circuit will continue to protect the load by entering a hiccup mode. In the hicc up mode, the output is disabled for approximately 20ms and then it goes through a soft-start. The output will no longer track the input voltage briefly as a result of the fault condition. This cycle can continue indefinitely as long as the over current condition persists. Thermal Overload Protection Temperature sensing circuits in the controller will disable operation when the Junction temperature exceeds approximately 150ºC. When the junction temperature drops by approx 20ºC, the conver ter will re-start with a normal soft-start cycle. Input Under-Voltage Lock-Out When the AVIN pin voltage is below a required voltage level (V UVLOR) for normal operation, converter switching is inhibited. The lock-out threshold has hysteresis to prevent chatter. When the device is operating normally, the AVIN voltage must fall below the lower threshold (V UVLOF) for the device to stop switching.
14 www.altera.com/enpirion
Application Information
Soft-Start Capacitor Selection A soft-start capacitor is recommended on the EV1340’s VREF pin to ground. The soft-start capacitor (CSS) serves as a slew rate limiter for fast VDDQ input ramps or for turning the device ON using the ENABLE pin. It is also a noise filter for noise coming from VDDQ. The soft-start time constant is determined by the value of this capacitor and the input divider resistors R C and R D. See Figure 5. Altera recommends a starting value of 3300pF for the soft-start capacitor on the VREF node. Output Voltage Programming and Loop Compensation The output voltage of EV1340QI is determined by the two voltage divi ders as shown in the simplified application diagram below: Figure 5: Typical Application Schematic The input voltage divider consisting of R C and RD should be selected to make VREF = 0.4 * VDDQ for proper POK operation. Altera recommends R C = 15kΩ and R D = 10kΩ. This resistor ratio is essential for proper operation of POK. In steady state, VREF = VFB, and VOUT = 0.5*VDDQ given the recommended values for R A RD. Although the EV1340 int egrates most of the compensation network, a phase lead capacitor and a resistor are required in parallel with the upper resistor R A of the external feedback network. See Figure 6 for all the component values in the compensation circuit, which has been optimized for use with 2X100 μF, 1206, X5R or X7R ceramic output capacitors. In rare cases, modifications to the compensation might be required. The EV1340 compensation can be modified for specific applications. For more information, contact Power Applications support. Figure 6: External Feedback and Compensation Network Input Capacitor Selection The EV1340 requires a minimum of 47µF of input capacitance for VDDQ. Additional capacitors (C AVIN and C1) of 10µF is recommended for AVIN and the resistor divider network of VREF (R C, R D). Low ESR ceramic capacitors are required with X5R or X7R dielectric formulation. Y5V or equivalent dielectric formulations must not be used because these dielectrics lose capacitance with frequency, temperature and bias voltage. In some applications, lower value ceramic capacitors maybe needed in parallel with the larger capacitors in order to provide high frequency decoupling. The table below shows some typical recommended input capacitors for the EV1340. Other capacitors with similar characteristics may also be used in the input circuit. Typical Recommended Input Capacitors Description MFG P/N 47µF, 10V, X5R, 1206 Taiyo Yuden LMK316BJ476ML-T 47µF, 4V, X5R, 0805 Murata GRM21BR60G476M AB A A A R R k R RC VDDQR value.calculated than lower valuestandard closest to down C Round ) F/ in /R (C 10 5 ) k in (value100 A A A
15 www.altera.com/enpirion Output Capacitor Selection The EV1340 has been optimized for use with 200µF of output capac itance. Low ESR ceramic capacitors are required with X5R or X7R dielectric formulation. Y5V or equivalent dielectric formulations must not be used as these lose capacitance with frequency, temperature and bias voltage. The capacitors shown in the table below are some typical output capacitors. Other capacitors with similar characteristics may also be used. Typical Recommended Output Capacitors Description MFG P/N 47µF, 10V, X5R, 1206 Taiyo Yuden LMK316BJ476ML-T 47µF, 6.3V, X5R, 1206 Taiyo Yuden Murata JMK316BJ476ML-T GRM31CR60J476ME19L 100µF, 6.3V, X5R, 1206 Murata GRM31CR60J107M Output ripple voltage is primarily determined by the aggregate output capac itor impedance. At the 1.5MHz switchi ng frequency output impedance, denoted as Z, is comprised mainly of effective series resistance, ESR, and effective series inductance, ESL: Z = ESR + ESL Placing multiple capacitors in parallel reduces the impedance and hence will result in lower ripple voltage. nTotal Z Z Z Z 1...1 1 1 2 1 Typical Ripple Voltages Output Capacitor Configuration Typical Output Ripple (mVp-p) VDDQ = 1.5V, VOUT = 0.75V 2 x 100 µF <10mV Schottky Diode Selection The EV1340 requires a Schottky diode from the SW pin to the VDDQ pin. The anode should be facing the SW pin and the cathode facing the VDDQ pin. Altera has characterized the ST Microelectronics TMBYV10-40FILM diode with the EV1340. Contact Power Applications support for alternate options for this diode. Low V IN Applications The EV1340 is an excellent solution for low V IN applications where highest efficiency is very critical. Reference the low V IN efficiency chart in the Typical Performance Characteristics section for estimated efficiencies at several use cases. In these applications, a precision voltage reference is required for the VREF input of the EV1340. Figure 7 shows a schematic for a typical low V IN application. Figure 7: Typical Low VIN Application Schematic Power-Up Sequencing During power up, neither ENABLE nor VDDQ should be asserted before AVIN. There are two common acceptable turn-on/off sequences for the device. ENABLE can be tied to AVIN and come up with it, and VDDQ can be ramped up and down as needed. Alte rnatively, VDDQ can be brought high after AVIN is asserted, and the device can be turned on and off by toggling the ENABLE pin.
16 www.altera.com/enpirion Layout Recommendations Figure 8 and Figure 9 shows critical components along with top and bottom traces of a recommended minimum footprint of the EV1340QI layout with ENABLE tied to V IN. Alternate ENABLE conf igurations and other small signal pins ne ed to be connected and routed according to specific customer application. Please see the Gerber files at www.altera.com/enpirion for exact dimensions and other layers. Please refer to Figures 8 and 9 while reading the lay out recommendations in this section. Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as cl ose to the EV1340QI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitor s and the EV1340QI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. Recommendation 2: There are a total of seven PGND pins dedica ted to the input and output circuits. The input and output ground currents should be separated with a slit until they reach the seven PGND pins to help minimize noise coupling between the converter input and output switching loops. Recommendation 3: The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. Please see the Gerber files at www.altera.com/enpirion. Recommendation 4: The large thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. Figure 8: Top PCB Layer with Critical Components and Copper for Minimum Footprint (Top View) Figure 9: Bottom PCB Layer with Critical Components and Copper for Minimum Footprint (Top View)
0.33mm, and the vias must have at least 1 oz. converter. Please see Figures 8, 9, 10, and 11. output capacitors to the system ground plane. proper filtering of the control circuit. Figure 8. See the section regarding exposed converter package on other layers. coupling into the control loop. the trace to this pin as short as possible. connection between AGND and PGND. further reduce noise coupling to VREF. customers to take advantage of this service. sales contact or to Power Applications support.
18 www.altera.com/enpirion Design Considerations for Lead-Frame Based Modules Exposed Metal on Bottom of Package Package lead frames offer advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. They do, however, require some special considerations. In the assembly process, lead-frame construction requires-for mechanical support- that some of the le ad-frame cantilevers be exposed at the point where wire-bonds or internal passives are attached. Because of this lead frame requirement, several small pads are exposed on the bottom of the package. Only the large thermal pad and the perimeter pads should be mechanically or electrically connected to the PC boar d. The PCB top layer under the EV1340 should be clear of any metal except for the large thermal pad. The hatched area in Figure 10 repres ents the area that should be clear of all me tal (traces, vias, or planes) on the top layer of the PCB. Figure 10: Lead-Frame Exposed Metal (Bottom View). The dimensioned hatched area highlights exposed metal below the device which should not be soldered down. There should not be any metal (traces, vias, or planes) on the top layer of the PCB below the hatched area.
19 www.altera.com/enpirion Recommended PCB Footprint Figure 11: EV1340QI PCB Footprint (Top View) The solder stencil aperture for the thermal pad is shown in blue and is based on Enpirion power product manufacturing specifications.
20 www.altera.com/enpirion Package and Mechanical Figure 12: EV1340 Package Dimensions Contact Information Altera Corporation
101 Innovation Drive
San Jose, CA 95134 Phone: 408-544-7000 www.altera.com/ © 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.