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Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 20
Technical content
Features
- High Efficiency, Up to 96%
- 4 0mm2 Total Solution Size
- No External Inductor Required
- JEDEC Compliant DDR2/3/QDR and Low Power DDR 4 Solution
- Enable Pin with Output Discharge to Support S3 (Suspend to RAM) Mode
- Operates Directly from VDDQ
- VOUT (VTT) Voltage Tracks VDDQ/2 ± 40mV
- Source and Sink Up to 2A Continuous Current
- Parallel Up to 4 Devices for 8A VTT Current
- Programmable Soft Start/Soft Shutdown
- Cost Effective Integrated Solution
- Thermal Overload, Over Current, Short Circuit, and Under-Voltage Protection
- RoHS Compliant, MSL level 3, 260C Reflow
Applications
- VTT Bus Termination for DDR2, DDR3, Low Power DDR4, and QDR Memories VTT C1P COUT CIN VOUT AVIN AGND SS VDDQ ENABLE PGND PGND C1N 15nF CFLY VDDQ 3.3V VREF DIVIDER VREF EV1320QI 10µF
Figure 1. Simplified Applications Circuit Figure 2. Highest Efficiency in Smallest Solution Size
06831 October 11, 2013 Rev B
Ordering Information
Part Number Package Markings Temp Rating (°C) Package Description EV1320QI AUxx -40 to +85 16-pin (3mm x 3mm x 0.55mm) QFN T&R EVB-EV1320QI AUxx QFN Evaluation Board Pin Assignments (Top View) NC 1 AVIN ENABLE POK SS AGND PGND PGND C1N C1N VOUT VOUT C1P C1P VDDQ VDDQ 6 7 8 9 1415 16 KEEP OUT Figure 3: Pin Out Diagram (Top View) NOTE A: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically connected to the PCB. Refer to Figure 10 for details. NOTE B: White ‘dot’ on top left is pin 1 indicator on top of the device package. Pin Description PIN NAM E FUNCTION 1 NC This pin is internally not connected. May be used as part of the VDDQ copper to optimize the layout. Otherwise, leave this pin open. See Figure 9.
2 AVIN Input Supply for internal controller and protection circuitry
3 ENABLE
Input Enable. Applying a logic high enables the output and initiates a soft-start. Applying a logic low disables and discharges the output. ENABLE is internally tied to AVIN and ground through a 100k resistor divider. Leaving ENABLE floating will result in voltage at half of AVIN. 4 POK VTT OK flag. This is an open drain output usually pulled up to AVIN. Leave floating if unused. 5 SS Soft Start pin. Connect soft start capacitor between this pin and AGND. 6 AGND Quiet ground for analog circuitry. Connect to the ground plane with a via next to the pin. 7, 8 PGND Power ground. Connect these pins to the ground electrode of the input and output filter capacitors. See layout recommendations for more details. 9,10 C1N Place 1 x 22µF and 1 x 10µF X5R MLCC capacitors between C1N and C1P. 11,12 VOUT VTT voltage = ½ VDDQ. 13,14 C1P Place 1 x 22µF and 1 x 10µF X5R MLCC capacitors between C1N and C1P. 15,16 VDDQ VDDQ voltage; VOUT (VTT) tracks this voltage. w ww.altera.com/enpirion, Page 2
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER SYMBOL MIN M AX UNITS Voltage on AVIN -0.5 4.0 V Voltage on C1P, C1N -0.5 2.0 V Voltage on AGND, PGND -0.5 AVIN + 0.3 V Voltage on VDDQ -0.5 2.2 V Voltage on VOUT -0.5 VDDQ + 0.3 V Voltage on POK -0.5 AVIN + 0.3 V Voltage on SS -0.5 AVIN + 0.3 V Voltage on ENABLE -0.5 AVIN + 0.3 V Storage Temperature Range TSTG -65 150 °C Maximum Operating Junction Temperature TJ-ABS Max 150 °C Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 °C ESD Rating (based on Human Body Model): All pins 2000 V ESD Rating (based on Charged Device Model) 500 V Recommended Operating Conditions PARAMETER SYMBOL MIN M AX UNITS Operating Junction Temperature TJ -40 +125 °C Operating Ambient Temperature TA -40 +85 °C Thermal Characteristics PARAMETER SYMBOL TYP UNITS Thermal Resistance: Junction to Ambient (0 LFM) (Note 1) θJA 50 °C/W Thermal Shutdown TSD 150 °C Thermal Shutdown Hysteresis TSDH 25 °C Note 1: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high thermal conductivity boards. www.altera.com/enpirion, Page 3
Electrical Characteristics
NOTE: AVIN = 3.3V; VDDQ = 1.5V. Minimum and Maximum values are over operating ambient temperature range unless otherwise noted. Typical values are at TA = 25°C. PARAMETER SYMBOL TEST CONDITIONS MIN TYP M AX UNITS VDDQ voltage range VDDQ 0.95 1.5 1.8 V AVIN voltage range AVIN 3.0 3.3 3.465 V VTT Tracking Accuracy DC (NOTE 2) ∆VTT AVIN=3.3V±5% 0A ≤ IVTT ≤ 2A 0.49* VDDQ − 40 0.51* VDDQ + 40 mV Under Voltage Lockout; AVIN rising VUVLO 2.5 V Under Voltage Lockout; AVIN falling VUVLO 2.2 V AVIN Shut-Down Supply Current IS ENABLE=Low 600 µA VDDQ Shut-Down Supply Current IS ENABLE=Low 200 µA AVIN No Load Operating Current IAVIN AVIN=3.3V 6 mA VDDQ No Load Operating Current IVDDQ AVIN=3.3V 750 µA Switching Frequency FSW 500 625 750 kHz POK Threshold Sourcing Current VOUT Rising 95 % POK Threshold Sourcing Current VOUT Falling 85 % POK Low Voltage ISINK = 1mA 0.15 0.4 V POK Pin VOH Leakage Current AVIN = 3.3V POK High 25 µA Output Impedance ROUT ∆VOUT/∆ILOAD 20 mΩ Continuous Output Current; I_Max_Source VDDQ=1.5V AVIN=3.3V -2 2 A Over Current Trip Level IOCP AVIN=3.3V ±4.5 A Enable Threshold Logic Low ENA_VIL Max voltage to ensure the converter is disabled 0.3 V Enable Threshold Logic High ENA_VIH 3.0V ≤ AVIN ≤ 3.46V AVIN –
0.5 AVIN V
Enable Input Current 100 200 µA Note 2: As measured at the bulk capacitors at the edge of EV1320QI evaluation board. Complies with JEDEC DDR2 and DDR3 VDDQ tracking specification. www.altera.com/enpirion, Page 4
Typical Performance Curves EFFICIENCY (%) OUTPUT CURRENT (A) Efficiency vs. Output Current VTT = 0.9V VTT = 0.75V VTT = 0.6V CONDITIONS AVIN = 3.0V VDDQ = 2* VTT EFFICIENCY (%) OUTPUT CURRENT (A) Efficiency vs. Output Current VTT = 0.9V VTT = 0.75V VTT = 0.6V CONDITIONS AVIN = 3.3V VDDQ = 2* VTT EFFICIENCY (%) OUTPUT CURRENT (A) Efficiency vs. Output Current VTT = 0.9V VTT = 0.75V VTT = 0.6V CONDITIONS AVIN = 3.6V VDDQ = 2* VTT 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 VTT (V) VDDQ (V) Output Voltage vs. Input Voltage LOAD = 0A LOAD = 1A LOAD = 2A CONDITIONS AVIN = 3.0V Note: VTT is measured at bulk caps on evaluation board edge 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 VTT (V) VDDQ (V) Output Voltage vs. Input Voltage LOAD = 0A LOAD = 1A LOAD = 2A CONDITIONS AVIN = 3.3V Note: VTT is measured at bulk caps on evaluation board edge 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 VTT (V) VDDQ (V) Output Voltage vs. Input Voltage LOAD = 0A LOAD = 1A LOAD = 2A CONDITIONS AVIN = 3.6V Note: VTT is measured at bulk caps on evaluation board edge www.altera.com/enpirion, Page 5
Typical Performance Curves (Continued) 0.54 0.55 0.56 0.57 0.58 0.59 0.60 0.61 0.62 0.63 0.64 VTT (V) OUTPUT CURRENT (A) Output Voltage vs. Output Current TA = -45 C TA = 25 C TA = 85 C CONDITIONS AVIN = 3.3V VDDQ = 1.2V VTT = 0.6V Note: VTT is measured at bulk caps on evaluation board edge 0.70 0.71 0.72 0.73 0.74 0.75 0.76 0.77 0.78 0.79 0.80 VTT (V) OUTPUT CURRENT (A) Output Voltage vs. Output Current TA = -45 C TA = 25 C TA = 85 C CONDITIONS AVIN = 3.3V VDDQ = 1.5V VTT = 0.75V Note: VTT is measured at bulk caps on evaluation board edge 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 0.92 0.93 0.94 VTT (V) OUTPUT CURRENT (A) Output Voltage vs. Output Current TA = -40 C TA = 25 C TA = 85 C CONDITIONS AVIN = 3.3V VDDQ = 1.8V CONDITIONS AVIN = 3.3V VDDQ = 1.8V VTT = 0.9V Note: VTT is measured at bulk caps on evaluation board edge 0.50 0.52 0.54 0.56 0.58 0.60 0.62 0.64 0.66 0.68 0.70 -40 -15 10 35 60 85 VTT (V) AMBIENT TEMPERATURE ( C) Output Voltage vs. Temperature LOAD = 0A LOAD = 1A LOAD = 2A CONDITIONS AVIN=3.3V VDDQ = 1.2V Note: VTT is measured at bulk caps on evaluation board edge 0.65 0.67 0.69 0.71 0.73 0.75 0.77 0.79 0.81 0.83 0.85 -40 -15 10 35 60 85 VTT (V) AMBIENT TEMPERATURE ( C) Output Voltage vs. Temperature LOAD = 0A LOAD = 1A LOAD = 2A CONDITIONS AVIN=3.3V VDDQ = 1.5V Note: VTT is measured at bulk caps on evaluation board edge 0.80 0.82 0.84 0.86 0.88 0.90 0.92 0.94 0.96 0.98 1.00 -40 -15 10 35 60 85 VTT (V) AMBIENT TEMPERATURE ( C) Output Voltage vs. Temperature LOAD = 0A LOAD = 1A LOAD = 2A CONDITIONS AVIN=3.3V VDDQ = 1.8V Note: VTT is measured at bulk caps on evaluation board edge www.altera.com/enpirion, Page 6
Typical Performance Curves (Continued) -40 -15 10 35 60 85 AVIN INPUT CURRENT (mA) AMBIENT TEMPERATURE( C) AVIN Input Current vs. Temperature AVIN = 3.6V AVIN = 3.3V AVIN = 3.0V CONDITIONS VDDQ = 1.5V VTT = 0.75V -40 -15 10 35 60 85 AVIN INPUT CURRENT (mA) AMBIENT TEMPERATURE( C) AVIN Input Current vs. Temperature VDDQ = 1.2V VDDQ = 1.5V VDDQ = 1.8V CONDITIONS AVIN = 3.3V 200 300 400 500 600 700 800 900 1000 -40 -15 10 35 60 85 VDDQ INPUT CURRENT (µA) AMBIENT TEMPERATURE( C) VDDQ Input Current vs. Temperature AVIN = 3.6V AVIN = 3.3V AVIN = 3.0V CONDITIONS VDDQ = 1.5V VTT = 0.75V No Load 200 300 400 500 600 700 800 900 1000 -40 -15 10 35 60 85 VDDQ INPUT CURRENT (µA) AMBIENT TEMPERATURE( C) VDDQ Input Current vs. Temperature VTT = 0.6V VTT = 0.75V VTT = 0.9V CONDITIONS AVIN = 3.3V VDDQ = 2*VTT No Load 500 550 600 650 700 750 -40 -15 10 35 60 85 OSCILLATOR FREQUENCY (kHz) AMBIENT TEMPERATURE( C) Frequency vs. Temperature AVIN = 3.6V AVIN = 3.3V AVIN = 3.0V CONDITIONS VDDQ = 1.5V VTT = 0.75V 100 1000 0.1 1 10 100 VTT RISE TIME (µs) SS CAPACITANCE (nF) VTT Rise Time vs. Capacitance CONDITIONS VDDQ = 1.5V VTT = 0.75V www.altera.com/enpirion, Page 7
Typical Performance Characteristics VOUT (AC Coupled) Output Ripple at 1A Load CONDITIONS AVIN = 3.3V VDDQ = 1.5V VTT = 0.75V CIN=22µF, COUT=22µF, C1P = 22µF+1x10µF Load = 1A Note: Output ripple is measured at bulk capacitors on evaluation board edge 500MHz Bandwidth VOUT (AC Coupled) Output Ripple at 2A Load CONDITIONS AVIN = 3.3V VDDQ = 1.5V VTT = 0.75V CIN=22µF, COUT=22µF, C1P = 22µF+1x10µF Load = 2A Note: Output ripple is measured at bulk capacitors on evaluation board edge 500MHz Bandwidth Switching Waveform at No Load CONDITIONS AVIN = 3.3V, VDDQ = 1.5V, VTT = 0.75V, CIN=22µF, COUT=22µF, C1P = 22µF+1x10µF CH1:VDDQ CH2:C1P CH3:C1N CH4:VTT Switching Waveform at 500mA CONDITIONS AVIN = 3.3V, VDDQ = 1.5V, VTT = 0.75V, CIN=22µF, COUT=22µF, C1P = 22µF+1x10µF CH1:VDDQ CH2:C1P CH3:C1N CH4:VTT Switching Waveform at 1A CONDITIONS AVIN = 3.3V, VDDQ = 1.5V, VTT = 0.75V, CIN=22µF, COUT=22µF, C1P = 22µF+1x10µF CH1:VDDQ CH2:C1P CH3:C1N CH4:VTT Switching Waveform at 2A CONDITIONS AVIN = 3.3V, VDDQ = 1.5V, VTT = 0.75V, CIN=22µF, COUT=22µF, C1P = 22µF+1x10µF CH1:VDDQ CH2:C1P CH3:C1N CH4:VTT www.altera.com/enpirion, Page 8
Typical Performance Characteristics (Continued) VTT (AC Coupled) Load Transient from 0 to 500mA CONDITIONS AVIN = 3.3V VDDQ = 1.5V VTT = 0.75V CIN=22µF, COUT=22µF C1P = 22µF+1x10µF) LOAD VDDQ (AC Coupled) ΔVTT is due to ΔVDDQ Note: Output deviation is measured at bulk capacitors on evaluation board edge VTT (AC Coupled) Load Transient from 0 to 1A CONDITIONS AVIN = 3.3V VDDQ = 1.5V VTT = 0.75V CIN=22µF, COUT=22µF C1P = 22µF+1x10µF LOAD VDDQ (AC Coupled) ΔVTT is due to ΔVDDQ Note: Output deviation is measured at bulk capacitors on evaluation board edge VTT (AC Coupled) Load Transient from 0 to 1.5A CONDITIONS AVIN = 3.3V VDDQ = 1.5V VTT = 0.75V CIN=22µF, COUT=22µF C1P = 22µF+1x10µF LOAD VDDQ (AC Coupled) ΔVTT is due to ΔVDDQ Note: Output deviation is measured at bulk capacitors on evaluation board edge VTT (AC Coupled) Load Transient from 0 to 2A CONDITIONS AVIN = 3.3V VDDQ = 1.5V VTT = 0.75V CIN=22µF, COUT=22µF C1P = 22µF+1x10µF LOAD VDDQ (AC Coupled) ΔVTT is due to ΔVDDQ Note: Output deviation is measured at bulk capacitors on evaluation board edge VDDQ (AC Coupled) VDDQ to VTT Tracking with Line CONDITIONS LOAD = 1Ω AVIN = 3.3V, CIN=22µF, COUT=22µF, C1P = 22µF+1x10µF VTT (AC Coupled) ΔVTT is due to ΔVDDQ ENABLE Startup with POK at No Load VDDQ CONDITIONS No Load CSS = 15nF AVIN = 3.3V, VDDQ = 1.2V, VTT = 0.6V, CIN=22µF, COUT=22µF, C1P = 22µF+1x10µF VTT POK www.altera.com/enpirion, Page 9
Typical Performance Characteristics (Continued) ENABLE Startup with POK at 2A VDDQ CONDITIONS No Load CSS = 15nF AVIN = 3.3V, VDDQ = 1.2V, VTT = 0.6V CIN=22µF, COUT=22µF C1P = 22µF+1x10µF VTT POK ENABLE Parallel Operation Startup at 4A VDDQ (VDDQ#1 tied to VDDQ#2) CONDITIONS LOAD = 4A CSS = 15nF AVIN = 3.3V, VDDQ = 1.8V, VTT = 0.9V, CIN=22µF, COUT=22µF C1P = 22µF+1x10µF VTT (VTT#1 tied to VTT#2) Total Load = 4A (2A + 2A) Parallel VDDQ Startup with POK VDDQ (VDDQ#1 tied to VDDQ#2) CONDITIONS LOAD = 4A, CSS = 15nF AVIN = 3.3V, VDDQ = 1.8V, VTT = 0.9V, CIN=22µF, COUT=22µF C1P = 22µF+1x10µF VTT (VTT#1 tied to VTT#2) POK #1 POK #2 Parallel Operation at 4A CH1: VDDQ (VDDQ#1 tied to VDDQ#2) CH2:VTT (VTT#1 tied to VTT#2) Total Load = 4A (2A + 2A) Load #2: 2A Load #1: 2A Parallel Operation Load Transient CH1: VDDQ (VDDQ#1 tied to VDDQ#2) CONDITIONS LOAD = 4A AVIN = 3.3V, VDDQ = 1.5V, VTT = 0.75V, CIN=22µF, COUT=22µF C1P = 22µF+1x10µF CH2: VTT (VTT#1 tied to VTT#2) LOAD ΔVTT is due to ΔVDDQ Note: Output deviation is measured at bulk capacitors on evaluation board edge www.altera.com/enpirion, Page 10
Figure 4: Functional Block Diagram www.altera.com/enpirion, Page 11
DDR4 JEDEC memory termination requirements. Table 1. Typical Soft-Start Capacitance Time Table output will be discharged through a 100Ω resistor. lower than 100Ω , the output will discharge faster. The ENABLE pin should not be left floating. transition is complete for enhanced noise immunity. consumption in shutdown mode.
The overload function is achieved by sensing the output voltage. An overload state is entered when the device is out of soft start and the output voltage drops below ~85% of VDDQ/2. When an OCP condition is detected, the device is disabled, the output is discharged through a 100 resistor for a period of 1.5mS. After the 1.5mS discharge time has expired, a soft start is initiated as described in the soft start section. If an over current condition is again detected the device will repeat the discharge/soft start cycle in a hiccup manner as long as the over current condition persists. Thermal Overload Protection Thermal shutdown will disable operation when the Junction temperature exceeds approximately 150ºC. Output will discharge through a 100 ohm resistor for 1.5mS. If the thermal fault condition is still present then the device will hiccup until temp falls by 25°C. Once the junction temperature drops by approximately 25ºC, the converter will re- start with a normal soft-start. Input Under -Voltage Lock -out Internal circuits ensure that the converter will not start switching until the AVIN voltage is above the specified minimum voltage. www.altera.com/enpirion, Page 13
Application Information
3.3V VREF DIVIDER VREF EV1320QI 10µF 22µF 22µF + 1 x 10µF 22µF OPTIONAL Figure 6. General Application Circuit for 2A Operation described in “Enable Operation” section.
connected between VDDQ pin and the PGND pin. Table 1. Recommended Capacitor Configurations not use Y5V or equivalent dielectric capacitors. appropriate for use in DCDC converter applications. paralleled to achieve a VTT current of up to 8A.
- The VDDQ inputs should be connected to a
- The VOUT connections should be
connected to a common VTT bus.
- Each EV1320QI device must have its own
- The C1N-C1P capacitors should only be
- All AVIN connections should be tied to a
- All ENABLE pins should be tied to a
- All soft start pins should be tied together
- All Analog ground (AGND) connections
- All Power ground (PGND) connections
- The devices should be placed such that the
equivalent to ensure current balance.
Figure 7. Parallel Operation with Three EV1320QI you to view and submit service requests.
Thermal considerations are important physical limitations that cannot be avoided in the real world. Whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be accounted for. The Altera Enpirion EV1320QI VDDQ/VTT Converter is packaged in a 3x 3x0.55mm 16-pin QFN package. The recommended maximum junction temperature for continuous operation is 125°C. Continuous operation above 125°C may reduce long- term reliability. The device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of 150°C. The EV1320QI is guaranteed to support the full 2A output current up to 85°C ambient temperature. The following example and calculations illustrate the thermal performance of the EV1320QI. Example: VDDQ = 1.2V VTT = 0.6V I OUT = 2A First calculate the output power. POUT = VTT * IOUT = 0.6V x 2A = 1.2W Next, determine the input power based on the efficiency (η) shown in Figure 8. Figure 8: Efficiency vs. Output Current For VDDQ = 1.2V, VTT = 0.6V at 2A, η ≈ 92.6% η = POUT / PIN = 92.6% = 0.926 PIN = POUT / η PIN ≈ 1.2W / 0.926 ≈ 1.2959W The power dissipation (PD) is the power loss in the system and can be calculated by subtracting the output power from the input power. PD = PIN – POUT ≈ 1.2959W – 1.2W ≈ 0.0959W With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA value (θ JA). The θJA parameter estimates how much the temperature will rise in the device for every watt of power dissipation. The EV1320QI has a θ JA value of 50 ºC/W without airflow. Determine the change in temperature (ΔT) based on PD and θJA. ΔT = PD x θJA The junction temperature (T J) of the device is approximately the ambient temperature (T A) plus the change in temperature. We assume the initial ambient temperature to be 25°C. TJ = TA + ΔT With 0.0959W dissipated into the device, the TJ will be 29.8°C. The maximum operating junction temperature JMAX) of the device is 125°C, so the device can operate at a higher ambient temperature. The maximum ambient temperature (T AMAX) allowed can be calculated. TAMAX = TJMAX – PD x θJA The ambient temperature can actually rise by another 95.2°C, bringing it to 1 20.2°C before the device will reach T JMAX. This indicates that the EV1320QI can support the full 2 A output current range up to approximately 1 20.2°C ambient temperature given the input and output voltage conditions. This allows the EV1320QI to guarantee full 2A output current capability at 85°C with room for margin. Note that the efficiency will be slightly lower at higher temperatures and these calculations are estimates. EFFICIENCY (%) OUTPUT CURRENT (A) Efficiency vs. Output Current VTT = 0.6V CONDITIONS AVIN = 3.0V VDDQ = 2* VTT 92.6% www.altera.com/enpirion, Page 17
Figure 9: Typical Top Side and Bottom Side Layout Recommendation (Top View) Figure 9 shows the critical components along with top and bottom traces of a recommended minimum footprint EV1320QI layout with ENABLE tied to VDDQ. Alternate enabling configurations, and the POK pin would have to be connected and routed according to the specific customer application. Please see the Gerber files at www.altera.com/enpirion for exact dimensions and the internal layers. Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EV1320QI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal relief s or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the EV1320QI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors . Recommendation 2: The C1N- C1P capacitors should be placed as close to the C1N- C1P pins as possible. Use large copper planes to minimize resistance and inductance. The C1P and C1N traces between the capacitors and the EV1320QI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. Recommendation 3: The system ground plane should be the first layer immediately below the surface layer (layer 2). This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. Recommendation 4: The VDDQ and VOUT copper are paralleled on layers 3 and 4 in order to minimize overall series resistance. Please see Gerber files. Recommendation 5: AVIN is the power supply for the internal control circuits. It should be connected to the 3.3V bus at a quiet point. A 10µF bypass capacitor (shown on the backside in Figure 9) is needed on the AVIN node. If the AVIN supply is noisy, an optional 1Ω resistor is recommended in series with AVIN. See Figure 6. Recommendation 6: The AGND pin does not get connected to PGND on layer 1. It connects to PGND on layer 2 ground plane. This provides som e noise isolation between AGND and the noisy PGND trace on layer 1. Recommendation 7: The soft-start capacitor CSS and the AVIN capacitor CAVIN are placed on the back side in Figure 9 so that the input PGND trace is not compromised. Recommendation 8: If POK needs to be used, place a via to the left of pin 4, and route the POK trace on layer 3 to the POK resistor. Place the POK resistor to AVIN such that any modifications to the traces and placements in this recommended layout are minimized. Recommendation 9: Follow all the layout recommendations as close as possible to optimize performance. Altera provides schematic and layout reviews for all customer designs. Please contact www.altera.com/mysupport for Power Applications support. www.altera.com/enpirion, Page 18
Figure 10: EV1320QI PCB Footprint (Top View) www.altera.com/enpirion, Page 19
Figure 11: EV1320QI Package Dimensions (Bottom View) Contact Information Altera Corporation
101 Innovation Drive
San Jose, CA 95134 Phone: 408-544-7000 www.altera.com © 2013 Altera Corporation —Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademark s of Altera Corporation and regis tered in the U.S. Patent and Trademark Office and in other countries . All other words and logos identified as trademark s or s ervice mark s are the property of their res pective holders as des cribed at www.altera.com/common/legal.html. Altera warrants performance of its s emiconductor products to current s pecifications in accordance with Altera's s tandard warranty, but res erves the right to mak e changes to any products and s ervices at any time without notice. Altera as s umes no res pons ibility or liability aris ing out of the application or us e of any information, product, or s ervice des cribed herein except as expres s ly agreed to in writing by Altera. Altera cus tomers are advis ed to obtain the lates t vers ion of device s pecifications before relying on any publis hed information and before placing orders for products or s ervices. www.altera.com/enpirion, Page 20