ET6202

ET6202 ETEK | Alldatasheet

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Technical content

Features

z A variety of display modes: choice of settings, and the number of spaces (4 to 7, 10 to 13) z Scan button: 10 × 2 matrix z 8 levels of brightness adjustment circuit z 4-wire serial interface z Package for SOP28 Pin assignment 14 15 OSC DI /O CLK ST B VDD SG1 / KS1 SG2 / KS2 SG3 / KS3 SG4 / KS4 SG5 / KS5 SG6 / KS6 SG7 / KS7 SG8 / KS8 SG9 / KS9 SG1 0 / KS1 0 SG1 2 / GR7 SG1 3 / GR6 SG1 4 / GR5 VD D GN D GN D GN D GR 1 GR 2 GR 3 GR 4 ET6202

Rev 1.1 2004-6-4 Pin Description Pin Name I/O Description of the function

1 OSC I Oscillation input port to connect a resistor to determine the oscillation frequency

2 DI/O I/O

Data input and output ports (N-channel open drain), the clock in the serial data output falling, In the clock rising edge of the serial data input.

3 CLK I Clock input port, when read in the rising edge of the serial data, and in falling

output when the number According to 4 STB I Serial interface filtering, falling in the STB input data as an order. (External pull-down power Resistance) 5，6 K1～K2 I Key input data port, the port on the importation of these data show that there is locked at the end of the cycle End 22，25，

28 GND ─ Grounding pin

8～17 SG1/KS1～ SG10/KS10 O Paragraph output port (P-channel open drain), can also be used as keys input scanning VDD ─ Power Supply 19，20， 24，26， GR6～GR1 O Gate output port I / O configuration The logical part of the I / O diagram below. 1. Input port: CLK, STB & DIN VD D GND

18 SG12/GR7 O Paragraph / output port gate

7，21 Number ET6202

Rev 1.1 2004-6-4 2. Input: K1 ~ K2 VDD GND 3. Output ports: DOUT, GR1 ~ GR4 VDD GND 4. Outputs: SG1 ~ SG10 VD D GND

Rev 1.1 2004-6-4 5. GR5,GR6 and SG12/GR7 VD D GND Functional block diagram Control Show memory Timing generator Key scan matrix Memory Crystal Serial Data Interface Brightness adjustment circuit R OSC GND Paragraph driver / Scan key driver / Gate driver SG1/KS1 SG2/KS2 SG3/KS3 SG4/KS4 SG5/KS5 SG6/KS6 SG7/KS7 SG8/KS8 SG9/KS9 SG10/KS10 SG12/GR7 GR1 GR2 GR3 GR4 SG14/GR5 SG13/GR6 DI/O CLK STB K1 K2 VDD GND

Rev 1.1 2004-6-4 Functions Order STB ports in the state by the high-low, the importation of an order by the DIN port of the first byte (b0 ~ b7). If the data or the order in the transmission For some reason, STB is set to port, serial communications are to be initialized, the data is input / command be considered invalid. Order 1: display mode command set ET6202 provides as follows two display modes: a command in the port of the STB by the state after the high-low by the DIN port to lose ET6202 into the first byte (b0 ~ b7). For these orders, the No. 3 to No. 6 (b2 ~ b5) are ig- nored, 7 and 8 (b6 ~ b7) 0. Display mode command set used by the decision, gate number (4 to 7, 10 to 13). Must show that an order to continue to make the show. If you choose the same mode settings, not to implement the order, so there will be no show. When the electric power, the choice of 10 × 7-bit mode. MSB LSB 0 0 ─ ─ ─ ─ b1 b0 b2 ~ b5 no assignment Display mode: b1 for 0, b0 to 0:13 paragraph × 4 bits b1 for 0, b0 to 1:12 paragraph bit × 5 b1 for 1, b0 to 0:11 paragraph bit × 6 b1 for 1, b0 1:10 paragraph bit × 7 Order 2: Set the order data Data set is the order of implementation of the ET6202 read and write data. The first order of 5 and 6 (b4, b5) are ignored, 8-bit (b7) 0, No. 7 (b6) is set to 1. When the electric power supply when the first 4 to a (b3 ~ b0) should be set to 0 MSB LSB 0 1 ─ ─ b3 b2 b1 b0 b4, b5 non-assignment Mode: b3 0: normal mode of operation b3 1: Test mode Incremental mode address settings (mode): b2 0: After the data into the Incremental address b2 1: Address the same Read and write data mode: b1 for 0, b0 0: write data to the display mode b1 for 1, b0 0: Reading key scan data

Rev 1.1 2004-6-4 ET6202's key scan matrix scan button and enter the data storage RAM The ET6202 is a key scan matrix, as follows from the 10 × 2 array composed of: SG1 / SG2 / SG3 / SG4 / SG5 / SG6 / SG7 / SG8 / SG9 / SG1 0 / KS1 KS2 KS3 KS4 KS5 KS6 KS7 KS8 KS9 KS10 Each scan key input data storage as follows, by an order from the highest-READ was read out. When the high data (b0) was read out, The next lowest data (b7) was read out. SG1/KS1 SG2/KS2 x SG3/KS3 SG4/KS4 x SG5/KS5 SG6/KS6 x SG7/KS7 SG8/KS8 x SG9/KS9 SG10/KS10 x Read order Notes: b5 ~ b7 no definition. Order 3: Address set up a command Address set up a command is set up for display memory address. If the address is 00H ~ 0DH, then the effective address. If the address is 0EH Address or higher, the data is invalid unless once again set the correct address. When the electric power, to address 00H. Please refer to the chart below. MSB LSB 1 1 ─ ─ b3 b2 b1 b0 b4, b5 non-assignment b0 to b3 address 00H ~ 0DH

Rev 1.1 2004-6-4 Display mode and the address of the RAM Display RAM memory through the serial interface from the external device to input data ET6202. ET6202 of RAM address is as follows (8 units). 00HL 00HU 01HL DIG1 02HL 02HU 03HL DIG2 04HL 04HU 05HL DIG3 06HL 06HU 07HL DIG4 08HL 08HU 09HL DIG5 0AHL 0AHU 0BHL DIG6 0CHL 0CHU 0DHL DIG7 xxHL xxHU Low 4 High 4 Order 4: Display Control Order Display Control command to control the display switches can also be used to set pulse width. Please refer to the table below. When the electric power, setting 1 / 16 the width letter and the show closed (key stop scanning). MSB LSB 1 0 ─ ─ b3 b2 b1 b0 b4, b5 non-assignment Show: b3 0: The show closed (to scan button) b3 1: Open show Dimming level: 000: width = 1 / 16 001: width = 2 / 16 010: width = 4 / 16 011: width = 10/16 100: width = 11/16 101: width = 12/16 110: width = 13/16 111: width = 14/16

Rev 1.1 2004-6-4 Scan timing and show Bond plans to scan and display timing is as follows. A key scan cycle includes 2. 10 × 2 matrix of data stored in RAM. SG Out put DIG1 DIG2 DIG3 DIGn DIG1

1 A =Tdisplay ×（n+1）

Tdisplay=500us Key scan data

Rev 1.1 2004-6-4 Serial communication format The chart shown in the ET6202 is a serial communication format. DOUT port is an N-channel open drain output port, so be sure to add a guarantee Pull-up resistor (1K ~ 10K) to DOUT port. If the data continue ST B DIN 1 2 3 7 8 b0 b1 b2 b6 b7 CLK Receiver (data / write operations command) Transmission (read data) STB DIN 1 2 3 7 8 b0 b1 b2 b3 CLK b4 b5 b6 b7 4 5 6 1 2 3 4 5 6 b0 b1 b2 b3 b4 b5 twait Reading set up a command data Start reading data twait(Latency) ≥ 1μs ）≥1µs It is worth noting that when reading data, the instructions of the eighth of the clock rising edge to read the data then the first falling edge of the clock must be greater than or 1μs mean waiting time twait

Rev 1.1 2004-6-4 Conversion characteristic waveform ET6202 conversion wave characteristics are as follows. PWSTB tCLK-STB fosc 50% tse tup thold tPZL tPLZ tTZL tTLZ tTZH tTHZ 90% 10% 10% 90% OSC ST B CLK DIN DOUT Gn Sn PWCLK PWCLK PWCLK (Clock pulse) ≥ 400ns PWSTB(Filter width) ≥ 1μs tsetup(Data setup time) ≥ 100ns thold(Data hold time) ≥ 100ns tCLK-STB(Filter clock time) ≥ 1μs tTHZ(Fall time) ≤ 10μs tTZH(Rise time) ≤ 1μs tPZL(Transmission delay) ≤ 100ns fosc = oscillation frequency tPLZ(Transmission delay) ≤ 300ns tTZL<1µs tTLZ<10µs

Rev 1.1 2004-6-4 Notes: The test conditions are as follows. tTHZ(Pull-down resistance = 10kΩ, load capacitance = 300pf) tTLZ(Pull-up resistor = 10kΩ, load capacitance = 300pf) Apply 1. Input data show Order 1Order 2 Order 3 Order 4Data 1 Data n STB CLK DIN Order 1: display mode command set Order 2: Set the order data Order 3: Address set up a command Data 1 ~ n: mobile data show that (the largest of 14 bytes) Order 4: Display Control Order 2. Enter a specific address Order 1Order 2 Order 3 Order 4Data STB CLK DIN Order 2: Set data Order 3: Address Setting Data: The data show

Rev 1.1 2004-6-4 Software flow chart Start Delay 200 ms Set Order 2 (Write data) Set 3 order Qing display RAM (See Note) Set Order 1 Set Order 4 (88H-8FH: open the show) Main program Set Order 2 (Including the key time to scan the data and write data) Set 3 order Set Order 1 Set Order 4 End Initialization Set Main cycle

Rev 1.1 2004-6-4 Notes: 1. Order 1: display mode 2. Order 2: Set data 3. Order 3: Address Setting 4. Order 4: Display Control When the power supply IC of the first power-on, the display RAM in the content has not been defined, so be sure to empty the initialization settings in the display RAM. Limit parameter 1. Maximum Ratings(Ta = 25Co，GND=0V Parameters Symbol Range Unit To provide voltage VDD -0.5～+7 V Logic input voltage VI -0.5～VDD+0.5 V IOLGR +250 mA Drive output current IOHSG -50 mA Maximum output current ITOTAL 400 mA 2. Recommended by the working conditions(Ta = -20～+70℃，GND = 0V) Parameters Symbol Minimum Typical Max Unit Logic supply voltage VDD 4.5 5 5.5 V Dynamic current (see Note) I DDdyn — — 5 mA 高电平输入电压 VIH 0.8V DD — VDD V 低电平输入电压 VIL 0 — 0.3VDD V 注释：测试条件：设置显示控制命令=80H（显示关闭状态&无载入情况） 电参数（VDD = 5V，GND = 0V，Ta = 25℃） 参数 符号 测试条件 最小值 典型值 最大值 单位 IOHSG1 V0=VDD-2V SG1～SG11, SG12/GR7 -20 -25 -40 mA 高电平输出电流 IOHSG2 V0=VDD-3V SG1～SG11, SG12/GR7 -25 -30 -50 mA 低电平输出电流 IOLGR V0=0.3V GR1～GR6, SG12/GR7 100 140 — mA 低电平输出电流 IOLDOU T Vo= 0 .4 V 4 — — mA 段输出端高电平输出 电流百分比 ITOLSG V0=VDD-3V SG1～SG11, SG12/GR7 — — +5 % 高电平输入电压 VIH — 0.8VDD — 5 V 低电平输入电压 VIL — 0 — 0.3VDD V 振荡频率 fosc R=51k 350 500 650 kHz K1～K2 的下拉电阻 RKN K1～K2 VDD=5V 40 — 100 kΩ

Rev 1.1 2004-6-4 Reference to the road map Applications SW29 SW28 OSC DI/O CL K ST B VD D SG1 / KS1 SG2 / KS2 SG3 / KS3 SG4 / KS4 SG5 / KS5 SG6 / KS6 SG8 / KS8 SG9 / KS9 SG1 0 / KS1 0 SG1 2/ GR7 SG1 3 / GR6 SG1 4 / GR5 VD D GN D GN D GN D GR 1 GR 2 GR 3 GR 4 51k DIGIT 1 DIGIT 2 DIGIT 3 DIGIT 4 DIGIT 5 DIGIT 6 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG1 0 SEG1 2 段 位 LED （共阴极） 0.1uf MCU 10k SW26 SW25 SW23 SW22 SW20 SW19 SW17 SW16 SW14 SW13 SW11 SW10 SW8 SW7 SW5 SW4 SW2 SW1 S1 0 S1 2 S1 0 S1 2 KS1KS2KS3KS4KS5KS6KS7KS8KS9KS10 10k SG7 / KS7S7 10k LED cathode connection a b c d e f g h COM/DIGITAL（GRID） 共阴极的LED连接 a b c d e f g h SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 1. 连接在 GND 和 VDD 端口之间的电容（0.1µF）必须放置在离 ET6202 尽可能近的地方。 2. 建议 NC 端口（管脚 10）连接到地。 *：此电路仅供参考。