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Technical content

High Performance Stereo Audio ADC

FEATURES

  • High performance multi-bit delta-sigma audio ADC
  • 100 dB signal to noise ratio
  • -85 dB THD+N
  • 24-bit, 8 to 200 kHz sampling frequency
  • I2S/LJ master or slave serial data port
  • 256/384Fs and other non standard audio system clocks
  • Low power standby mode

APPLICATIONS

  • Soundbar
  • Audio Interface
  • Digital TV
  • A/V Receiver
  • DVR
  • NVR

ORDERING INFORMATION

ES7240S -40°C ~ +85°C TSSOP-16 BLOCK DIAGRAM ES7240S AINL AINR Multi-bit Delta-sigma Modulator Audio Data Interface DSP Clock Manager Sample Rate Detector Control Interface SDOUT SCLK LRCK MCLK M1 M0

Everest Semiconductor Confidential ES7240S Revision 8.0 2 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com

Everest Semiconductor Confidential ES7240S Revision 8.0 3 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com 1. PIN OUT AND DESCRIPTION Pin Name Pin number Input or Output Pin Description M0, M1 1, 16 I Mode selection MCLK 2 I Master clock SCLK 7 I/O Serial data bit clock LRCK 8 I/O Serial data left and right channel frame clock SDOUT 4 O Serial data output RESETb 9 I Active low chip reset (low power) AINL, AINR 10,12 I Analog left and right inputs VDDP 3 I Power supply for the digital input and output VDDD/GNDD 6, 5 I Digital power supply VDDA/GNDA 13, 14 I Analog power supply REFP 15 O Filtering capacitor connection REFQ 11 O Filtering capacitor connection ES7240S MCLK VDDP SDOUT GNDD VDDD SCLK LRCK REFP GNDA VDDA AINR REFQ AINL RESETb

Everest Semiconductor Confidential ES7240S Revision 8.0 4 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com 2. TYPICAL APPLICATION CIRCUIT CPU/DSP P VDD( + 3 V3 ) 100nF DVDD(+3V3) 100nF 1uF 1uF AGND 1uF AVDD(+3V3) 1uF 1uF LIN RI N M01 M C LK2 VD DP3 SDOUT4 GNDD5 VD DD6 SCLK7 LRCK8 RESETb9 AINL 10 REFQ 11 AINR 12 VD DA 13 GNDA 14 REFP 15 M116 ES7240S Everes t These formats are I2S (pull up resistor at SD OU T pin) and left justified (pull down resistor at SDO U T pin) P VDD( + 3 V3 ) 10K AGNDAGND AGND AGND 0RGND(SYS) For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible A dditional parallel capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help* * * In the layout, chip is treated as an analog device

Everest Semiconductor Confidential ES7240S Revision 8.0 5 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com 3. CLOCK MODES AND SAMPLING FREQUENCIES The device can work either in master clock mode or slave clock mode by setting mode control pins M1 and M0 according to Table 1. Table 1 Mode Control Pin Pin Description M1:M0 00 – master clock mode, single speed mode 01 – master clock mode, double speed mode 10 – master clock mode, quad speed mode 11 – slave clock mode, all speed modes In master mode, LRCK and SCLK are derived internally from MCLK. The available MCLK/LRCK ratios are listed in Table 2. SCLK/LRCK ratio is always 64 in master mode. Table 2 Master Mode Sampling Frequencies and MCLK/LRCK Ratio Speed Mode Sampling Frequency MCLK/LRCK Ratio Single Speed 8kHz – 50kHz 256 Double Speed 50kHz – 100kHz 128 Quad Speed 100kHz – 200kHz 64 In slave mode, LRCK and SCLK are supplied externally. LRCK and SCLK must be synchronously derived from the system clock with some specific rates. The device can auto detect MCLK /LRCK ratio according to Table 3 . The device only supports the MCLK/LRCK ratios listed in Table 3 . The SCLK/LRCK ratio is normally 64. Table 3 Slave Mode Sampling Frequencies and MCLK/LRCK Ratio Speed Mode Sampling Frequency MCLK/LRCK Ratio Single Speed 8kHz – 50kHz 256, 384, 512, 768, 1024 Double Speed 50kHz – 100kHz 128, 192 Quad Speed 100kHz – 200kHz 64 4. POWER UP AND POWER DOWN RESETb pin active low will put the device in power down mode. During power-up, RESETb pin should be hold at low level to keep the device in reset until the power supplies, clocks and mode selection pins are stable. 5. DIGITAL AUDIO INTERFACE The device provides many formats of serial audio data interface to the output f rom the ADC through LRCK, SCLK and SDOUT pins. These formats are I 2S (pull up resistor a t SDOUT pin) and left justified (pull down resistor at SDOUT pin). ADC data is out at SDOUT on the falling edge of

Everest Semiconductor Confidential ES7240S Revision 8.0 6 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com SCLK. The relationships of SDOUT (SDATA ), SCLK and LRCK with these formats are shown through Figure 1 to Figure 2. n-2 n-1 n321

1 SCLK

Figure 1 I2S Serial Audio Data Format Up To 24-bit n-2 n-1 n321 MSB LSB LEFT CHANNEL n-2 n-1 n321 MSB LSB RIGHT CHANNEL SDATA SCLK LRCK Figure 2 Left Justified Serial Audio Data Format Up To 24-bit 6. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Continuous operation at or beyond these conditions may permanently damage the device. PARAMETER MIN MAX Analog Supply Voltage Level -0.3V +5.0V Digital Supply Voltage Level -0.3V +5.0V Input Voltage Range DGND-0.3V DVDD+0.3V Operating Temperature Range -40°C +85°C Storage Temperature -65°C +150°C RECOMMENDED OPERATING CONDITIONS PARAMETER MIN TYP MAX UNIT VDDA 3.0 3.3 3.6 V VDDD 3.0 3.3 3.6 V VDDP 1.6 3.3 3.6 V ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: VDDA=3.3V, VDDD=3.3V, AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256. PARAMETER MIN TYP MAX UNIT ADC Performance Signal to Noise ratio (A-weigh) 95 100 104 dB

Everest Semiconductor Confidential ES7240S Revision 8.0 7 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com THD+N -88 -85 -75 dB Channel Separation (1KHz) 95 100 105 dB Interchannel Gain Mismatch 0.1 dB Gain Error ±5 % Filter Frequency Response – Single Speed Passband 0 0.4535 Fs Stopband 0.5465 Fs Passband Ripple ±0.05 dB Stopband Attenuation 70 dB Filter Frequency Response – Double Speed Passband 0 0.4167 Fs Stopband 0.5833 Fs Passband Ripple ±0.005 dB Stopband Attenuation 70 dB Filter Frequency Response – Quad Speed Passband 0 0.2083 Fs Stopband 0.7917 Fs Passband Ripple ±0.005 dB Stopband Attenuation 70 dB Analog Input Full Scale Input Level AVDD/3.3 Vrms Input Impedance 20 KΩ POWER CONSUMPTION CHARACTERISTICS PARAMETER MIN TYP MAX UNIT Normal Operation Mode VDDD=3.3V, VDDP=3.3V, VDDA=3.3V 30 mA Power Down Mode VDDD=3.3V, VDDP=3.3V, VDDA=3.3V 28 uA SERIAL AUDIO PORT SWITCHING SPECIFICATIONS PARAMETER Symbol MIN MAX UNIT MCLK frequency 51.2 MHz MCLK duty cycle 40 60 % LRCK frequency 200 KHz LRCK duty cycle 40 60 % SCLK frequency 26 MHz SCLK pulse width low TSCLKL 15 ns SCLK Pulse width high TSCLKH 15 ns SCLK falling to LRCK edge TSLR –10 10 ns SCLK falling to SDOUT valid TSDO 11 ns

Everest Semiconductor Confidential ES7240S Revision 8.0 8 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Figure 4 Serial Audio Port Timing

Everest Semiconductor Confidential ES7240S Revision 8.0 9 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com 7. PACKAGE

Everest Semiconductor Confidential ES7240S Revision 8.0 10 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com 8. CORPORATE INFORMATION Everest Semiconductor Co., Ltd. No. 1355 Jinjihu Drive, Suzhou Industrial Park, Jiangsu, P.R. China, Zip Code 215021 苏州工业园区金鸡湖大道 1355 号国际科技园, 邮编 215021 Email: info@everest-semi.com