ES6425

ES6425 ESS | Alldatasheet

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ESS Technology, Inc. SAM0529-091305 1 ESS Technology, Inc. ES6425 Digital Media Processor 2 Product Brief

DESCRIPTION

The ES6425 Digital Media Processor 2 (DMP2) is a high performance single-chip audio/video decoder for a wide series of applications such as networked or non- networked/flash memory media players. This second generation of Digital Media Processor has an enhanced performance engine to decode MPEG-4 video at D1 resolution with state-of-the-art progressive scan NTSC/PAL video encoder for brilliant and sharp, flicker- free output to the video display. At the heart of the ES6425 is the ESS proprietary Programmable Multimedia Processor core consisting of 32-bit RISC and 64-bit DSP processors that enable simultaneous parallel execution of system commands and specialized multimedia decoding tasks. The ES6425 includes a memory controller which interfaces to 8-bit or 16-bit DRAM with up to 128-Mb capacity. The ES6425 performs video processing to provide high- resolution display of MPEG-1, MPEG-2, and MPEG-4 videos and JPEG photos. The integrated NTSC/PAL TV- encoder provides composite, S-video, and YUV outputs. The ES6425 includes an On-Screen-Display (OSD) controller to provide a user friendly setup menu to enable or modify the various audio decoding and video display features. A CCIR656/601 digital video output port is also present. The ES6425 also performs audio processing for Wave, MP3, AAC, Dolby  Digital, and WMA playback along with a 7-band graphic equalizer. The ES6425 has a multi- channel audio serial port compliant to I 2S format for interfacing to an external audio DAC and ADC. An S/PDIF output port is also integrated for transmitting digital audio streams. A 16-bit host interface present in the ES6425 connects to many different storage solutions including Compact Flash , Smart Media, xD-Picture Card, and IDE hard drives. Similarly, a serial interface is built-in to interface to SD , xD, MultiMediaCard, and Memory Stick devices. The ES6425 is available in an industry-standard 208-pin Plastic Quad Flat Pack (PQFP) device package.

FEATURES

• Single-chip digital audio and video decoder and processor.  MPEG-4 Advanced Simple Profile* at full screen D1 video playback (playability is dependent on memory card bandwidth).  MPEG-2 video playback (playability is dependent on memory card bandwidth).  MPEG-1 video playback.  Motion JPEG playback.  JPEG photo playback.  Progressive JPEG photo playback.  MP3 music playback.  WMA music playback (Microsoft license required).  Dolby Digital decode (ES6425FDF only)  AAC audio decode and playback.  ESS Music Slideshow.  S/PDIF digital audio output.  Integrated NTSC/PAL encoder with pixel adaptive de- interlacer and five 10-bit 54 MHz video DACs.  High-quality progressive scan video output for flicker-free video display.  Simultaneous Composite, S-Video, and YUV outputs.  CCIR656/601 YUV 4:2:2 output.  On-Screen-Display controller with 3-bit blending to provide 256 colors display.  Integrated I2S serial port for up to 5.1 channel audio output and stereo input.  Direct interface for IDE devices and flash memory cards including CF, MS, MS Pro, SD, xD, MMC, and SM.  DRAM memory controller with interface to 8-bit or 16-bit SDRAM for up to 16 MB of memory.  16-bit SRAM interface for connecting to boot EPROM or flash memory.  Lead-free leads using 98%-Sn/2%-Cu or 98%-Sn/2%-Bi.

2 SAM0529-091305 ESS Technology, Inc. ES6425 PRODUCT BRIEF ES6425 PINOUT DIAGRAM ES6425 PINOUT DIAGRAM The device pinout for the ES6425 is shown in Figure 1. The pound symbol (#) denotes an active-low signal. Figure 1 ES6425 Device Pinout 100 101 102 103 104105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 LCS1# LOE# LD0 VSS LCS3# LCS2# I2CDATA/AUX0 LA21 LA20 RESET# VEE NC HIOCS16#/AUX3[4] HA1/AUX4[3] VSS HA0/AUX4[2] HWR#/AUX4[5] HRD#/AUX4[6] HD4/AUX1[4] HD5/AUX1[5] HD6/AUX1[6]/VFD_DOUT HD2/AUX1[2] HD3/AUX1[3] VEE VCC DB8 VCC DB5 DB9 DCS0# VCC VSS TSD0/SEL_PLL0 TSD1/SEL_PLL1 TDMFS TDMCLK TDMDR TDMTSC# TWS/SEL_PLL2 VEE LA4 LA5 LA6 LA7 LA8 LA9 VSS VCC LA10 LA11 LA12 LA13 LA14 LA15 LA16 VSS VEE LA17 LA18 LA19 TDMDX/RSEL VSS TSD2 SPDIF/SEL_PLL3 NC VSS MCLK TBCK VEE VEE AVSS VSS DQM RSD RWS RBCK CAMIN3 XIN XOUT AVEE DSCK VSS DB15 DB13 DB11 DB1 VSS DMBS1 DRAS# DOE#/DSCK_E N VEE DMA9 DMA7 VSS DMA5 DMA3 VEE DCS1# DB14 DB12 DB10 DB0 VEE DMBS0 DWE# DCAS# VSS DMA8 DMA6 VEE DMA4 DMA2 VSS DB7 DB6 VSS DB4 DB3 DB2 DMA11 DMA10 DMA1 DMA0 HCS3FX3#/AUX3[6] HCS1FX#/AUX3[7] VSS HIORDY/AUX3[3] VSS HD13/AUX2[5] HD12/AUX2[4] HD11/AUX2[3] HD10/AUX2[2] HD9/AUX2[1] HD8/AUX2[0]/VFD_CLK VSS HIRQ/AUX4[7] HRST#/AUX3[5] HRRQ#/AUX4[0]/CAMIN2 HWRQ#/AUX4[1] HD15/AUX2[7]/IR HD14/AUX2[6] VCC HD7/AUX1[7]/VFD_DIN HD1/AUX1[1] HD0/AUX1[0] VCC VSS HSYNC#/AUX3[0]/CAMIN7 PCLK2XSCN/CAMIN4 YUV7/PIXOUT7 YUV6/VDAC/PIXOUT6 PCLKQSCN/AUX3[2]/CAMIN5 VSYNC#/AUX3[1]/CAMIN6 YUV5/YDAC/PIXOUT5 ADVSS ADVEE YUV4/RSET/PIXOUT4 YUV3/COMP/PIXOUT3 YUV2/CDAC/PIXOUT2 YUV1/VREF/PIXOUT1 YUV0/UDAC/PIXOUT0 DCLK VEE AUX7 AUX6 VEE LD1 LD2 LA3 LD12 VEE HA2/AUX4[4] VEE VEE LD3 LD5 LD9 LD13 LWRHL# CAMIN1 I2C_CLK/AUX1 IORD#/AUX3 LD4 LD6 LD10 LD14 VSS LA0 IOW#/AUX2 AUX4 VEE LD7 LD11 LD15 VEE LA1 VSS AUX5 VSS LD8 VSS LWRLL# CAMIN0 LA2 VSS VCC LCS0#/PIXOUT_CLK VSS ES6425 Note: (*) MPEG-4 Advanced Simple Profile without hardware Q-PEL and Global Motion Compensation (GMC).

ESS Technology, Inc. SAM0529-091305 3 ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION ES6425 PIN DESCRIPTION Table 1 lists the pin descriptions for the ES6425. The pound symbol (#) denotes an active-low signal. Table 1 ES6425 Pin Description Name Pin Numbers I/O Definition VEE 92, 99, 104, 130, 148, 157, 159, 164, 183, 193, 201 P I/O power supply. 204-207 O RISC port address bus. VSS 8, 17, 26, 34, 43, 98, 103, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192, 200, 208 G Ground. VCC 9, 35, 44, 83, 121, 139, 172 I Core power supply. RESET# 24 I Reset input (active-low); (5V tolerant input). TDMDX O TDM transmit data. RSEL I LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-kΩ resistor; read during reset. TDMDR 28 I TDM receive data; (5V tolerant input). TDMCLK 29 I TDM clock; (5V tolerant input). TDMFS 30 I TDM frame sync; (5V tolerant input). TDMTSC# 31 O TDM output enable (active-low). TWS O Audio transmit frame sync. SEL_PLL2 I System and DSCK output clock frequency selection is made at the rising edge of RESET#. The matrix below lists the available clock frequencies and their respective PLL bit settings. Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset. TSD0 O Audio transmit serial data output 0. SEL_PLL0 I Pull up to VCC via 4.7-k Ω resistor for proper operation; read during reset. RSEL Selection 01 6 - b i t R O M 18 - b i t R O M SEL_PLL2 SEL_PLL1 SEL_PLL0 Clock Type 0 0 0 DCLK x 4.5 0 0 1 DCLK x 5.0 0 1 0 Bypass mode 0 1 1 DCLK x 4.0 1 0 0 DCLK x 4.25 1 0 1 DCLK x 4.75 1 1 0 DCLK x 5.5 1 1 1 DCLK x 6.0

4 SAM0529-091305 ESS Technology, Inc. ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION TSD1 O Audio transmit serial data output 1. SEL_PLL1 I Pull up to VCC via 4.7-k Ω resistor for proper operation; read during reset. TSD2 37 O Audio transmit serial data output 2. This pin must be pulled down to VSS via a 4.7-kΩ resistor for proper operation. MCLK 39 I/O Audio master clock for audio DAC. TBCK 40 I/O Audio transmit bit clock. TBCK is an input during reset and subsequently is programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4). SPDIF O S/PDIF output. SEL_PLL3 I Pull down to ground via 4.7-k Ω resistor for proper operation; read during reset. NC 38, 42 — No connect. RSD 45 I Audio receive serial data; (5V tolerant input). RWS 46 I Audio receive frame sync; (5V tolerant input). RBCK 47 I Audio receive bit clock; (5V tolerant input). CAMIN3 48 I Camera and YUV input 3. XIN 49 I 27-MHz crystal input. XOUT 50 O 27-MHz crystal output. AVEE 51 P Analog power for PLL. AVSS 52 G Analog ground for PLL. DMA[11:0] 53-58, 61-66 O DRAM address bus. DCAS# 69 O DRAM column address strobe (active-low). DOE# O DRAM output enable (active-low). DSCK_EN O DRAM clock enable. DWE# 71 O DRAM write enable (active-low). DRAS# 72 O DRAM row address strobe (active-low). DMBS0 73 O SDRAM bank select 0. DMBS1 74 O SDRAM bank select 1. DB[15:0] 77-82, 85-90, 93-96 I/O DRAM data bus. DCS[1:0]# 97,100 O SDRAM chip select (active-low). DQM 101 O Data input/output mask. DSCK 102 O Output clock to SDRAM. DCLK 105 I Clock input to PLL; (5V tolerant input). Table 1 ES6425 Pin Description (Continued) Name Pin Numbers I/O Definition

ESS Technology, Inc. SAM0529-091305 5 ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION UDAC 106 O Video DAC output: Y: Luma component for YUV and Y/C processing. C: Chrominance signal for Y/C processing. U: Chrominance component signal for YUV mode. V: Chrominance component signal for YUV mode. YUV0 O YUV pixel 0 output data. PIXOUT0 O CCIR656 output pixel 0. VREF 107 I Internal voltage reference to DAC. Bypass to ground with 0.1-µF capacitor. YUV1 O YUV pixel 1 output data. PIXOUT1 O CCIR656 output pixel 1. CDAC 108 O Chrominance signal for Y/C processing display. YUV2 O YUV pixel 2 output data. PIXOUT2 O CCIR656 output pixel 2. COMP 109 I Compensation input. Bypass to ADVEE with 0.1-µF capacitor. YUV3 O YUV pixel 3 output data. PIXOUT3 O CCIR656 output pixel 3. RSET 110 I DAC current adjustment resistor input. YUV4 O YUV pixel 4 output data. PIXOUT4 O CCIR656 output pixel 4. ADVEE 111 P Analog power. ADVSS 112 G Analog ground for video DAC. YDAC 113 O Luma component for Y/C processing display. YUV5 O YUV pixel 5 output data. PIXOUT5 O CCIR656 output pixel 5. VDAC 114 O Video DAC output. Refer to description and matrix for UDAC pin 106. YUV6 O YUV pixel 6 output data. PIXOUT6 O CCIR656 output pixel 6. Table 1 ES6425 Pin Description (Continued) Name Pin Numbers I/O Definition Value DAC V (pin 114) DAC Y (pin 113) DAC C (pin 108) DAC U (pin 106)

0 CVBS1 Y N/A C

1 CVBS1 Y CVBS2 C

3 CVBS1 N/A CVBS2 N/A

4 CVBS1 N/A N/A N/A

5 CVBS1 Y Pr Pb

7 SYNC G R B

8 CHROMA Y Pr Pb

9 CVBS1 G R B

10 CVBS1 G B R

11 SYNC G B R

12 N/A Y Pb Pr

13 CVBS1 Y Pb Pr

6 SAM0529-091305 ESS Technology, Inc. ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION YUV7 115 O YUV pixel 7 output data. PIXOUT7 O CCIR656 output pixel 7. PCLK2XSCN 116 I/O 27-MHz video pixel clock. CAMIN4 I Camera and YUV input 4. PCLKQSCN 117 O 13.5-MHz video output pixel clock. AUX3[2] I/O Aux3 data I/O; (5V tolerant input). CAMIN5 I Camera and YUV input 5 VSYNC# 118 I/O Vertical sync (active-low); (5V tolerant input). AUX3[1] I/O Aux3 data I/O; (5V tolerant input). CAMIN6 I Camera and YUV input 6. HSYNC# 119 I/O Horizontal sync (active-low); (5V tolerant input). AUX3[0] I/O Aux3 data I/O; (5V tolerant input). CAMIN7 I Camera and YUV input 7. HD[5:0] 122-127 I/O Host data bus; (5V tolerant input). AUX1[5:0] I/O Aux1 data I/O; (5V tolerant input). HD6 128 I/O Host data bus; (5V tolerant input). AUX1[6] I/O Aux1 data I/O; (5V tolerant input). VFD_DOUT O VFD data output. HD7 131 I/O Host data bus; (5V tolerant input). AUX1[7] I/O Aux1 data I/O; (5V tolerant input). VFD_DIN I VFD data input. HD8 132 I/O Host data bus; (5V tolerant input). AUX2[0] I/O Aux2 data I/O; (5V tolerant input). VFD_CLK I VFD clock. HD9 133 I/O Host data bus; (5V tolerant input). AUX2[1] I/O Aux2 data I/O; (5V tolerant input). HD10 134 I/O Host data bus; (5V tolerant input). AUX2[2] I/O Aux2 data I/O; (5V tolerant input). HD11 135 I/O Host data bus; (5V tolerant input). AUX2[3] I/O Aux2 data I/O; (5V tolerant input). HD12 136 I/O Host data bus; (5V tolerant input). AUX2[4] I/O Aux2 data I/O; (5V tolerant input). HD13 137 I/O Host data bus; (5V tolerant input). AUX2[5] I/O Aux2 data I/O; (5V tolerant input). HD14 140 I/O Host data bus; (5V tolerant input). AUX2[6] I/O Aux2 data I/O; (5V tolerant input). HD15 141 I/O Host data bus; (5V tolerant input). AUX2[7] I/O Aux2 data I/O 7; (5V tolerant input). IR I IR remote control; (5V tolerant input). HWRQ# 142 O Host write request (active-low). AUX4[1] I/O Aux4 data I/O 1; (5V tolerant input). Table 1 ES6425 Pin Description (Continued) Name Pin Numbers I/O Definition

ESS Technology, Inc. SAM0529-091305 7 ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION HRRQ# 143 O Host read request (active-low). AUX4[0] I/O Aux4 data I/O 0; (5V tolerant input). CAMIN2 I Camera and YUV input 2. HIRQ 144 O Host interrupt. AUX4[7] I/O Aux4 data I/O 7; (5V tolerant input). HRST# 145 O Host reset (active-low). AUX3[5] I/O Aux3 data I/O 5; (5V tolerant input). HIORDY 146 I Host I/O ready. AUX3[3] I/O Aux3 data I/O 3; (5V tolerant input). HWR# 149 O Host write (active-low). AUX4[5] I/O Aux4 data I/O 5; (5V tolerant input). HRD# 150 O Host read (active-low). AUX4[6] I/O Aux4 data I/O 6; (5V tolerant input). HIOCS16# 151 I Device 16 bit data transfer (active-low). AUX3[4] I/O Aux3 data I/O 4; (5V tolerant input). CAMCLK I Camera and YUV port pixel clock. HCS1FX# 152 O Host select 1 (active-low). AUX3[7] I/O Aux3 data I/O 7; (5V tolerant input). HCS3FX# 153 O Host select 3 (active-low). AUX3[6] I/O Aux3 data I/O 6; (5V tolerant input). HA[2:0] 154, 155, 158 I/O Host address bus. AUX4[4:2] I/O Aux4 data I/Os 2, 3, and 4; (5V tolerant input). AUX0 160 I/O Auxiliary port 0 (open collector); (5V tolerant input). I2CDATA I/O I 2C data I/O; (5V tolerant input). AUX1 161 I/O Auxiliary port 1 (open collector); (5V tolerant input). I2C_CLK I/O I 2C clock I/O; (5V tolerant input). IOW# 162 O I/O write strobe (LCS1) (active-low). AUX2 I/O Auxiliary port 2; (5V tolerant input). IOR# 165 O I/O read strobe (LCS1) (active-low). AUX3 I/O Auxiliary port 3; (5V tolerant input). AUX4-7 166-169 I/O Auxiliary ports 4-7; (5V tolerant input). LOE# 170 O RISC port output enable (active-low). LCS0# 173 O RISC port chip select 0 (active-low). PIXOUT_CLK O CCIR656 output pixel clock. LCS[3:1]# 174-176 O RISC port chip select [3:1] (active-low). 194-197 I/O RISC port data bus; (5V tolerant input). LWRLL# 198 O RISC port low-byte write enable (active-low). LWRHL# 199 O RISC port high-byte write enable (active-low). CAMIN0 202 I Camera and YUV input 0. CAMIN1 203 I Camera and YUV input 1. Table 1 ES6425 Pin Description (Continued) Name Pin Numbers I/O Definition

8 http://www.esstech.com © 2005 ESS Technology, Inc. SAM0529-091305 ES6425 PRODUCT BRIEF SYSTEM BLOCK DIAGRAM No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications are subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. U.S. patents pending. MPEG is the Moving Picture Experts Group of the ISO/IEC. References to MPEG in this document refer to the ISO/IEC JTC1 SC29 committee draft ISO 11172 dated January 9, 1992. Vibratto, SmartBright, SmartLogo, SmartColor, and Music Slideshow are trademarks of ESS Technology, Inc. Dolby is a trademark of Dolby Laboratories, Inc. Trusurround, Trusurround XT, SRS, and (o) symbol are trademarks of SRS Labs., Inc. All other trademarks are trademarks of their respective companies and are used for identification purposes only. ESS Technology, Inc. 48401 Fremont Blvd. Fremont, CA 94538 Tel: (510) 492-1088 Fax: (510) 492-1898 SYSTEM BLOCK DIAGRAM A sample system block diagram for the ES6425 board design is shown in Figure 2. Figure 2 ES645 System Block Diagram

ORDERING INFORMATION

(4/16 MB) Audio DAC Speakers EEPROM IR Remote Video IDE HDD Memory Cards ROM/Flash (1 MB) DMP2 ES6425 A/V ReceiverS/PDIF AudioADC Part Number Description Package ES6425FF Digital Media Processor 2 with lead-free leads. 208-pin PQFP ES6425FDF Digital Media Processor 2 with Dolby Digital support and lead-free leads. 208-pin PQFP The letter F at the end of the part number identifies the package type PQFP . The second letter F at the end of the part number indicates lead-free leads with the device.