ES4318

ES4318 ESS | Alldatasheet

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Technical content

ESS Technology, Inc. SAM0377-052101 1 ES4318 DVD Processor Product Brief

DESCRIPTION

The ES4318 Digital Video Disc (DVD) processor is a single-chip solution for a DVD player that integrates MPEG video decoding, DVD system navigation, Content Scrambling System (CSS), and Dolby™ Digital (AC-3) and MPEG audio decoding. The fully programmable ES4318 is based on a proprietary ESS architecture. It offers the best feature set in comparison to any currently existing DVD chip, and a glueless interface to various peripheral components. The ES4318 is the most cost effective solution in its class with an integration level and quality that set new benchmarks. The ES4318 processor is capable of decoding Dolby™ Digital (AC-3) or DTS digital surround, simultaneously with MPEG-1 or MPEG-2 video. For embedded applications, the ES4318’s internal RISC processor can be used in place of a microcontroller to provide all system control, DVD system navigation, CSS decryption, and many other features. On-chip, multi-tap filters provide arbitrary scaling with state of the art SmartScale™ technology useful for video standards conversion. SmartStream™ technology from ESS provides video error concealment and video post-processing, leading to the highest playability and video quality. Other features included in the ES4318 are video letterbox display, DVD Sub-Picture overlay, and On-Screen Display. The ES4318 provides a glueless 8/16-bit parallel interface to most DVD servo/loaders. It connects directly with 8/16-bit ROM and 16-bit SDRAM/EDO. An 8-bit YUV video interface supports many TV encoders. General purpose auxiliary pins are provided to control various peripheral devices. A standard I 2S interface supports popular audio DACs and ADCs. The ES4318 also features a direct S/PDIF output. A block diagram of a typical stand-alone system using the ES4318 with the glueless SDRAM interface appears below. The DVD system stream from a DVD disc is passed to the ES4318 through the 8-bit/16-bit parallel host interface. The ES4318 parses the system layer and demultiplexes the audio and video streams. Audio is decoded and passed through the I audio serial bus to an external audio DAC and then to the speakers. Video is decoded and output as YUV pixels to an NTSC or PAL video encoder. System control and housekeeping functions (keypad and remote control) are also provided on-chip.

FEATURES

• Single-chip DVD video decoder in a 208-pin PQFP package
• MPEG-1 system and MPEG-2 program streams parsing supported
• Programmable multimedia processor architecture
• Compatible with Audio CD, VideoCD, VCD 3.0, and Super VideoCD (SVCD)
• DVD Navigation 1
• Built-in Content Scrambling System (CSS) circuitry Video
• Pan & Scan and Letter-Box conversions
• Trick modes include Slow, Fast Forward, Fast Reverse, Step, and Goto
• Sub-Picture decoder supports karaoke/subtitling functions
• 4-bit On-Screen Display (OSD) with 4-bit blending
• 8-bit YUV component video output Audio
• Built-in Karaoke key-shift function
• Dolby™ Digital 2-channel downmix audio output for Dolby™
• Dolby Pro Logic
• Linear PCM streams for 24 bit/96KHz
• Concurrent S/PDIF out and 2-channel audio output
• Sensaura Dolby Digital Virtual Suround
• DTS Digital Surround 2-channel downmix stereo output
• S/PDIF output for encoded AC-3, DTS Digital output or Linear PCM Peripheral
• Glueless interface to DVD loaders (ATAPI or A/V bus I/F)
• Bidirectional I2S audio interface
• Direct servo/loader interface
• 8 general-purpose auxiliary ports
• Single 27 MHz clock input Smart Technology
• SmartZoom™ for motion zoom and pan
• SmartScale™ for NTSC to PAL conversion and vice versa
• SmartStream™ for video error concealment; supports Microsoft Windows™ Sound System BLOCK DIAGRAM ES4318 2MByte SDRAM DVD drive EPROM Panel Interface NTSC/PAL Encoder Audio CODEC TV MIC Speakers Remote Control/ Keypad Video Audio

2 SAM0377-052101 ESS Technology, Inc. ES4318 PRODUCT BRIEF PINOUT Figure 1 ES4318 Device Pinout PIN DESCRIPTION 100 101 102 103 104105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 LCS1# LOE# LD0 VSS LCS3# LCS2# AUX0 LA21 LA20 RESET# VCC NC HIOCS16# HA1 VSS HA0 HWR#/DCI_CLK HRD#/DCI_ACK# HD4/DCI4 HD5/DCI5 HD6/DCI6 HD2/DCI2 HD3/DCI3 VCC VCC DB8 VCC DB5 DB9 DCS0# VCC VSS TSD/SEL_PLL0 SEL_PLL2 TDMFS TDMCLK TDMDR TDMTSC# TWS/SEL_PLL1 VCC LA4 LA5 LA6 LA7 LA8 LA9 VSS VCC LA10 LA11 LA12 LA13 LA14 LA15 LA16 VSS VCC LA17 LA18 LA19 TDMDX/RSEL VSS NC SPDIF_DOBM NC VSS MCLK TBCK VCC VCC VSS VSS DQM RSD RWS RBCK APLLCAP XIN XOUT VCC DSCK VSS DB15 DB13 DB11 DB1 VSS DRAS2# DRAS0# DOE#/DSCK_EN VCC DMA9 DMA7 VSS DMA5 DMA3 VCC DCS1# DB14 DB12 DB10 DB0 VCC DRAS1# DWE# DCAS# VSS DMA8 DMA6 VCC DMA4 DMA2 VSS DB7 DB6 VSS DB4 DB3 DB2 DMA11 DMA10 DMA1 DMA0 HCS3FX# HCS1FX# VSS HIORDY VSS HD13 HD12 HD11 HD10 HD9 HD8/DCI_FDS# VSS HIRQ/DCI_ERR# HRST# HRDQ# HWRQ#/DCI_REQ# HD15 HD14 VCC HD7/DCI7 HD1/DCI1 HD0/DCI0 VCC VSS HSYNCH# PCLK2XSCN YUV7 YUV6 PCLKQSCN VSYNCH# YUV5 VSS VCC YUV4 YUV3 YUV2 YUV1 YUV0 DCLK VCC AUX7 AUX6 VCC LD1 LD2 LA3 LD12 VCC HA2 VPP VCC LD3 LD5 LD9 LD13 LWRHL# NC AUX1 AUX3 LD4 LD6 LD10 LD14 VSS LA0 AUX2 AUX4 VCC LD7 LD11 LD15 VCC LA1 VSS AUX5 VSS LD8 VSS LWRLL# NC LA2 VSS VCC LCS0# VSS 208-Pin PQFP Package ES4318 Name Number I/O Definition VCC 1, 9, 18, 27, 35, 44, 51, 59, 68, 75, 83, 92, 99, 104, 111, 121, 130, 139, 148, 157, 164, 172, 183, 193, 201 I 3.65 V ± 150 mv. LA[21:0] 23:19,16:10,7:2,207:204 O Device address output. 38,147,156,163,171,177,184,192,200,208 I Ground. RESET# 24 I Reset input, active low.

ESS Technology, Inc. SAM0377-052101 3 ES4318 PRODUCT BRIEF TDMDX O TDM transmit data. RSEL I ROM Select TDMDR 28 I TDM receive data. TDMCLK 29 I TDM clock input. TDMFS 30 I TDM frame synch. TDMTSC# 31 O TDM output enable, active low. TWS 32 O Audio transmit frame sync. SEL_PLL1 I Select PLL1. TSD O Audio transmit serial data port. SEL_PLL0 I Select PLL0. SEL_PLL2 36 Select PLL2. See the table for pin number 33. MCLK 39 I/O Audio master clock for audio DAC. TBCK 40 I/O Audio transmit bit clock. SPDIF_DOBM 41 O S/PDIF (IEC958) Format Output. RSD 45 I Audio receive serial data. RWS 46 I Audio receive frame synch. RBCK 47 I Audio receive bit clock. APLLCAP 48 I Analog PLL Capacitor. XIN 49 I Crystal input. XOUT 50 O Crystal output. DMA[11:0] 66:61,58:53 O DRAM address bus. DCAS# 69 O Column address strobe, active low. DOE# 70 O Output enable, active low. DSCK_EN I Clock Enable, active low. DWE# 71 O DRAM write enable, active low. DRAS[2:0]# 74:72 O Row address strobe, active low. DB[15:0] 96:93,90:85,82:77 I/O DRAM data bus. DCS[1:0]# 97,100 O SDRAM chip select [1:0], active low. DQM 101 O Data input/output mask. DSCK 102 O Clock to SDRAM. DCLK 105 I Clock Input (27 MHz) YUV[7:0] 115:113,110:106 O 8-bit YUV output. PCLK2XSCN 116 I/O 2X pixel clock. PCLKQSCN 117 I/O Pixel clock. VSYNCH# 118 I/O Vertical sync for screen video interface, programmable for rising or falling edge, active low. HSYNCH# 119 I/O Horizontal sync for screen video interface, programmable for rising or falling edge, active low. HD[15:0] 141:140,137:131,128:122 O Host data bus HCS1FX# 152 O Host select 1. HCS3FX# 153 O Host select 3. HIOCS16# 151 I Device 16-bit data transfer. HA[2:0] 158, 155:154 I/O Host address bus. VPP 159 I Peripheral protection voltage. HWR#/DCI_ACK# 149 I,I Host write/DCI Interface Acknowledge Signal, active low. HRD#/DCI_CLK 150 I,I Host read/DCI Interface Clock. HD[15:0] 141:140,137:131,128:122 I/O Host data bus. HWRQ# 142 O Host write request. HRDQ# 143 O Host read request. HIRQ 144 I/O Host interrupt. HRST# 145 O Host reset. HIORDY 146 I Host I/O ready. HWR# 149 O Host write request. AUX[7:0] 169:165,162:160 I/O Auxiliary ports. LOE# 170 O Device output enable, active low. LCS[3:0]# 176:173 O Chip select [3:0], active low. LD[15:0] 197:194, 191:185, 182:178 I/O Device data bus. LWRLL# 198 O Device write enable, active low. LWRHL# 199 O Device write enable, active low. NC 37,38,42,203:202 No connect. Name Number I/O Definition RSEL Selection 01 6 - b i t R O M 1 8-bit ROM SEL_PLL2 SEL_PLL0 Clock Output 0 0 2.5 x DCLK 01 3 x D C L K 1 0 3.5 x DCLK 11 4 x D C L K

4 © 2000—2001 ESS Technology, Inc. All rights reserved. SAM0377-052101 ES4318 PRODUCT BRIEF No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications are subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. (P) U.S. Patent 4,214,125 and others, other patents pending. VideoDrive TM is a trademark of ESS Technology, Inc. MPEG is the Moving Picture Experts Group of the ISO/ IEC. All other trademarks are owned by their respective holders and are used for identification purposes only.

ORDERING INFORMATION

Part Number Description Package ES4318 DVD Processor 208-pin TQFP see detail A EE1E3 15 2 157 208 Index 104 D 105 Pin 1 Note: 1. All dimensions are in inches (millimeter). 2. Actual package used has millimeter native dimensions – take care with rounding from metric to imperial. Symbol Min Nom Max A –– 0 . 1 6 5 A1 0.010 (0.25) A2 0.130 (3.30) 0.134 (3.40) 0.138 (3.50) B0 . 0 0 7 (0.18) 0.009 (0.23) 0.011 (0.28) C0 . 0 0 5 (0.12) 0.006 (0.16) 0.008 (0.20) D1 . 1 9 5 (30.35) 1.205 (30.60) 1.215 (30.85) D1 1.098 (27.90) 1.102 (28.00) 1.106 (28.10) D3 1.004 (25.50) REF e 0.0197 (0.50) BASIC E1 . 1 9 5 (30.35) 1.205 (30.60) 1.215 (30.85) E1 1.098 (27.90) 1.102 (28.00) 1.106 (28.10) e L C B 156 φ