ES1021QI ALTERA | Alldatasheet

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Technical content

Features

 Enables Arbitrary Turn-on and Turn-off Sequencing of Up to Four Power Supplies (0.7V to 5V)  Operates From 1.5V to 5V Supply Voltage  Supplies VDD +5.3V of Charge Pumped Gate Drive  Adjustable Voltage Slew Rate for Each Rail  Multiple Sequencers Can be Daisy-Chained to Sequence an Infinite Number of Independent Supplies  Glitch Immunity  Undervoltage Lockout for Each Supply  Active Low ENABLE Input  Dual Channel Groupings  QFN Package  Pb-free (RoHS-compliant)

Applications

G r a p h i c s C a r d s  FPGA/ASIC/Microprocessor/PowerPC Supply Sequencing N e t w o r k R o u t e r s  Telecommunications Systems FIGURE 1. TYPICAL ES1021QI APPLICATION FIGURE 2. ES1021QI GROUP INDEPENDENT TURN-OFF AND DELAY

10128 July 9, 2014 Rev A

Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 2014 Altera Corporation

Ordering Information

(Notes 1, 2) PART MARKING TEMP . RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ES1021QI S1021 -40 to +85 24 Ld 4x4 QFN L24.4x4 NOTES: 1. Add “T” suffix for Tape and Reel. Please refer to Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing- and-marking.html 2. These Altera Enpirion Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FIGURE 3. ES1021QI BLOCK DIAGRAM

Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 2014 Altera Corporation Pin Configurations ES1021QI (24 LD QFN) TOP VIEW 24 23 22 21 20 19 7 8 9 10 11 12 EPAD ENABLE_1 GATE_A DLY_OFF_C DLY_OFF_D GATE_B GATE_C GATE_D DLY_ON_B RESET_2 GND UVLO_B DLY_OFF_B UVLO_D DLY_ON_D DLY_ON_C UVLO_C DLY_OFF_A NC UVLO_A DLY_ON_A NC VDD RESET (GND) ENABLE_2

Enpirion Power Datasheet ES1021QI Power Sequencing ControllerJuly 2014 Altera Corporation Pin Descriptions PIN NAME PIN NUMBER DESCRIPTION VDD 23 Chip Bias. Bias IC from nominal 1.5V to 5V. GND 10 Bias Return. IC ground. ENABLE_1 1 Input to start on/off sequencing. Input to initiate start of programmed sequencing of supp lies on or off. Enable functionali ty disabled for 10ms after UVLO is satisfied. ES1021QI has two ENABLE inputs; one for each 2-channel grouping. ENABLE _1 is for (A, B), and ENABLE_2 is for (C, D).ENABLE_2 11 RESET 24 RESET Output. RESET provides low signal 150ms after all GA TEs are fully enhanced. Delay is for stabilization of output voltages. RESET asserts low upon UVLO not being satisfied or ENABLE being deasserted. RESET outputs are open-drain, N-channel FET and are guaranteed to be in correct state for VDD down to 1V and ar e filtered to ignore fast tr ansients on VDD and UVLO_X. RESET_2 only exists for (C, D) group I/O. RESET_2 9 UVLO_A 20 Undervoltage Lockout/Monitoring Input. Provides a programma ble UV lockout referenced to an internal 0.633V reference. F iltered to ignore short (<30µs) transients belo w programmed UVLO level.UVLO_B 12 UVLO_C 17 UVLO_D 14 DLY_ON_A 21 Gate On Delay Timer Output. Allows programming of de lay and sequence for VOUT turn- on using a capacitor to ground. Ea ch capacitor charged with 1µA 10ms after turn-on initiated by ENABLE/ENABLE . Internal current source provides delay to associated FET GATE turn-on.DLY_ON_B 8 DLY_ON_C 16 DLY_ON_D 15 DLY_OFF_A 18 Gate Off Delay Timer Output. Allows programming of delay and sequence for VOUT turn-off through ENABLE/ENABLE via a capacitor to ground. Each capacitor charged with 1µA internal cu rrent source to an internal reference voltage, causing corresponding gate to be pull ed down, thus turning off FET. DLY_OFF_B 13 DLY_OFF_C 3 DLY_OFF_D 4 GATE_A 2 FET Gate Drive Output. Drives external FETs with 1µA current source to soft-start ramp into load. GATE_B 5 GATE_C 6 GATE_D 7 GND EPAD Ground. Die Substr ate. Can be left floating. NC 19, 22 No Connect ES1021QI Feature Matrix PART NAME EN/EN CMOS/ TTL GATE DRIVE OR OPEN DRAIN OUTPUTS REQUIRED CONDITIONS FOR INITIAL START-UP NUMBER OF UVLO INPUTS MONITORED BY EACH RESET NUMBER OF CHANNELS THAT TURN OFF WHEN ONE UVLO FAULTS PRESET OR ADJUSTABLE SEQUENCE NUMBER OF UVLO AND PAIRS OF I/O FEATURES ES1021QI EN CMOS Gate Drive 4 UVLO 2 EN

2 UVLO 2 Gates Preset 2 Monitors

Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 2014 Altera Corporation Absolute Maximum Ratings (Note 5) Thermal Information Operating Conditions Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

24 Ld 4x4 QFN Package (Notes 3, 4) 46 8

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposu re to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. NOTES: 3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. 4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 5. All voltages are relative to GND, unless otherwise specified. Electrical Specifications VDD = 1.5V to +5V , TA = TJ = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT UVLO Falling Undervoltage Lockout Threshold VUVLOvth TJ = +25°C 619 633 647 mV Undervoltage Lockout Threshold Tempco TCUVLOvth 40 µV/°C Undervoltage Lockout Hysteresis VUVLOhys 10 mV Undervoltage Lockout Threshold Range RUVLOvth Max V UVLOvth- Min VUVLOvth 7m V Undervoltage Lockout Delay TUVLOdel ENABLE satisfied 10 ms Transient Filter Duration tFIL VDD, UVLO, ENABLE glitch filter 30 µs DELAY ON/OFF Delay Charging Current DLY_ichg V DLY = 0V 0.92 1 1.08 µA Delay Charging Current Range DLY_ichg_r DLY_ichg(max) - DLY_ichg(min) 0.08 µA Delay Charging Current Temperature Coefficient TC_DLY_ichg 0.2 nA/°C Delay Threshold Voltage DLY_Vth 1.238 1.266 1.294 V Delay Threshold Voltage Temperature Coefficient TC_DLY_Vth 0.2 mV/°C ENABLE, RESET ENABLE Threshold VENh 0.5 VDD V ENABLE Hysteresis VENh -VENl Measured at VDD = 1.5V 0.2 V ENABLE Lockout Delay tdelEN_LO UVLO satisfied 10 ms ENABLE Input Capacitance Cin_en 5 pF RESET Pull-up Voltage Vpu_rst VDD V RESET Pull-Down Current IRSTpd1 VDD = 1.5V , RST = 0.1V 5m A IRSTpd3 VDD = 3.3V , RST = 0.1V 13 mA IRSTpd5 VDD = 5V , RST = 0.1V 17 mA RESET Delay after GATE High TRSTdel GATE = VDD+5V 160 ms

Enpirion Power Datasheet ES1021QI Power Sequencing ControllerJuly 2014 Altera Corporation Descriptions and Operation The ES1021QI sequencer is a 4-channel voltage sequencing controller, and is designed for use in multiple-voltage systems requiring power sequencing of various supply volt ages. Individual voltage rails are gated on and off by external N-Channel MOSFETs, the gates of which are driven by an internal charge pump to V DD + 5.3V (VQP) in a user-programmed sequence. The ES1021QI is a 4-channel device that groups the four ch annels into two groups of two channels each. Each group of A, B and C, D, has its own ENABLE and RESET I/O pins. All four UVLO and both ENABLEs must be satisfied for sequencing to start. The A, B group turns on first, 10ms after the second ENABLE is pulled low, with A then B turning on, followed by C then D. Once the preceding GATE = VQP , the next DLY_ON pin starts to charge its capacitor; thus, all four GATEs turn on. Approximately 160ms after D GATE = VQP , the RESET output is released to go high. Once any UVLO is unsatisfied, only the related group’s RESET and two GATEs are pulled low. The related EN input must be cycled for the faulted group to be turned on again. Normal shutdown is invoked by signaling both ENABLE inputs high, which causes the two related GATEs to shut down in reverse order from turn-on. DLY_X capacitors adjust the delay between GATES during turn-on and turn-off, but not the order. During bias up, the RESET output is guaranteed to be in the correct state, with VDD lower than 1V . ES1021QI requires that the related ENABLE be cycled for restart of its associated group GATEs. If no capacitors are connected between DLY_ON or DLY_OFF pins and ground, then all such related GATEs start to turn on immediately after the 10ms (TUVLOdel) ENABLE stabilization timeout has expired. The GATEs start to turn off immediately when ENABLE is asserted. RESET Output Low VRSTl Measured at VDD = 5V with 5k pull-up resistors 0.1 V RESET Output Capacitance C OUT_RST 10 pF GATE GATE Turn-On Current IGATEon GATE = 0V 0.8 1.1 1.4 µA GATE Turn-Off Current I GATEoff_l GATE = VDD, Disabled -1.4 -1.05 -0.8 µA GATE Current Range I GATE_range Within IC IGATE max-min 0.35 µA GATE Turn-On/Off Current Temperature Coefficient TC_I GATE 0.2 nA/°C GATE Pull-Down High Current IGATEoff_h GATE = VDD, UVLO = 0V 88 mA GATE High Voltage VGATEh VDD < 2V, TJ = +25°C VDD + 4.9V V VGATEh VDD > 2V VDD + 5V VDD + 5.3V V GATE Low Voltage VGATEl Gate Low Voltage, VDD = 1V 0 0.1 V BIAS IC Supply Current IVDD_5V VDD = 5V 0.20 0.5 mA IVDD_3.3V VDD = 3.3V 0.14 mA IVDD_1.5V VDD = 1.5V 0.10 mA VDD Power-on Reset VDD_POR 1 V NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +2 5°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Electrical Specifications VDD = 1.5V to +5V , TA = TJ = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT

by the number of common DLY_X pins to obtain the desired timing. lockout delay for a sequence-off, so this table illustrates the delay to GATE transition from a disable signal. TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD NOTE: Nom. T DEL_SEQ = Capacitor (µF)*1.3MW.

FIGURE 4. UVLO THRESHOLD VOLTAGE FIGURE 5. DLY CHARGE CURRENT FIGURE 6. ES1021QI GROUP INDEPENDENT TURN-OFF AND DELAY

19 R9 DNP

FIGURE 7. ES1021QI SCHEMATIC

In any system there are variance contributors. For ES1021QI, timing errors are mainly contributed by three sources. FIGURE 8. CAPACITOR TIMING MISMATCH

by these factors is insignificant, since both DLY_X traces overlay each other. FIGURE 9. DLY_VTH AND DLY_ICHG TIMING MISMATCH

Enpirion Power Datasheet ES1021QI Power Sequencing ControllerJuly 2014 Altera Corporation

Revision History

The table lists the revision history for this document. DATE REVISION CHANGE July, 2014 1.0 Initial Release.

Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 2014 Altera Corporation Package Outline Drawing L24.4x4

24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 4, 10/06 0 . 90 ± 0 . 1 5C 0 . 2 REF TYPICAL RECOMMENDED LAND PATTERN 0 . 05 MAX.( 24X 0 . 6 ) DETAIL "X" ( 24X 0 . 25 ) 0 . 00 MIN. ( 20X 0 . 5 ) ( 2 . 10 ) SIDE VIEW ( 3 . 8 TYP ) BASE PLANE TOP VIEW BOTTOM VIEW 712 24X 0 . 4 ± 0 . 1 4.00 PIN 1 18INDEX AREA 2419 4.00 2.5 0.5020X SEE DETAIL "X" - 0 . 05 + 0 . 0724X 0 . 23 2 . 10 ± 0 . 15 PIN #1 CORNER (C 0 . 25) SEATING PLANE 0.08 C 0.10 C C

0.10 M C A B

A B (4X) 0.15 located within the zone indicated. The pin #1 identifier may be Unless otherwise specified, tolerance : Decimal ± 0.05 Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. Dimension b applies to the metallized terminal and is measured Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. either a mold or mark feature. Dimensions are in millimeters.1. NOTES: