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Document overview

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Technical content

Features

  • Hot-swap Single Power Distribution Control for +12V
  • Overcurrent Fault Isolation
  • Programmable Current Regulation Level
  • Programmable Current Regul ation Time to Latch-Off
  • Rail-to-Rail Common Mode Input V oltage Range
  • Enhanced Internal Charge Pump Drives N-Channel MOSFET gate to 6.5V above IC bias.
  • Undervoltage and Overcu rrent Latch Indicators
  • Adjustable Turn-On Ramp
  • Protection During Turn-On
  • Two Levels of Overcurrent Detection Provide Fast Response to Varying Fault Conditions
  • 1µs Response Time to Dead Short
  • Pb-Free (RoHS Compliant)

Applications

  • FPGA, DSP, and ASIC power protection
  • Power Distribution Control
  • Hot Plug Components and Circuitry Application Circuits - High Side Controller +12V EN LOAD POK OC ES1010SI +V SUPPLY TO BE CONTROLLED

09617 March 14, 2014 Rev A

ES1010SI 12V Hot-Swap Power Distribution Controllers March 2014 Altera Corporation

Ordering Information

(8 LD SOIC) TOP VIEW PART NUMBER (Notes 1, 3) PART MARKING TEMPERATURE RANGE (°C) PACKAGE (Pb-free) PKG . DWG . # ES1010SI 1010 -40 to +85 8 Ld SOIC M8.15 EVB-ES1010SI Evaluation Platform NOTES: 1. These Altera Enpirion Pb-free plastic p ackaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.. Pin Descriptions PIN NO. SYMBOL FUNCTION DESCRIPTION 1 ISET- Current Set Connect to the low side of the current sense resistor through the current limiting set resistor. This pin functions as the current limit programming pin. 2 ISEN+ Current Sense Connect to the more positive end of sense resistor to measure the voltage drop across this resistor.

3 GATE External FET Gate Drive

Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to VIN +6.5V by an 14µA current source.

4 GND Chip Return

5 VIN Chip Supply 12V chip supply. This can be either connected directly to the +12V rail supplying the switched load voltage or to a dedicated GND +12V supply.

6 CLTIM Current Limit Timing

Connect a capacitor from this pin to ground. This capacitor determines the time delay between an overcurrent event and chip output shutdown (current limit time-out). The duration of current limit time-out is equal to 93k x CLTIM. 7 POK Power Good Indicator Indicates that the voltage on the ISEN+ pin is satisfactory. POK is driven by an open drain N-Channel MOSFET and is pulled low when the output voltage (VISEN+) is less than the UV level for the particular IC. 8 EN Power-ON EN is used to control and reset the chip. The chip is enabled when EN pin is driven high to a maximum of 5V or is left open. Do not drive this input >5V . After a current limit time-out, the chip is reset by a low level signal applied to this pin. This input has 20µA pull-up capability. ISET- ISEN+ GATE GND EN POK CLTIM VIN

ES1010SI 12V Hot-Swap Power Distribution ControllersMarch 2014 Altera Corporation Absolute Maximum Ratings TA = +25°C Thermal Information Operating Conditions ESD Thermal Resistance (Typical, Note 2) JA (°C/W) CAUTION: Do not operate at or near the ma ximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. NOTES: 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. 3. All voltages are relative to GND, unless otherwise specified. Electrical Specifications VIN = 12V, TA = TJ = full temperature range, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 4) TYP MAX (Note 4) UNITS CURRENT CONTROL ISET- Current Source I ISET_ft 17 20 22 µA ISET- Current Source I ISET_pt TJ = +15°C to +55°C 19 20 21 µA Current Limit Amp Offset V oltage Vio_ft V ISET- - VISEN+ -4.5 0 4.5 mV Current Limit Amp Offset V oltage Vio_pt V ISET- - VISEN+, TJ = +15°C to +55°C -2 0 2 mV GATE DRIVE GATE Response Time to Severe OC pd_woc_amp V GATE to 10.8V - 100 - ns GATE Response Time to Overcurrent pd_oc_amp V GATE to 10.8V - 600 - ns GATE Turn-On Current I GATE VGATE to = 6V 10.8 14 16.7 µA GATE Pull-Down Current OC_GATE_I_4V Overcurrent 45 82 124 mA GATE Pull-Down Current (Note 4) WOC_GATE_I_4V Severe Overcurrent - 0.8 - A Undervoltage Threshold 12V UV_VTH 8.9 9.6 10.2 V GATE High V oltage 12VG GATE V oltage VIN + 5.7V VIN + 6.5V - V BIAS VIN Supply Current IVIN - 3 3.9 mA VIN POR Rising Threshold VIN_POR_L2H VIN Low to High 7 8.4 9 V VIN POR Falling Threshold VIN_POR_H2L VIN High to Low 6.9 8.1 8.7 V VIN POR Threshold Hysteresis VIN_POR_HYS VIN_POR_L2H - VIN_POR_H2L 0.1 0.3 0.5 V Maximum EN Pull-Up V oltage PWRN_PUV Maximum Exte rnal Pull-up V oltage - 5 - V

ES1010SI 12V Hot-Swap Power Distribution Controllers March 2014 Altera Corporation Simplified Block Diagram Description and Operation The ES1010SI is targeted for +12V single power supply distribution control for generic hot swap switching applications. This ICs features a highly accurate programmable current regulation (CR) level with programmable time delay to latch-off, and programmable soft-start turn-on ramp all set with a minimum of external passive components. It also includes severe OC protection EN Pull-Up V oltage VEN EN Pin Open 2.5 3.2 - V EN Rising Threshold V EN_THR 1.1 1.7 2.35 V EN Hysteresis EN_HYS 125 170 250 mV EN Pull-Up Current I EN 12.6 17 24 µA CURRENT REGULATION DURATION/POWER GOOD CCLTIM Charging Current C CLTIM_ichg0 V CLTIM = 0V 17.2 20.5 25 µA CCLTIM Fault Pull-Up Current (Note 4) -2 0 - mA Current Limit Time-Out Threshold V oltage CCLTIM_Vth CLTIM V oltage 1.6 1.8 2.1 V Power Good Pull Down Current PG_Ipd V OUT = 0.5V - 8 - mA NOTES: 4. Parameters with MIN and/or MAX limits ar e 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Electrical Specifications VIN = 12V, TA = TJ = full temperature range, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 4) TYP MAX (Note 4) UNITS ISET- ISEN+ GATE GND VIN CLTIM POK EN CLIM WOCLIM ENABLE OC 10µA FALLING EDGE DELAY 18V VREF 1.86V 12V R R S QN Q ENABLE POR VIN RISING EDGE PULSE UV 18V 20µA 7.5k 20µA UV DISABLE

feature is enabled once the IC is biased, monitoring and reporting any UV condition on the ISEN+ pin. N-Channel MOSFET to the programmed current regulation level; this is the start of the time-out period. See Figures 2 through 13 for graphs and waveforms related to text. The IC is reset after an OC latch-off condition by a low level on the EN pin and is turned on by the EN pin being driven high. Design applications where the CR Vth is set extremely low (25mV or less), there is a two-fold risk to consider.

  • There is the susceptibility to noise influencing the absolute CR Vth value. This can be addressed with a 100pF capacitor across the RSENSE resistor.
  • Due to common mode limitations of the overcurrent comparator, the voltage on the ISET- pin must be 20mV above the IC ground either initially (from ISET-*RSET) or before CCLTIM reaches time-out (from gate charge-up). If this does not happen, the IC may incorrectly report overcurrent fault at start-up when there is no fault. Circuits with high load capacitance and initially low load current are susceptible to this type of unexpected behavior. Do not signal nor pull-up the EN input to > 5V . Exceeding 6V on this pin will cause the internal charge pump to malfunction.

TABLE 1. R ISET- PROGRAMMING RESISTOR V ALUE NOTE: Nominal Vth = R ISET- x 20µA. TABLE 2. C CLTIM CAPACITOR V ALUE NOTE: Nominal time-out period = C CLTIM x 93k.

internal power dissipation. Refer to the MOSFET SOA information in the manufacturer’s data sheet. time may offer the best application solution relative to reliability and FET MTF. between the RSENSE resistors and the IC is as direct and as short as possible with zero current in the sense lines (see Figure 1). FIGURE 1. SENSE RESISTOR PCB LAYOUT

FIGURE 2. V IN BIAS CURRENT FIGURE 3. I SET- SOURCE CURRENT FIGURE 4. C CLTIM CURRENT SOURCE FIGURE 5. C CLTIM OC VOLTAGE THRESHOLD FIGURE 6. UV THRESHOLD FIGURE 7. GATE CHARGE CURRENT

FIGURE 8. POWER-ON RESET VOLTAGE THRESHOLD FIGURE 9. GATE VOLTAGE vs BIAS and TEMPERATURE FIGURE 10. ES1010SI TURN-ON FIGURE 11. ES1010SI TURN-OFF

pulls high internally enabling the ES1010SI if not driven low via EN test point or J2. of 2.5~A. The 0.01µF delay time to latch-off capacitor results in a nominal 1ms before latch-off of output after an OC event. the provided FET is rated for a much higher current. FIGURE 12. IOC REGULATION and TURN-OFF FIGURE 13. WOC TURN-OFF and RESTART FIGURE 14. EVB-ES1010SI HIGH SIDE SWITCH APPLICATION

The table lists the revision history for this document. TABLE 3. BILL OF MATERIALS, EVB-ES1010SI J1 Bias V oltage Selection Jumper Install if switched rail voltage is = +12V . J2 EN Disable Install J2 to disable U2. Connects EN to GND. March 2014 1.0 Initial release.

ES1010SI 12V Hot-Swap Power Distribution ControllersMarch 2014 Altera Corporation Small Outline Plastic Packages (SOIC) INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Pub- lication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs sh all not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. C onverted inch dimensions are not necessarily exact. M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N8 8 7 a 0° 8° 0° 8° - Rev. 1 6/05