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Technical content

Features

 Buck mode: input voltage range 3V to 36V (refer to “Input Voltage” on page 16 for more details)  Boost mode expands operating input voltage lower than 2.5V (refer to “Input Voltage” on page 16 for more details)  Selectable forced PWM mode or LLM mode  300µA IC quiescent current (LLM, no load); 180µA input quiescent current (LLM, no load, VOUT tied to AVIN)  Less than 5µA (MAX) shutdown input current (IC disabled)  Operational topologies - Synchronous buck - Non-synchronous buck - Two-stage boost buck - Non-inverting single inductor buck boost  Programmable frequency from 200kHz to 2.2MHz and frequency synchronization capability  ±1% tight voltage regulation accuracy  Reliable overcurrent protection - Temperature compensated current sense - Cycle-by-cycle current limiting with frequency foldback - Hiccup mode for worst case short condition  20 Ld 4x4 QFN package  Pb-free (RoHS compliant)

Applications

 FPGA Applications  General purpose  24V bus power  Battery power  Point of load  Embedded processor and I/O supplies FIGURE 1. TYPICAL APPLICATION FIGURE 2. EFFICIENCY, SYNCHRONOUS BUCK, LLM MODE, VOUT 5V, TA =

10040 May 28, 2014 Rev A

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation Pin Configuration ER3125QI (20 LD QFN) TOP VIEW

Ordering Information

(Notes 1, 2) PART MARKING TEMP . RANGE (°C) PACKAGE (PB-Free) PKG. DWG. # ER3125QI R3125 -40 to +105 20 Ld 4x4 QFN L20.4x4C NOTES: 1. Please refer to Packing and Marking Information: www.alter a.com/support/reliability/packing/rel-packing-and-marking.html 2. These Altera Enpirion Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Functional Pin Descriptions PIN NAME PIN # DESCRIPTION EN 1 The controller is enabled when this pin is left floating or pulled HIGH. The IC is disabled when this pin is pulled LOW. Range: 0V to 5.5V. FSW 2 Connecting this pin to AVINO, or GND, or leaving it open will force the IC to have 500kHz switching frequency. The oscillator switching frequency can also be programmed by adjusting the resistor from this pin to GND. SS 3 Connect a capacitor from this pin to ground. This capacitor, along with an internal 5µA current source, sets the soft-start interval of the converter. Also, this pin can be used to track a ramp on this pin. FB 4 This pin is the inverting input of the vo ltage feedback error amplifier. With a properly selected resistor divider connected from VOUT to FB, the output voltage can be set to any voltage between the power rail (reduced by maximum duty cycle and voltage drop) and the 0.8V reference. Loop compensation is achieved by connecting an RC network across COMP and FB. The FB pin is also monitored for overvoltage events. COMP 5 Output of the voltage feedback error amplifier. RCLX 6 Programmable current limit pin. With this pin connected to the AVINO pin, or to GND, or left open, the current limiting threshold is set to default of 3.6A; the current limiting threshold can be programmed with a resistor from this pin to GND. AVIN AVINO AGND PVIN PVIN BOOST FSW RCLX LLM POK SW SW PAD

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation LLM 7 Light load mode select ion pin. Pull this pin to GND for forced PWM mode; to have it floating or connected to AVINO will enable LLM mode when the peak inductor current is below the default threshold of 700mA. The current boundary threshold between LLM and PWM can also be programmed with a resistor at this pin to ground. Check for more details in the “LLM Mode Operation” on page 15. POK 8 POK is an open drain output and pull-up pin with a resistor to AVINO for proper function. POK will be pulled low under the events when the output is out of regulation (OV or UV) or EN pin is pulled low. POK rising has a fixed 128 cycles delay. SW 9, 10 These pins are the SW nodes that sh ould be connected to the output inductor. These pins are connected to the source of the high-side N- channel MOSFET. BOOST 11 This pin is used to set boost mode and monitor the battery voltage that is the input of the boost converter. After AVINO POR, the controller will detect the voltage on this pin; if voltage on this pin is below 200mV, the controller is set in synchronous/non-synchronous buck mode and will latch in this state unless AVINO is below POR falling threshold; if the voltage on this pin after AVINO POR is above 200mV, the controller is set in boost mode and latches in this state. In boost mode, the low-side driver output PWM with same duty cycle with upper-side driver to drive the boost switch. In boost mode, this pin is used to monitor input voltage through a resistor divider. By setting the resistor divider, the high threshold and hysteresis can be programmed. When voltage on this pin is above 0.8V, the PWM output (LGATE) for the boost converter is disabled, and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled. In boost mode operation, LLM is disabled when boost PWM is enabled. Check the “2-Stage Boost Buck Converter Operation” on page 17 for more details. SYNC 12 This pin can be used to synchronize two or more ER3125QI controllers. Multiple ER3125QIs can be synchronized with their S YNC pins connected together. 180° phase shift is automatically generated between the master and slave ICs. The internal oscillator can also lock to an external frequency source applied on this pin with square pulse waveform (with frequency 10% higher than the IC’s local frequency, and pulse width higher than 150ns). Range: 0V to 5.5V. This pin should be left floating if not used. LGATE 13 In synchronous buck mode, this pin is used to drive the lo wer side MOSFET to improve efficiency. A 5.1k or smaller value resistor has to be added to connect LGATE to ground to avoid falsely turn-on of LGATE caused by coupling noise. In non-synchronous buck when a diode is used as the bottom side power device, this pin should be connected to AVINO through a resistor (less than 5k) before IC start-up to have the low-side driver (LGATE) disabled. In boost mode, it can be used to drive the boost power MOSFET. The boost control PWM is same with the buck control PWM. PGND 14 This pin is used as the ground connection of the powe r flow including driver. Connect it to large ground plane. BOOT 15 This pin provides bias voltage to the high-side MOSFET dri ver. A bootstrap circuit is used to create a voltage suitable to drive the internal N- channel MOSFET. The boot charge circuitries are integrated inside of the IC. No external boot diode is needed. A 1µF ceramic capacitor is recommended to be used between BOOT and SW pin. PVIN 16, 17 Connect the input rail to these pins that are connected to the drain of the integrated high-side MOSFET as well as the source for the internal linear regulator that provides the bias of the IC. Range: 3V to 36V. With the part switching, the operating input voltage applied to the PVIN pins must be under 36V. This recommendation allows for short voltage ringing spikes (within a couple of ns time ra nge) due to switching while not exceeding “Absolute Maximum Ratings” on page 5. AGND 18 This pin provides the return path for the control and mo nitor portions of the IC. Connect it to a quiet ground plane. AVINO 19 This pin is the output of the internal linear regulator that supplies the bias for the IC including the driver. A minimum 4.7µF decoupling ceramic capacitor is recommended between AVINO to ground. AVIN 20 This pin is the input of the auxiliar y internal linear regulator, which can be supplied by the regulator output after power-up. With such configuration, the power dissipation inside of the IC is reduced. The input range for this LDO is 3V to 20V. In boost mode operation, this pin works as boost output overvoltage detection pin. It detects the boost output through a resistor divider. When voltage on this pin is above 0.8V, the boost PWM is disabled; and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled. Range: 0V to 20V. PAD 21 Bottom thermal pad. It is not connected to any electrical potential of the IC. In layout it must be connected to PCB ground copper plane with area as large as possible to effectively reduce the thermal impedance. Functional Pin Descriptions (Continued) PIN NAME PIN # DESCRIPTION

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation Typical Application Schematics Typical Application Schematic I Typical Application Schematic II - AVINO Switch-Over to VOUT Typical Application Schematic III - Boost Buck Converter (a) SYNCHRONOUS BUCK (b) NON-SYNCHRONOUS BUCK POK POK LLM LLM AVIN AVIN AVINO AVINOER3125QI ER3125QI RCLX RCLX BOOST BOOST FSW FSW AGND AGND PVIN PVIN SW SW VPVIN VOUT VPVIN VOUT (a) SYNCHRONOUS BUCK (b) NON-SYNCHRONOUS BUCK POK POK LLM LLM AVIN AVIN AVINO AVINO ER3125QI ER3125QI PVIN PVIN SW SW RCLX RCLX BOOST BOOST FSW FSW AGND AGND VPVIN VOUT VPVIN VOUT (a) 2-STAGE BOOST BUCK (b) NON-INVERTING SINGLE INDUCTOR BUCK BOOST POK BOOST AVIN PVIN SW LLM AVINO RCLX FSW AGND VOUT ER3125QI POK BOOST AVIN PVIN SW AVINO RCLX FSW AGND AVINO VOUT VPVIN ER3125QI

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation Absolute Maximum Ratings Thermal Information ESD Rating Charged Device Model (Tested per JESD22-C101E) . . . . 1kV Latchup Rating (Tested per JESD78B; Class II, Level A)100mA Thermal Resistance θJA (°C/W) θJC (°C/W) Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposu re to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. NOTES: θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. 4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Refer to “Block Diagram” on page 14 and “Typical Application Schematics” on page 4. Operating Conditions Unless Otherwise Noted: VPVIN = 12V , or VAVINO = 4.5V ±10%, TA = -40°C to +105°C. Typicals are at TA =+ 25°C. Boldface limits apply across the operating temperature range, -40°C to +105°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNITS PVIN PIN SUPPLY PVIN Pin Voltage Range PVIN Pin 3.05 36 V PVIN Pin connected to AVINO 3.05 5.5 V Operating Supply Current IQ LLM = AVINO/FLOATING, no load at the output 300 µA LLM = GND (forced PWM), VPVIN = 12V, IC operating, not including driving current 1.3 mA Shutdown Supply Current I IN_SD EN connected to GND, VPVIN = 12V 2.8 4.5 µA INTERNAL MAIN LINEAR REGULATOR MAIN LDO VAVINO Voltage VAVINO VPVIN > 5V 4.2 4.5 4.8 V MAIN LDO Dropout Voltage V DROPOUT_MAIN VPVIN = 4.2V, IAVINO = 35mA 0.3 0.52 V VPVIN = 3V, IAVINO = 25mA 0.25 0.42 V VAVINO Current Limit of MAIN LDO 60 mA INTERNAL AUXILIARY LINEAR REGULATOR AVIN Input Voltage Range VAVIN 32 0 V AUX LDO VAVINO Voltage VAVINO VAVIN > 5V 4.2 4.5 4.8 V LDO Dropout Voltage V DROPOUT_AUX VAVIN = 4.2V, IAVINO = 35mA 0.3 0.52 V VAVIN = 3V, IAVINO = 25mA 0.25 0.42 V Current Limit of AUX LDO 60 mA AUX LDO Switch-over Rising Threshold VAVIN_RISE AVIN voltage rise; Switch to auxiliary LDO 3 3.1 3.2 V AUX LDO Switch-over Falling Threshold Voltage V AVIN_FALL AVIN voltage fall; Switch back to main BIAS LDO 2.73 2.87 2.97 V AUX LDO Switch-over Hysteresis V AVIN_HYS AVIN switch-over hysteresis 0.2 V

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation POWER-ON RESET Rising VAVINO POR Threshold VPORH_RISE 2.82 2.9 3.05 V Falling VAVINO POR Threshold VPORL_FALL 2.6 2.8 V VAVINO POR Hysteresis VPORL_HYS 0.3 V ENABLE Enable On Voltage VENH 1.7 V Enable Off voltage V ENL 1 V EN Pull-up Current I EN_PULLUP VEN = 1.2V, VPVIN = 24V 1.5 µA VEN = 1.2V, VPVIN = 12V 1.2 µA VEN = 1.2V, VPVIN = 5V 0.9 µA OSCILLATOR PWM Frequency FOSC RT = 665kΩ 160 200 240 kHz RT = 51.1kΩ 1870 2200 2530 kHz FSW pin connected to AVINO or floating or GND 450 500 550 kHz MIN ON Time t MIN_ON 130 225 ns MIN OFF Time t MIN_OFF 210 330 ns SYNCHRONIZATION Input High Threshold VIH 2 V Input Low Threshold VIL 0.5 V Input Minimum Pulse Width 25 ns Input Impedance 100 kΩ Input Minimum Frequency Divided by Free Running Frequency 1.1 Input Maximum Frequency Divided by Free Running Frequency 1.6 Output Pulse Width CSYNC = 100pF 100 ns Output Pulse High VOH R LOAD = 1kΩ AVINO- 0.25 V Output Pulse Low VOL GND V REFERENCE VOLTAGE Reference Voltage VREF 0.8 V System Accuracy -1.0 +1.0 % FB Pin Source Current 5n A Soft-start Soft-Start Current ISS 3 5 7 µA ERROR AMPLIFIER Unity Gain-Bandwidth CLOAD = 50pF 10 MHz DC Gain CLOAD = 50pF 88 dB Electrical Specifications Refer to “Block Diagram” on page 14 and “Typical Application Schematics” on page 4. Operating Conditions Unless Otherwise Noted: VPVIN = 12V , or VAVINO = 4.5V ±10%, TA = -40°C to +105°C. Typicals are at TA =+ 25°C. Boldface limits apply across the operating temperature range, -40°C to +105°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNITS

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation Maximum Output Voltage 3.6 V Minimum Output Voltage 0.5 V Slew Rate SR C LOAD = 50pF 5 V/µs LLM CONTROL Default LLM Current Threshold LLM = AVINO or floating 700 mA INTERNAL HIGH-SIDE MOSFET Upper MOSFET RDS(ON) RDS(ON)_UP Limits apply for +25°C only 127 140 m Ω LOW-SIDE MOSFET GATE DRIVER LGate Source Resistance 100mA source current 3.5 Ω LGATE Sink Resistance 100mA sink current 2.8 Ω BOOST CONVERTER CONTROL BOOST Boost_Off Threshold Voltage 0.74 0.8 0.86 V BOOST Hysteresis Sink Current I BOOST_HYS 2.1 3.2 4.2 µA AVIN Boost Turn-Off Threshold Voltage 0.74 0.8 0.86 V AVIN Hysteresis Sink Current I AVIN_HYS 2.1 3.2 4.2 µA POWER-GOOD MONITOR Overvoltage Rising Trip Point VFB/VREF Percentage of reference point 104 110 116 % Overvoltage Rising Hysteresis V FB/VOVTRIP Percentage below OV trip point 3 % Undervoltage Falling Trip Point VFB/VREF Percentage of reference point 84 90 96 % Undervoltage Falling Hysteresis VFB/VUVTRIP Percentage above UV trip point 3 % POK Rising Delay tPOK_R_DELAY 128 cycle POK Leakage Current POK HIGH, VPOK = 4.5V 10 nA POK Low Voltage VPOK POK LOW, IPOK = 0.2mA 0.10 V OVERCURRENT PROTECTION Default Cycle-by-Cycle Current Limit Threshold I OC_1 IRCLX = GND or AVINO or floating 3 3.6 4.2 A Hiccup Current Limit Threshold I OC_2 Hiccup, IOC_2/IOC_1 115 % OVERVOLTAGE PROTECTION OV 120% Trip Point Active in and after soft-start. Percentage of reference point LG = UG = LOW 120 % OV 120% Release Point Active in and after soft-start. Percentage of reference point 102.5 % OV 110% Trip Point Active after soft-start done. Percentage of reference point LG = UG = LOW 110 % OV 110% Release Point Active after soft-start done. Percentage of reference point 102.5 % OVER-TEMPERATURE PROTECTION Over-Temperature Trip Point 160 °C Electrical Specifications Refer to “Block Diagram” on page 14 and “Typical Application Schematics” on page 4. Operating Conditions Unless Otherwise Noted: VPVIN = 12V , or VAVINO = 4.5V ±10%, TA = -40°C to +105°C. Typicals are at TA =+ 25°C. Boldface limits apply across the operating temperature range, -40°C to +105°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNITS

  1. Parameters with MIN and/or MAX limits are 100% tested at +2 5°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested. FIGURE 3. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM MODE, FIGURE 4. EFFICIENCY, SYNCHRONOUS BUCK, LLM MODE, VOUT 5V, TA = FIGURE 5. LINE REGULATION, V OUT 5V, TA = +25°C FIGURE 6. LOAD REGULATION, V OUT 5V, TA = +25°C

FIGURE 7. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM MODE, FIGURE 8. EFFICIENCY, SYNCHRONOUS BUCK, LLM MODE, VOUT 3.3V, TA FIGURE 9. INPUT QUIESCENT CURRENT UNDER NO LOAD, LLM MODE, FIGURE 10. IC DIE TEMPERATURE UNDER +25°C AMBIENT

FIGURE 11. IC DIE TEMPERATURE UNDER +25°C AMBIENT FIGURE 12. SYNCHRONOUS BUCK MODE, V PVIN 36V, IO 2A, ENABLE ON FIGURE 13. SYNCHRONOUS BUCK MODE, V PVIN 36V, IO 2A, ENABLE OFF FIGURE 14. V PVIN 36V, PREBIASED START-UP

FIGURE 15. SYNCHRONOUS BUCK WITH FORCE PWM MODE, VPVIN 36V, FIGURE 16. V PVIN 24V, 0 TO 2A STEP LOAD, FORCE PWM MODE FIGURE 17. V PVIN 24V, 80mA LOAD, LLM MODE FIGURE 18. V PVIN 24V, 0 TO 2A STEP LOAD, LLM MODE

FIGURE 19. NON-SYNCHRONOUS BUCK, FORCE PWM MODE, VPVIN 12V, FIGURE 20. NON-SYNCHRONOUS BUCK, FORCE PWM MODE, VPVIN 12V, FIGURE 21. BOOST BUCK MODE, BOOST INPUT STEP FROM 36V TO 3V, FIGURE 22. BOOST BUCK MODE, BOOST INPUT STEP FROM 3V TO 36V,

FIGURE 23. BOOST BUCK MODE, VO = 9V, IO = 1.8A, BOOST INPUT DROPS FIGURE 24. EFFICIENCY, BOOST BUCK, 500KHZ, VOUT 12V, FIGURE 25. UPPER MOSFET R DS(ON) (mΩ) OVER-TEMPERATURE

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation Block Diagram Functional Description Initialization Initially the ER3125QI continually monitors the voltage at the EN pin. When the voltage on the EN pin exceeds its rising ON threshold, the internal LDO will start-up to build up AVINO. After Power-On Reset (POR) circuits detect that AVINO voltage has exceeded the POR threshold, the soft-start will be initiated. Soft-Start The soft-start (SS) ramp is built up in the external capacitor on the SS pin that is charged by an internal 5µA current source. The SS ramp starts from 0 to a voltage above 0.8V . Once SS reaches 0.8V , the bandgap reference takes over and IC gets into steady state operation. The soft-start time is referring to the duration for SS pin ramps from 0 to 0.8V while output voltage ramps up with the same rate from 0 to target regulated voltage. The required capacitance at SS pin can be calculated from Equation 1. The SS plays a vital role in the hiccup mode of operation. The IC works as cycle-by-cycle peak current limiting at over load condition. When a harsh condition occurs and the current in the upper side MOSFET reaches the second overcurrent threshold, the SS pin is pulled to ground and a dummy soft-start cycle is initiated. At dummy SS cycle, the current to charge soft-start cap is cut down to 1/5 of its normal value. So a dummy SS cycle takes 5x of the regular SS cycle. During the dummy SS period, the control loop is disabled and no PWM output. At the end of this cycle, it will start the normal SS. The hiccup mode persist until the second overcurrent threshold is no longer reached. The ER3125QI is capable of starting up with prebiased output. PVIN AVINO AVIN AGND BOOST LLM FSW AVINO POK PVIN (x2) AVINO RCLX SW (x2) CSS μF[] 6.5 t SS S[]⋅= (EQ. 1)

PWM control for fast transient response and cycle-by-cycle current limiting. See “Block Diagram” on page 14. signal comes for next cycle. pin signal is compared with the current ramp signal to shutdown the PWM. boundary current threshold. The default threshold is 700mA when there is no programming resistor at the LLM pin. The ER3125QI supports both Synchronous and non-synchronous buck operations. avoid falsely turn-on of LGATE caused by coupling noise. 2.2nF as typical) at switch node can reduce this ringing. FIGURE 26. R LLM vs ILLM

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation AVIN Switch-Over The ER3125QI has an auxiliary LDO integrated as shown in the “Block Diagram” on page 14. It is used to replace the internal MAIN LDO function after the IC start-up. “Typical Application Schematic II - AVINO Switch-Over to VOUT” on page 4 shows its basic application setup with output voltage connected to AVIN. After IC soft-start is done and the output voltage is built up to steady state, and once the AVIN pin voltage is over the AUX LDO Switch-over Rising Threshold, the MAIN LDO is shut off and the AUXILIARY LDO is activated to bias AVINO. Since the AVIN pin voltage is lower than the input voltage VPVIN, the internal LDO dropout voltage and the consequent power loss is reduced. This feature brings substantial efficiency improvements in light load range, especially at high input voltage applications. When the voltage at AVIN falls below the AUX LDO Switch-over Falling Threshold, the AUXILIARY LDO is shut off and the MAIN LDO is re-activated to bias AVINO. At the OV/UV fault events, the IC also switches back over from AUXILIARY LDO to MAIN LDO. The AVIN switchover function is offered in buck configuration. It is not offered in boost configuration when the AVIN pin is used to monitor the boost output voltage for OVP . Input Voltage With the part switching, the operating ER3125QI input voltage must be under 36V . This recommendation allows for short voltage ringing spikes (within a couple of ns time range) due to part switching while not exceeding the 44V , as stated in the Absolute Maximum Ratings. The lowest IC operating input voltage (PVIN pin) depends on AVINO voltage and the Rising and Falling V AVINO POR Threshold in the Electrical Specifications table on page 6. At IC start-up when AVINO is just over rising POR threshold, there is no switching before the soft-start starts. Therefore, the IC minimum start-up voltage on the PVIN pin is 3.05V (MAX of Rising VAVINO POR). When the soft-start is initiated, the regulator is switching and the dropout voltage across the internal LDO increases due to driving current. Thus, the IC PVIN pin shutdown voltage is related to driving current and AVINO POR falling threshold. The internal upper side MOSFET has typical 10nC gate drive. For a typical example of synchronous buck with 4nC lower MOSFET gate drive and 500kHz switching frequency, the driving current is 7mA total causing 70mV drop across internal LDO under 3V VPVIN. Then the IC shutdown voltage on the PVIN pin is 2.87V (2.8V + 0.07V). In practical design, extra room should be taken into account with concern to voltage spikes at PVIN. With boost buck configuration, the input voltage range can be expanded further down to 2.5V or lower depending on the boost stage voltage drop upon maximum duty cycle. Since the boost output voltage is connected to the PVIN pin as the buck inputs, after the IC starts up, the IC will keep operating and switching as long as the boost output voltage can keep the AVINO voltage higher than falling threshold. Refer to “2-Stage Boost Buck Converter Operation” on page 17 for more details. Output Voltage The output voltage can be programmed down to 0.8V by a resistor divider from VOUT to FB. For Buck, the maximum achievable voltage is (VPVIN*DMAX - VDROP), where VDROP is the voltage drop in the power path including mainly the MOSFET RDS(ON) and inductor DCR. The maximum duty cycle DMAX is decided by (1 - fSW * tMIN(OFF)). Output Current With the high-side MOSFET integrated, the maximum output current, which the ER3125QI can support is decided by the package and many operating conditions including input voltage, output voltage, duty cycle, switching frequency and temperature, etc. From the thermal perspective, the die temperature shouldn’t exceed +125°C with the power loss dissipated inside of the IC. Figures 10 and 11 show the thermal performance of this part operating at different conditions. Figures 10 and 11 show 2A and 2.5A buck applications under +25°C still air conditions over VPVIN range. The temperature rise data in these figures can be used to estimate the die temperature at different ambient temperatures under various operating conditions. Note that more temperature rise is expected at higher ambient temperature due to more conduction loss caused by RDS(ON) increase. Generally, the part can output 2.5A in typical buck application conditions (VPVIN 8~30V , VO 5V , 500kHz, still air and +85°C ambient conditions). For any other operating conditions, refer to the previous mentioned thermal curves to estimate the maximum output current. The output current should be derated under any conditions causing the die temperature to exceed +125°C.

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation The die temperature is equal to the sum of ambient temperature and the temperature rise resulting from the power dissipated by the IC package with a certain junction to ambient thermal impedance θJA. The power dissipated in the IC is related to the MOSFET switching loss, conduction loss and the internal LDO loss. Besides the load, these losses are also related to input voltage, output voltage, duty cycle, switching frequency and temperature. With the exposed pad at the bottom, the heat of the IC mainly goes through the bottom pad and θJA is greatly reduced. The θJA is highly related to layout and air flow conditions. In layout, multiple vias (≥9) are strongly recommended in the IC bottom pad. The bottom pad with its vias should be placed in the ground copper plane with an area as large as possible across multiple layers. The θJA can be reduced further with air flow. Refer to Figures 8 and 9 for the thermal performance with 100 CFM air flow. For applications with high output current and extreme operating conditions (compact board size, high ambient temperature, etc.), synchronous buck is highly recommended since the external low-side MOSFET generates smaller heat than external low-side power diode. This helps to reduce PCB temperature rise around the ER3125QI and reduce junction temperature rise. 2-Stage Boost Buck Converter Operation The “Typical Application Schematic III - Boost Buck Converter” on page 4, shows the circuits of boost function. Schematic (a) shows a boost working as a pre-stage to provide input to the following Buck stage. This is for applications when the input voltage could drop to a very low voltage in some constants (in some battery powered systems as for example), causing the output voltage to drop out of regulation. The boost converter can be enabled to boost the input voltage up to keep the output voltage in regulation. When system input voltage recovers back to normal, the boost stage is disabled while only the buck stage is switching. The BOOST pin is used to set boost mode and monitor the boost input voltage. At IC start-up before soft-start, the controller will be latched in boost mode when the voltage is at or above 200mV; it will latch in synchronous buck mode if voltage on this pin is below 200mV . In boost mode the low-side driver output PWM has the same PWM signal with the buck regulator. In boost mode, the BOOST pin is used to monitor boost input voltage to turn on and turn off the boost PWM. The AVIN pin is used to monitor the boost output voltage to turn on and turn off the boost PWM. Referring to Figure 27 on page 18, a resistor divider from boost input voltage to the BOOST pin is used to detect the boost input voltage. When the voltage on BOOST pin is below 0.8V , the boost PWM is enabled with a fixed 500µs soft- start and the boost duty cycle increases linearly from tMIN(ON)*fSW to ~50%. A 3µA sinking current is enabled at the BOOST pin for hysteresis purposes. When the voltage on the BOOST pin recovers to be above 0.8V , the boost PWM is disabled immediately. Use Equation 3 to calculate the upper resistor RUP (R1 in Figure 27) for a desired hysteresis VHYS at boost input voltage. Use Equation 4 to calculate the lower resistor RLOW (R2 in Figure 27) according to a desired boost enable threshold. Where VFTH is the desired falling threshold on boost input voltage to turn on the boost, 3µA is the hysteresis current, and 0.8V is the reference voltage to be compared with. Note that the boost start-up threshold has to be selected in a way that the buck is operating working well and kept in close loop regulation before boost start-up. Otherwise, large in-rush current at boost start-up could occur at boost input due to the buck open loop saturation. The boost start-up input voltage threshold should be set high enough to cover the DC voltage drop of boost inductor and diode, also the buck’s maximum duty cycle and voltage conduction drop. This ensures buck is not reaching maximum duty cycle before boost start-up. Similarly, a resistor divider from the boost output voltage to the AVIN pin is used to detect the boost output voltage. When the voltage on the AVIN pin is below 0.8V , the boost PWM is enabled with a fixed 500µs soft-start, and a 3µA RUP MΩ[] VHYS RLOW RUP 0.8⋅

(R4 in Figure 27) according to a desired boost enable threshold at boost output. the PVIN pin (buck input) still sees 5.2V to keep the IC working. power, VBAT is the boost input voltage, and EFF is the estimated efficiency of the whole boost and buck stages. FIGURE 27. BOOST CONVERTER CONTROL

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation Non-Inverting Single Inductor Buck Boost Converter Operation In “Typical Application Schematic III - Boost Buck Converter” on page 4, schematic (b) shows non-inverting single inductor buck boost configuration. The recommended setting is to use resistor divider 1MΩ and 130kΩ (as shown in TYP Schematic III b) connecting from AVINO to both BOOST and AVIN pins (BOOST and AVIN pin are directly connected). In this way, the BOOST pin voltage is a fixed voltage 0.52V that is higher than the boost mode detection threshold 0.2V to set IC in boost mode and lower than the boost switching threshold 800mV to have boost being constantly switching (during and after soft-start). As the same in 2-stage boost buck mode, LGATE is switching ON with the same phase of upper FETs switching ON, meaning both upper and lower side FETs are ON and OFF at the same time with the same duty cycle. When both FETs ON, input voltage charges inductor current ramping up for duration of DT; when both FETs OFF, inductor current is free wheeling through the 2 power diodes to output, and output voltage discharge the inductor current ramping down for (1-D)T (in CCM mode). The steady state DC transfer function is: where VPVIN is the input voltage, VOUT is the buck boost output voltage, D is duty cycle. Another useful equation is to calculate the inductor DC current as below: where ILDC is the inductor DC current and IOUT is the output DC current. Equation 10 shows the inductor current is charging output only during (1-D)T, which means inductor current has larger DC current than output load current. Thus, for this part with high-side FET integrated, the non-inverting buck boost configuration has less load current capability compared with buck and 2-stage boost buck configurations. Its load current capability depends mainly on the duty cycle and inductor current. Inductor ripple current can be calculated below: The inductor peak current is, In power stage DC calculations, use Equation 9 to calculate D, then use Equation 10 to calculate ILDC. D and ILDC are useful information to estimate the high-side FET’s power losses and check if the part can meet the load current requirements. Oscillator and Synchronization The oscillator has a default frequency of 500kHz with the fSW pin connected to AVINO, or ground, or floating. The frequency can be programmed to any frequency between 200kHz and 2.2MHz with a resistor from fSW pin to GND. (EQ. 9)VOUT D ILDC ILRIPPLE VOUT 1D–() T ILPEAK ILDC 2--- ILRIPPLE⋅+= (EQ. 12) RFSW kΩ[] 145000 16 f SW⋅ kHz[]–

The SYNC pin is bi-directional and it outputs the IC’s default or programmed local clock signal when it’s free running. be 1.6 of the free running frequency. have 180° phase shift with respective to the master IC. FB voltage is within OV/UV window (90%REF < FB < 110%REF). current flowing through the upper MOSFET. There are 2 current limiting thresholds. The first one IOC1 is to limit the high-side MOSFET peak current cycle-by-cycle. FIGURE 28. R FSW vs FREQUENCY

40kΩ to 330kΩ. RCLX value out of this range is not recommended. the true soft-start cycle is attempted again. The IOC2 offers a robust and reliable protections against the worst case conditions. overload condition. The low limit of frequency under frequency foldback operation is 40kHz. ON. 110% OVP is off during soft-start and active after soft-start is done. 120% OVP is active during and after soft-start. The ER3125QI PWM will be disabled if the junction temperature reaches +160°C. There is +20°C hysteresis for OTP . The part will restart after the junction temperature drops below +140°C. ESR ceramic capacitors and thus smaller board layout. Electrolytic and polymer capacitors may also be used. voltage level. Additional capacitance may be used. FIGURE 29. R LIM vs IOC1

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation where ΔI is the inductor’s peak to peak ripple current, fSW is the switching frequency and COUT is the output capacitor. If using electrolytic capacitors then: Regarding transient response needs, a good starting point is to determine the allowable overshoot in VOUT if the load is suddenly removed. In this case, energy stored in the inductor will be transferred to COUT causing its voltage to rise. After calculating capacitance required for both ripple and transient needs, choose the larger of the calculated values. The Equation 17 determines the required output capacitor value in order to achieve a desired overshoot relative to the regulated voltage. where VOUTMAX/VOUT is the relative maximum overshoot allowed during the removal of the load. Input Capacitors - Buck Depending on the system input power rail conditions, the aluminum electrolytic type capacitor is normally needed to provide the stable input voltage. Thus, restrict the switching frequency pulse current in a small area over the input traces for better EMC performance. The input capacitor should be able to handle the RMS current from the switching power devices. Ceramic capacitors must be used at PVIN pin of the IC and multiple capacitors including 1µF and 0.1µF are recommended. Place these capacitors as closely as possible to the IC. Output Inductor - Buck The inductor value determines the converter’s ripple current. Choosing an inductor current requires a somewhat arbitrary choice of ripple current, ΔI. A reasonable starting point is 30% to 40% of total load current. The inductor value is calculated using Equation 18: Increasing the value of inductance reduces the ripple current and thus ripple voltage. However, the larger inductance value may reduce the converter’s response time to a load transient. The inductor current rating should be as such that it will not saturate in overcurrent conditions. Low-Side Power MOSFET In synchronous buck application, a power N MOSFET is needed as the synchronous low-side MOSFET and a good one should have low Qgd, low RDS(ON) and small Rg (Rg_typ < 1.5Ω recommended). The Vgth_min is recommended to be or higher than 1.2V . A good example is SQS462EN. A 5.1k or smaller value resistor has to be added to connect LGATE to ground to avoid falsely turn-on of LGATE caused by coupling noise. Output Voltage Feedback Resistor Divider The output voltage can be programmed down to 0.8V by a resistor divider from VOUT to FB according to Equation 19. In an application requiring least input quiescent current, large resistors should be used for the divider. Generally, a resistor value of 10k to 300k can be used for the upper resistor. VOUTripple ΔI*ESR= (EQ. 16) (EQ. 17)COUT IOUT 2*L VOUT 2* VOUTMAX VOUT⁄() 2 1 )– (EQ. 18)L VPVIN VOUT– VOUT VPVIN VOUT 0.8 1 RUP RLOW ⎛⎞⋅= (EQ. 19)

current at start-up must be checked by oscilloscope to ensure it is under acceptable range. The ER3125QI uses constant frequency peak current mode control architecture to achieve fast loop transient response. line regulation. Figure 30 shows the small signal model of a buck regulator. where, Rt is the gain of the current amplifier. FIGURE 30. SMALL SIGNAL MODEL OF BUCK REGULATOR

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation Current Sampling Transfer Function He(S) In current loop, the current signal is sampled every switching cycle. It has the following transfer function in Equation 22: where, Qn and ωn are given by Power Stage Transfer Functions Transfer function F1(S) from control to output voltage is: Where, Transfer function F2(S) from control to inductor current is given by Equation 24: where . Current loop gain Ti(S) is expressed as Equation 25: The voltage loop gain with open current loop is expressed in Equation 26: The Voltage loop gain with current loop closed is given by Equation 27: If Ti(S)>>1, then Equation 27 can be simplified as Equation 28: He S() S2 ωn ωnQn Qn π---– = ωn πfSW=, F1 S() vˆo 1 S ωesr ωo ωoQp ωesr RcCo Co LP LPCo F2 S() Iˆo dˆ---- VPVIN 1 S ωz -----+ ωo ωoQp ωz RoCo Ti S() RtFmF2 S() He S()= (EQ. 25) Tv S() KFmF1 S() Av S()= (EQ. 26) Lv S() Tv S() Lv S() Ro RLP+ Rt 1 S ωesr 1 S ωp -----+ Av S() RoCo

FIGURE 31. TYPE III COMPENSATOR

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation The compensator design procedure is as follows: 1. Position ωCZ2 and ωCP to derive R3 and C3. Put the compensator zero ωCZ2 at (1 to 3)/(RoCo) Put the compensator pole ωCP at ESR zero or 0.35 to 0.5 times of switching frequency, whichever is lower. In all-ceramic-cap design, the ESR zero is normally higher than half of the switching frequency. R3 and C3 can be derived as follows: Case A: ESR zero less than (0.35 to 0.5)f SW Case B: ESR zero larger than (0.35 to 0.5)f SW 2. Derive R 2 and C1. The loop gain Lv(S) at cross over frequency of fc has unity gain. Therefore, C1 is determined by Equation 35. The compensator zero ωCZ1 can boost the phase margin and bandwidth. To put ωCZ1 at 2 times of cross cover frequency fc is a good start point. It can be adjusted according to specific design. R1 can be derived from Equation 36. Example: VPVIN = 12V, Vo = 5V, Io = 2A, fSW = 500kHz, Co = 60µF/3mΩ, L = 10µH, Rt = 0.20V/A, fc = 50kHz, R1 =1 0 5 k , RBIAS = 20kΩ. Select the crossover frequency to be 35kHz. Since the output capacitors are all ceramic, use Equations 33 and 34 to derive R3 to be 20k and C3 to be 470pF. Then use Equations 35 and 36 to calculate C1 to be 180pF and R2 to be 12.7k. Select 150pF for C1 and 15k for R2. There is approximately 30pF parasitic capacitance between COMP to FB pins that contributes to a high frequency pole. Any extra external capacitor is not recommended between COMP and FB. Figure 32 shows the simulated bode plot of the loop. It is shown that it has 26kHz loop bandwidth with 70° phase margin and - 28 dB gain margin. Note in applications where the LLM mode is desired especially when type III compensation network is used, the value of the capacitor between the COMP pin and the FB pin (not the capacitor in series with the resistor between COMP and FB) should be minimal to reduce the noise coupling for proper LLM operation. No external capacitor between COMP and FB is recommended at LLM applications. In LLM mode operations, a RC filter from FB to ground (R in series with C, connecting from FB to ground) may help to reduce the noise effects injected to FB pin. The recommended values for the filter is 499Ω to 1k for the R and 470pF for the C. ωcz2 RoCo 2πRcCo RoCo 3RcCo– 3R1 3RcR1 2πRcCo 0.33RoCofSW 0.46– fSW R1 R1 R3+() C3 2πfcRtR1Co 4πfcC1

FIGURE 32. SIMULATED LOOP BODE PLOT

  1. Place the input ceramic capacitors as closely as possibl e to the IC PVIN pin and power ground connecting to the

possible to achieve the least voltage spikes induced by the trace parasitic inductance.

  1. Place the input aluminum capacitors closely as possible to the IC PVIN pin.
  2. Keep the switch node copper area small bu t large enough to handle the load current.
  3. Place the output ceramic and al uminum capacitors close to the power stage components as well.
  4. Place vias ( ≥9) in the bottom pad of the IC. The bottom pad should be placed in ground copper plane with an area

as large as possible in multiple layers to effectively reduce the thermal impedance.

  1. Place the 4.7µF ceramic decoupling capacitor at the AVINO pin (the closest place to the IC). Put multiple vias (≥3)

close to the ground pad of this capacitor.

  1. Keep the bootstrap capacitor close to the IC.
  2. Keep the LGATE drive trace as short as possible and try to avoid using via in the LGATE drive path to achieve the
  3. Place the positive voltage sense trace cl ose to the place to be strictly regulated.
  4. Place all the peripheral control components close to the IC.

FIGURE 33. PCB VIA PATTERN

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation

Revision History

The table lists the revision history for this document. DATE REVISION CHANGE May, 2014 1.0 Initial Release.

Enpirion Power Datasheet ER3125QI 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter May 2014 Altera Corporation Package Outline Drawing L20.4x4C

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 11/06 located within the zone indicated. The pin #1 identifier may be Unless otherwise specified, tolerance : Decimal ± 0.05 Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. Dimension b applies to the metallized terminal and is measured Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. either a mold or mark feature. Dimensions are in millimeters.1. NOTES: BOTTOM VIEW DETAIL "X"TYPICAL RECOMMENDED LAND PATTERN TOP VIEW BOTTOM VIEW SIDE VIEW 4.00 A 4.00 B PIN 1 INDEX AREA (4X) 0.15 0.50 2.0 16X 2016 PIN #1 INDEX AREA 2 .70 ± 0 . 15

0.10 M ABC

20X 0.4 ± 0.10 610 BASE PLANE SEATING PLANE 0.10 SEE DETAIL "X" 0.08 C C C 0 . 90 ± 0 . 1 0 . 2 REFC 0 . 05 MAX. 0 . 00 MIN. ( 3. 8 TYP ) ( 2. 70 ) ( 20X 0 . 6) ( 20X 0 . 5 ) ( 20X 0 . 25 )