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Document overview
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- PDF pages: 25
Technical content
Features
- Wide input voltage range 3V to 36V
- Synchronous Operation for high efficiency
- No compensation required
- Integrated High-side and Low-side NMOS devices
- Selectable PFM or forced PWM mode at light loads
- Internal fixed (500kHz) or ad justable Switching frequency 300kHz to 2MHz
- Continuous output current up to 500mA
- Internal or exte rnal Soft-start
- Minimal external components required
- Power-good and enable functions available.
Applications
- FPGA power
- Digital processor power
- Mixed-signal ASIC power
- Industrial control
- Medical devices
- Portable instrumentation
- Distributed Power supplies
- Cloud Infrastructure
FIGURE 1. TYPICAL APPLICATION FIGURE 2. EFFICIENCY vs LOAD, PFM, V OUT = 3.3V
09616 March 14, 2014 Rev A
ER3105DI 500mA Wide VIN Synchronous Buck Regulator March 2014 Altera Corporation
Ordering Information
(Notes 1, 2, 3) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG . DWG. # ER3105DI 3105 -40 to +125 12 Ld DFN L12.4x3 EVB-ER3105DI Evaluation Board NOTES: 1. Add “T” suffix for Tape and Reel. 2. These Altera Enpirion Pb-free plastic p ackaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ER3105DI 500mA Wide VIN Synchronous Buck RegulatorMarch 2014 Altera Corporation Pin Configuration ER3105DI (12 LD 4X3 DFN) TOP VIEW Pin Descriptions PIN NUMBER SYMBOL PIN DESCRIPTION 1 SS The SS pin controls the soft-start ramp time of the output. A single capacitor from the SS pin to ground determines the output ramp rate. See “Soft Start” on page 16 for soft-start details. If the SS pin is tied to A VINO, an internal soft-start of 2ms will be used. 2 SYNC Synchronization and light load operational mode selection input. Co nnect to logic high or A VINO for PWM mode. Connect to logic low or ground for PFM mode. Logic ground enables the IC to automatically choose PFM or PWM operation. Connect to an external clock source for synchronization with positive edge trigger. Sync source must be higher than the programmed IC frequency. There is an internal 5M pull-down resistor to prevent an undefined logic state if SYNC is left floating. 3 BOOT Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the necessary charge to turn on the internal N-Channel MOSFET. Connect an external 100nF capacitor from this pin to SW. 4 PVIN The input supply for the power stage of the re gulator and the source for the internal linear bias regulator. Place a minimum of 4.7µF ceramic capacitance from PVIN to GND and close to the IC for decoupling. 5 SW Switch node output. It connects the switching FET’s with the external output inductor. 6 PGND Power ground connection. Connect directly to the system GND plane. 7 EN Regulator enable input. The re gulator and bias LDO are held off when the pin is pulled to ground. When the voltage on this pin rises above 1V , the chip is enabled. Connect this pin to PVIN for automatic start-up. Do not connect EN pin to A VINO since the LDO is controlled by EN voltage.
8 POK Open drain power-good output that is pulled to ground when the output voltage is below regulation
limits or during the soft-start interval. There is an internal 5M internal pull-up resistor. 9 A VINO Output of the internal 5V lin ear bias regulator. Decouple to PGND with a 1µF ceramic capacitor at the pin. 10 FB Feedback pin for the regulator. FB is the inverting input to the voltage loop error amplifier. COMP is the output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. In addition, the PWM regulator’s power-good and UVLO circuits use FB to monitor the regulator output voltage. 11 COMP COMP is the output of the er ror amplifier. When it is tied to A VINO, internal compensation is used. When only an RC network is connected from COMP to GND, external compensation is used. See “Loop Compensation Design” on page 21 for more details. 12 FSW Frequency selection pin. Tie to A VINO for 500kH z switching frequency. Connect a resistor to GND for adjustable frequency from 300kHz to 2MHz. EPAD GND Signal ground connections. Co nnect to application board GND plane with at least 5 vias. All voltage levels are measured with respect to this pin. The EPAD MUST not float. AVINO EN PVIN FB SW BOOT COMP POK SS FSW PGND 6 GND 7 SYNC
FIGURE 3. INTERNAL DEFA ULT PARAMETER SELECTION FIGURE 4. USER PROGRAMMABLE PARAMETER SELECTION TABLE 1. EXTERNAL COMPONENT SELECTION
ER3105DI 500mA Wide VIN Synchronous Buck RegulatorMarch 2014 Altera Corporation Absolute Maximum Ratings Thermal Information COMP, FSW, POK, SYNC, SS, A VINO to GND . . -0.3V to +5.9V ESD Rating Thermal Resistance JA (°C/W) JC (°C/W) Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. 4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications TA = -40°C to +125°C, VIN = 3V to 36V , unless otherwise noted. Typical values are at TA =+ 2 5°C. Boldface limits apply over the junction temperature range, -40°C to +125°C PARAMETER SYMBOL TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNITS SUPPLY VOLTAGE VIN V oltage Range VIN 33 6 V VIN Quiescent Supply Current I Q VFB = 0.7V , SYNC = 0V , FSW = AV I N O 80 µA VIN Shutdown Supply Current I SD EN = 0V , VIN=36V (Note 5) 1.8 2.5 µA AV I N O Vo l t a g e AV I N O I OUT = 0mA 4.8 5.15 5.5 V VIN = 6V; IOUT = 10mA 4.65 5 5.35 V POWER-ON RESET A VINO POR Threshold Rising Edge 2.75 2.95 V Falling Edge 2.4 2.6 V OSCILLATOR Nominal Switching Frequency F SW FSW = A VINO 440 500 560 kHz Resistor from FSW to GND = 340k 240 300 360 kHz Resistor from FSW to GND = 32.4k 2000 kHz Minimum Off-Time tOFF VIN = 3V 150 ns Minimum On-Time tON (Note 8) 90 ns FSW V oltage VFSW RFSW = 100kΩ 0.39 0.4 0.41 V Synchronization Frequency SYNC 300 2000 kHz SYNC Pulse Width 100 ns ERROR AMPLIFIER Error Amplifier Transconductance Gain gm External Compensation 165 230 295 µA/V Internal Compensation 50 µA/V FB Leakage Current V FB = 0.6V 1 100 nA Current Sense Amplifier Gain R T 0.54 0.6 0.66 V/A FB V oltage TA = -40°C to +85°C 0.589 0.599 0.606 V TA = -40°C to +125°C 0.589 0.599 0.609 V
ER3105DI 500mA Wide VIN Synchronous Buck Regulator March 2014 Altera Corporation POWER-GOOD Lower POK Threshold - VFB Rising 90 94 % Lower POK Threshold - VFB Falling 82.5 86 % Upper POK Threshold - VFB Rising 116.5 120 % Upper POK Threshold - VFB Falling 107 112 % POK Propagation Delay Percentage of the soft-start time 10 % POK Low V oltage I SINK = 3mA, EN = A VINO, VFB = 0V 0.05 0.3 V TRACKING AND SOFT-START Soft-Start Charging Current I SS 1.5 2 2.5 µA Internal Soft-Start Ramp Time EN/SS = A VINO 1.7 2.4 3.1 ms FAULT PROTECTION Thermal Shutdown Temperature T SD Rising Threshold 150 °C THYS Hysteresis 20 °C Current Limit Blanking Time t OCON 17 Clock pulses Overcurrent and Auto Restart Period tOCOFF 8 SS cycle Positive Peak Current Limit IPLIMIT (Note 6) 0.8 0.9 1 A PFM Peak Current Limit I PK_PFM 0.26 0.3 0.34 A Zero Cross Threshold 10 mA Negative Current Limit INLIMIT (Note 6) -0.46 -0.40 -0.34 A POWER MOSFET High-side R HDS ISW = 100mA, AVINO = 5V 450 600 m Low-side R LDS ISW = 100mA, AVINO = 5V 250 330 m SW Leakage Current EN = SW = 0V 300 nA SW Rise Time tRISE VIN = 36V 10 ns EN/SYNC Input Threshold Falling Edge, Logic Low 0.4 1V Rising Edge, Logic High 1.2 1.4 V EN Logic Input Leakage Current EN = 0V/36V -0.5 0.5 µA SYNC Logic Input Leakage Current SYNC = 0V 10 100 nA SYNC = 5V 1.0 1.3 µA NOTES: 5. Test Condition: V IN = 36V , FB forced above regulation point (0.6V), no switching, and power MOSFET gate charging current not included. 6. Established by both current sense amplifier gain test and current sense amplifier output test @ IL = 0A. 7. Parameters with MIN and/or MAX limits are 100% tested at +2 5°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 8. Minimum On-Time required to maintain loop stability. Electrical Specifications TA = -40°C to +125°C, VIN = 3V to 36V , unless otherwise noted. Typical values are at TA =+ 2 5°C. Boldface limits apply over the junction temperature range, -40°C to +125°C (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNITS
FIGURE 5. EFFICIENCY vs LOAD, PFM, V OUT = 5V FIGURE 6. EFFICIENCY vs LOAD, PWM, V OUT = 5V FIGURE 7. EFFICIENCY vs LOAD, PFM, V OUT = 3.3V FIGURE 8. EFFICIENCY vs LOAD, PWM, V OUT = 3.3V FIGURE 9. EFFICIENCY vs LOAD, PFM, V OUT = 1.8V FIGURE 10. EFFICIENCY vs LOAD, PWM, V OUT = 1.8V
FIGURE 11. V OUT REGULATION vs LOAD, PWM, VOUT = 5V FIGURE 12. V OUT REGULATION vs LOAD, PFM, VOUT = 5V FIGURE 13. V OUT REGULATION vs LOAD, PWM, VOUT = 3.3V FIGURE 14. V OUT REGULATION vs LOAD, PFM, VOUT = 3.3V FIGURE 15. V OUT REGULATION vs LOAD, PWM, VOUT = 1.8V FIGURE 16. V OUT REGULATION vs LOAD, PFM, VOUT = 1.8V
FIGURE 17. EFFICIENCY vs LOAD, PFM, V OUT = 5V FIGURE 18. EFFICIENCY vs LOAD, PWM, V OUT = 5V FIGURE 19. EFFICIENCY vs LOAD, PFM, V OUT = 3.3V FIGURE 20. EFFICIENCY vs LOAD, PWM, V OUT = 3.3V FIGURE 21. EFFICIENCY vs LOAD, PFM, V OUT = 1.8V FIGURE 22. EFFICIENCY vs LOAD, PWM, V OUT = 1.8V
FIGURE 23. EFFICIENCY vs LOAD, PFM, V OUT = 1.8V FIGURE 24. EFFICIENCY vs LOAD, PFM, V OUT = 3.3V FIGURE 25. EFFICIENCY vs LOAD, PFM, V OUT = 5V FIGURE 26. V OUT REGULATION vs LOAD, PWM, VOUT = 5V FIGURE 27. V OUT REGULATION vs LOAD, PFM, VOUT = 5V
FIGURE 28. V OUT REGULATION vs LOAD, PWM, VOUT = 3.3V FIGURE 29. V OUT REGULATION vs LOAD, PFM, VOUT = 3.3V FIGURE 30. V OUT REGULATION vs LOAD, PWM, VOUT = 1.8V FIGURE 31. V OUT REGULATION vs LOAD, PFM, VOUT = 1.8V FIGURE 32. START-UP AT NO LOAD, PFM FIGURE 33. START-UP AT NO LOAD, PWM
FIGURE 34. SHUTDOWN IN NO LOAD, PFM FIGURE 35. SHUTDOWN AT NO LOAD, PWM FIGURE 36. START-UP AT 500mA, PWM FIGURE 37. SHUTDOWN AT 500mA, PWM FIGURE 38. START-UP AT 500mA, PFM FIGURE 39. SHUTDOWN AT 500mA, PFM
FIGURE 40. JITTER AT NO LOAD, PWM FIGURE 41. JITTER AT 500mA, PWM FIGURE 42. STEADY STATE AT NO LOAD, PFM FIGURE 43. STEADY STATE AT NO LOAD, PWM FIGURE 44. STEADY STATE AT 500mA LOAD, PWM FIGURE 45. LIGHT LOAD OPERATION AT 20mA, PFM
FIGURE 46. LIGHT LOAD OPERATION AT 20mA, PWM FIGURE 47. LOAD TRANSIENT, PFM FIGURE 48. LOAD TRANSIENT, PWM FIGURE 49. PFM TO PWM TRANSITION FIGURE 50. OVERCURRENT PROTECTION, PWM FIGURE 51. OVERCURRENT PROTECTION HICCUP, PWM
FIGURE 52. SYNC AT 500mA LOAD, PWM FIGURE 53. NEGATIVE CURRENT LIMIT, PWM FIGURE 54. NEGATIVE CURRENT LIMIT RECOVERY , PWM FIGURE 55. OVER-TEMPERATURE PROTECTION, PWM
ER3105DI 500mA Wide VIN Synchronous Buck Regulator March 2014 Altera Corporation Functional Block Diagram Functional Description The ER3105DI combines a synchronous buck PWM controller with integrated power switches. The buck controller drives internal high-side and low-side N-channel MOSFETs to deliver load current up to 500mA. The buck regulator can operate from an unregulated DC source, such as a battery, with a voltage ranging from +3V to +36V . An internal LDO provides bias to the low voltage portions of the IC. Peak current mode control is utilized to simplify feedback loop compensation and reject input voltage variation. User selectable internal feedback loop compensation further simplifies design. The ER3105DI switches at a default 500kHz. The buck regulator is equipped with an internal current sensing circuit and the peak current limit threshold is typically set at 0.9A. Power-On Reset The ER3105DI automatically initializes upon receipt of the input power supply and continually monitors the EN pin state. If EN is held below its logic rising threshold the IC is held in shutdown and consumes typically 1µA from the PVIN supply. If EN exceeds its logic rising threshold, the regulator will enable the bias LDO and begin to monitor the A VINO pin voltage. When the A VINO pin voltage clears its rising POR threshold the controller will initialize the switching regulator circuits. If A VINO never clears the rising POR threshold, the controller will not allow the switching regulator to operate. If A VINO falls below its falling POR threshold while the switching regulator is operating, the switching regulator will be shut down until A VINO returns. Soft Start To avoid large in-rush current, VOUT is slowly increased at startup to its final regulated value. Soft-start time is determined by the SS pin connection. If SS is pulled to A VINO, an internal 2ms timer is selected for soft-start. For other soft-start times, simply connect a capacitor from SS to GND. In this case, a 2µA current pulls up the SS voltage and the FB pin will follow this ramp until it reaches the 600mV reference level. Soft-start time for this case is described by Equation 1: GATE DRIVE AND DEADTIME BIAS LDO OSCILLATOR PFM CURRENT SET FAULT LOGIC 450mV/T Slope Compensation (PWM only) 600mV/Amp Current Sense PWM/PFM SELECT LOGIC EN/SOFT START Zero Current Detection PWM PWM 600mV VREF gm 150k 54pF Internal Compensation s R Q Q POWER GOOD LOGIC FB Internal = 50µs External = 230µs PGND SW BOOT AVINO PVIN EN FB FSW SYNC COMP POK GND PACKAGE PADDLE SS FB Time ms Cn F 0.3= (EQ. 1)
POK is the open-drain output of a window comparator that continuously monitors the buck regulator output voltage via the FB pin. POK becomes high impedance provided the FB pin is within the range specified in the “Electrical Specifications” on page 3. the fault condition is cleared by an attempt to soft-start. There is an internal 5M internal pull-up resistor. comes from the error amplifier’s output (VCOMP). the sum of the current sense and slope compensation signal. connected to the output voltage via the FB pin and its associated divider network. operation. The IC enters the DCM mode of operation when 8 consecutive cycles of inductor current crossing zero are detected. where D = duty cycle, FSW = switching frequency, L = inductor value, IOUT = output loading current, VOUT = output voltage. frequency equal to the converters programmed PWM operating frequency. FIGURE 56. PWM OPERATION WA VEFORMS
and forces the converter to return to PWM operation. voltage. The scaled voltage is applied to the inverting input of the error amplifier; refer to Figure 57. voltage, VOUT, of the regulator. Equation 3 describes the relationship between VOUT and resistor values. If the desired output voltage is 0.6V , then R3 is left unpopulated and R2 is 0Ω. regulator will attempt a normal soft-start. FIGURE 57. DCM MODE OPERATION WA VEFORMS
8 CYCLES
FIGURE 58. EXTERNAL RESISTOR DIVIDER
ER3105DI 500mA Wide VIN Synchronous Buck RegulatorMarch 2014 Altera Corporation Should the output fault persist, the regulator will repeat the hiccup sequence indefinitely. There is no danger even if the output is shorted during soft-start. If VOUT is shorted very quickly, FB may collapse below 5/8ths of its target value before 17 cycles of overcurrent are detected. The ER3105DI recognizes this condition and will begin to lower its switching frequency proportional to the FB pin voltage. This insures that under no circumstance (even with VOUT near 0V) will the inductor current run away. Negative Current Limit Should an external source somehow drive current into VOUT, the controller will attempt to regulate VOUT by reversing its inductor current to absorb the externally sourced current. In the event that the external source is low impedance, current may be reversed to unacceptable levels and the controller will initiate its negative current limit protection. Similar to normal overcurrent, the negative current protection is realized by monitoring the current through the lower FET. When the valley point of the inductor current reaches negative current limit, the lower FET is turned off and the upper FET is forced on until current reaches the POSITIVE current limit or an internal clock signal is issued. At this point, the lower FET is allowed to operate. Should the current again be pulled to the negative limit on the next cycle, the upper FET will again be forced on and current will be forced to 1/6th of the positive current limit. At this point the controller will turn off both FET’s and wait for COMP to indicate return to normal operation. During this time, the controller will apply a 100 load from SW to PGND and attempt to discharge the output. Negative current limit is a pulse-by-pulse style operation and recovery is automatic. Negative current limit protection is disabled in PFM operating mode because reverse current is not allowed to build due to the diode emulation behavior of the lower FET. Over-Temperature Protection Over-temperature protection limits maximum junction temperature in the ER3105DI. When junction temperature (TJ) exceeds +150°C, both FET’s are turned off and the controller waits for temperature to decrease by approximately 20°C. During this time POK is pulled low. When temperature is within an acceptable range, the controller will initiate a normal soft-start sequence. For continuous operation, the +125°C junction temperature rating should not be exceeded. Boot Undervoltage Protection If the Boot capacitor voltage falls below 1.8V , the Boot undervoltage protection circuit will turn on the lower FET for 400ns to recharge the capacitor. This operation may arise during long periods of no switching such as PFM no load situations. In PWM operation near dropout (VIN near VOUT), the regulator may hold the upper FET on for multiple clock cycles. To prevent the boot capacitor from discharging, the lower FET is forced on for approximately 200ns every 10 clock cycles. Application Guidelines Simplifying the Design While the ER3105DI offers user programmed options for most parameters, the easiest implementation with fewest components involves selecting internal settings for SS, COMP and FSW. Table 1 on page 4 provides component value selections for a variety of output voltages and will allow the designer to implement solutions with a minimum of effort. Operating Frequency The ER3105DI operates at a default switching frequency of 500kHz if FSW is tied to A VINO. Tie a resistor from FSW to GND to program the switching frequency from 300kHz to 2MHz, as shown in Equation 4. Where: t is the switching period in µs.
higher VOUT will mean higher inductance. While ceramic capacitors offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered. these conditions do not reflect reality. As a result, the actual capacitance may be considerably lower than the advertised value. choice in many applications due to their reliability and extremely low ESR. FIGURE 59. R FSW SELECTION vs FSW
where I is the inductor’s peak-to-peak ripple current, FSW is the switching frequency and COUT is the output capacitor. FIGURE 60. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK REGULATOR FIGURE 61. TYPE II COMPENSATOR
ER3105DI 500mA Wide VIN Synchronous Buck Regulator March 2014 Altera Corporation Choose Loop bandwidth fc less than 100kHz Gain margin: >10dB Phase margin: >40° The compensator design procedure is as follows: The loop gain at crossover frequency of f c has a unity gain. Therefore, the compensator resistance R6 is determined by Equation 9. Where GM is the trans-conductance, gm, of the voltage error amplifier in each phase. Compensator capacitor C6 is then given by Equation 10. Put one compensator pole at zero frequency to achieve high DC gain, and put another compensator pole at either ESR zero frequency or half switching frequency, whichever is lower in Equation 10. An optional zero can boost the phase margin. CZ2 is a zero due to R2 and C3 Put compensator zero 2 to 5 times fc Example: VIN = 12V , VO = 5V , IO = 500mA, fSW = 500kHz, R2 = 90.9k, Co = 22µF/5mΩ, L = 39µH, fc = 50kHz, then compensator resistance R6: It is acceptable to use 150kas theclosest standard value for R6. It is also acceptable to use the closest standard values for C6 and C7. There is approximately 3pF parasitic capacitance from VCOMP to GND; Therefore, C7 is optional. Use C6 = 1500pF and C7 = OPEN. Use C3 = 68pF. Note that C3 may increase the loop bandwidth from previous estimated value. Figure 62 shows the simulated voltage loop gain. It is shown that it has a 75kHz loop bandwidth with a 61° phase margin and 6dB gain margin. It may be more desirable to achieve an increased gain margin. This can be accomplished by lowering R6 by 20% to 30%. In practice, ceramic cz1 R6C6 R2C3 C6 C7+ R6C6C7 R2 R3+ C3R2R3 2fcVoCoRt RoCo VoCo IoR6 RcCo fSW R6 fcR2 R6 27.3 310 50kHz 5V 22 F 150.2k == (EQ. 12) 5V 22 F C7 max 5m 22F
pin and use vias directly at the capacitor pad to tie the capacitor to the system GND plane. Place a 1µF MLCC near the A VINO pin and directly connect its return with a via to the system GND plane. components are used for SS, COMP or FSW the same advice applies. FIGURE 62. SIMULATED LOOP GAIN
The table lists the revision history for this document. March 2014 1.0 Initial release. FIGURE 63. PRINTED CIRCUIT BOARD POWER PLANES AND
ER3105DI 500mA Wide VIN Synchronous Buck RegulatorMarch 2014 Altera Corporation Package Outline Drawing L12.4x3
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 7/10 1.70 +0.10/-0.15 12 X 0.40 ±0.10 12 0.10
7 ABC M
PIN #1 INDEX AREA 6 1 2X 2.50 10X 0.50 3.30 +0.10/-0.15 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" TOP VIEW BOTTOM VIEW SIDE VIEW located within the zone indicated. The pin #1 identifier may be Unless otherwise specified, tolerance : Decimal ± 0.05 Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. Dimension applies to the metallized terminal and is measured Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. either a mold or mark feature. Dimensions are in millimeters.1. NOTES: (4X) 0.15 3.00 INDEX AREA PIN 1 4.00 B A
1.00 MAX
SEE DETAIL "X" C SEATING PLANE 0.08 C 0.10 C ( 3.30) 2.80 ( 10X 0 . 5 ) ( 12X 0.23 ) ( 1.70 ) 12 X 0.60
0.2 REFC
0 . 05 MAX. 0 . 00 MIN. Compliant to JEDEC MO-229 V4030D-4 issue E.7. 71 2