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Document overview
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- PDF pages: 24
Technical content
Features
- Up to 2A Continuous Output Current
- Integrated MOSFETs for Small Regulator Footprint
- Adjustable Switching Fre quency, 500kHz to 1.2MHz
- Tight Output V oltage Regulation, 1% Over-temperature
- Wide Input V oltage Range, 5V 10% or 5.5V to 14V
- Wide Output V oltage Range, from 0.6V
- Simple Single-Loop V oltage-Mode PWM Control Design
- Input V oltage Feed-Forward for Constant Modulator Gain
- Fast PWM Converter Transient Response
- Lossless R DS(ON) High Side and Low Side Overcurrent Protections
- Undervoltage Detection
- Integrated Thermal Shutdown Protection
- Power-Good Indication
- Adjustable Soft-Start
- Start-Up with Pre-Bias Output
- Pb-free (RoHS Compliant)
Applications
- FPGA power
- Point of Load Applications
- Graphics Cards
- ASIC Power Supplies
- Embedded Processor and I/O Supplies
- DSP Supplies VOUT ER2120QIAVINO AGND SYNC BOOT PVIN SW PGND M/S FSW POK EN SS FB COMP + VIN ENABLE POWER GOOD 5.5V TO 14V AVIN VOUT ER2120QI AVINO AGND SYNC BOOT PVIN SW PGNDM/S FSW POK EN SS FB COMP VIN ENABLE POWER GOOD 4.5V TO 5.5V AVIN
09615 March 14, 2014 Rev A
ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs March 2014 Altera Corporation
Ordering Information
(24 LD QFN) TOP VIEW *See “Functional Pin Descriptions” beginning on page 13 for pin descriptions. PART NUMBER (Note 1) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG . # ER2120QI (Notes 1, 3) 2120 -40 to +85 24 Ld 4x4 QFN L24.4x4D EVB-ER2120QI Evaluation Board NOTES: 1. These Altera Enpirion Pb-free plastic pack aged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 24 23 22 21 20 19 789 1 0 1 1 1 2 PVIN SW SW SW SW PGND POK AGND EN SYNC M/S FSW COMP FB SS PGND PGND PGND AVIN AVINO BOOT PVIN PVIN PVIN GND
FIGURE 3. STAND-ALONE REGULATOR: VIN 5.5V TO 14V FIGURE 4. STAND-ALONE REGULATOR: VIN 4.5V TO 5.5V
ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs March 2014 Altera Corporation ER2120QI With Multiple Slaved Channels ER2120QI EN FSW M/S SYNC AVINO GND MASTER SLAVE SW PVIN VOUT1 VIN RT ER2120QI EN FSW M/S SYNC GND SW PVIN VOUT2 RT SLAVE ER2120QI EN FSW M/S SYNC GND SW PVIN VOUTN RT ENABLE SS
ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs March 2014 Altera Corporation Absolute Maximum Ratings Thermal Information Recommended Operating Conditions Thermal Resistance JA (°C/W) JC (°C/W) CAUTION: Do not operate at or near the ma ximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. NOTES: 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Refer to “Block Diagram” and “Typical Application Schematics”. Operating conditions unless otherwise noted: VIN = 12V , or VAVI N = 5V ±10%, TA = -40°C to +85°C. Typical are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C PARAMETER SYMBOL TEST CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNIT S VIN SUPPLY PVIN Input V oltage Range VIN 5.5 (Note 4) (Note 5) V VIN tied to VAV I N 4.5 5.5 V Input Operating Supply Current IQ VFB = 1.0V 7 mA Input Standby Supply Current IQ_SBY EN tied to GND, VIN = 14V 1.25 2 mA SERIES REGULATOR AV I N Vo l t a g e VAV I N O VIN > 5.6V 4.5 5.0 5.5 V Maximum Output Current I AV I N O VIN = 12V 50 mA A VIN Current Limit VIN = 1 2 V, AV I N s h o r t e d t o P G N D 3 0 0 m A POWER-ON RESET Rising A VIN POR Threshold 4.2 4.4 4.49 V Falling A VIN POR Threshold 3.85 4.0 4.10 V ENABLE Rising Enable Threshold V oltage V EN_Rising 2.7 V Falling Enable Threshold V oltage V EN_Fall 2.3 V Enable Sinking Current IEN 500 µA OSCILLATOR PWM Frequency fOSC RT = 96k 400 500 600 kHz RT = 40k 960 1200 1440 kHz FSW pin tied to A VIN 800 kHz Ramp Amplitude VOSC VIN = 14V 1.0 V Ramp Amplitude VOSC VIN = 5V 0.470 V Modulator Gain VVIN/VOSC By Design 8 - Maximum Duty Cycle DMAX fOSC = 500kHz 88 % Maximum Duty Cycle D MAX fOSC = 1.2MHz 76 %
ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs March 2014 Altera Corporation REFERENCE VOLTAGE Reference V oltage VREF 0.600 V System Accuracy -1.0 +1.0 % FB Pin Bias Current ±80 ±200 nA SOFT-START Soft-Start Current ISS 20 30 40 µA Enable Soft-Start Threshold 0.8 1.0 1.2 V Enable Soft-Start Threshold Hysteresis 12 mV Enable Soft-Start V oltage High 2.8 3.2 3.8 V ERROR AMPLIFIER DC Gain 88 dB Gain-Bandwidth Product GBWP 15 MHz Maximum Output V oltage 3.9 4.4 V Slew Rate SR 5 V/µs INTERNAL MOSFETS Upper MOSFET RDS(ON) rDS_UPPER VAV I N = 5V 180 m Lower MOSFET RDS(ON) rDS_LOWER VAV I N = 5V 90 m POK POK Threshold VFB/VREF Rising Edge Hysteresis 1% 107 111 115 % Falling Edge Hysteresis 1% 86 90 93 % POK Rising Delay (Note 8) t POK_DELAY fOSC = 500kHz 1 ms POK Leakage Current VPOK = 5.5V 5 µA POK Low V oltage VPOK 0.10 V POK Sinking Current IPOK 0.5 mA PROTECTION Positive Current Limit IPOC_peak IOC from PVIN to SW (Notes 6, 7) A = 0°C to +85°C) 2.1 3.5 4.5 A IOC from PVIN to SW (Notes 6, 7) A = -40°C to +0°C) 2.0 3.4 4.0 A Negative Current Limit I NOC_peak IOC from SW to PGND (Notes 6, 7) A = 0°C to +85°C) 2.2 3.0 3.5 A IOC from SW to PGND (Notes 6, 7) A =- 4 0 ° C t o + 8 5 ° C ) 1.9 2.8 3.7 A Undervoltage Level V FB/VREF 76 80 84 % Thermal Shutdown Setpoint TSD 150 °C Thermal Recovery Setpoint TSR 130 °C Electrical Specifications Refer to “Block Diagram” and “Typical Application Schematics”. Operating conditions unless otherwise noted: VIN = 12V , or VAVI N = 5V ±10%, TA = -40°C to +85°C. Typical are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C PARAMETER SYMBOL TEST CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNIT S
- Parameters with MIN and/or MAX limits ar e 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
- Minimum V IN can operate below 5.5V as long as VAV I N is greater than 4.5V .
- Maximum V IN can be higher than 14V voltage stress across the upper and lower do not exceed 15.5V in all conditions.
- Circuit requires 150ns minimum on time to detect overcurrent condition.
- Limits established by characteri zation and are not production tested.
- POK Rising Delay is measured from the point where V OUT reaches regulation to the point where POK rises. It does not include the external
soft-start time. The POK Rising Delay specification is measured at 500kHz. COUT = 100µF + 22µF, TA = +25° C, unless otherwise noted. FIGURE 5. EFFICIENCY vs LOAD (V IN = 5V) FIGURE 6. EFFICIENCY vs LOAD (V IN = 12V) FIGURE 7. V OUT REGULATION vs LOAD (VOUT = 0.6V , 500kHz) FIGURE 8. V OUT REGULATION vs LOAD (VOUT = 1.2V , 500kHz)
FIGURE 9. V OUT REGULATION vs LOAD (VOUT = 1.5V , 500kHz) FIGURE 10. V OUT REGULATION vs LOAD (VOUT = 1.8V , 500kHz) FIGURE 11. V OUT REGULATION vs LOAD (VOUT = 2.5V , 500kHz) FIGURE 12. V OUT REGULATION vs LOAD (VOUT = 3.3V , 500kHz)
FIGURE 13. V OUT REGULATION vs LOAD (VOUT = 5V , 500kHz) FIGURE 14. POWER DISSIPA TION vs LOAD (VOUT = 0.6V , 500kHz) FIGURE 15. POWER DISSIPATION vs LOAD (VOUT = 1.2V , 500kHz) FIGURE 16. POWER DISSIPATION vs LOAD (VOUT = 1.5V , 500kHz)
FIGURE 17. POWER DISSIPATION vs LOAD (VOUT = 1.8V , 500kHz) FIGURE 18. POWER DISSIPATION vs LOAD (VOUT = 2.5V, 500kHz) FIGURE 19. POWER DISSIPATION vs LOAD (V OUT = 3.3V, 500kHz) FIGURE 20. POWER DISSIPATION vs LOAD (VOUT = 5V , 500kHz) FIGURE 21. V AV I N LOAD REGULATION FIGURE 22. V AV I N REGULATION vs VIN
FIGURE 23. MASTER TO SLA VE OPERATION FIGURE 24. MASTER OPERATION AT NO LOAD FIGURE 25. MASTER OPERATION WITH FULL LOAD FIGURE 26. MASTER OPERATION WITH NEGATIVE LOAD
FIGURE 27. SOFT-START AT NO LOAD FIGURE 28. START-UP WITH PRE-BIASED FIGURE 29. SOFT-START AT FULL LOAD FIGURE 30. POSITIVE OUTPUT SHORT CIRCUIT
reaches regulation to the point where POK rises. This delay is reversely proportional to the switching frequency. The AGND terminal of the ER2120QI provides the return path for the control and monitor portions of the IC. 100k pull-up resistor connecting to A VIN. FIGURE 31. POSITIVE OUTPUT SHORT CIRCUIT (HICCUP MODE) FIGURE 32. NEGATIVE OUTPUT SHORT CIRCUIT FIGURE 33. RECOVER FROM POSITIVE SHORT CIRCUIT FIGURE 34. LOAD TRANSIENT
ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs March 2014 Altera Corporation SYNC (Pin 4) SYNC is a bi-directional pin used to synchronize slave devices to the master device. As a master device, this pin outputs the clock signal to which the slave devices synchronize. As a slave device, this pin is an input to receive the clock signal from the master device. If configured as a slave device, the ER2120QI is disabled if there is no clock signal from the master device on the SYNC pin. Leave this pin unconnected if the IC is used in stand-alone operation. M/S (Pin 5) As a slave device, tie a 5k resistor between the M/S pin and ground. As a master or a stand-alone device, tie the M/S pin directly to the A VIN pin. Do not short the M/S pin to GND. FSW (Pin 6) The FSW pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from the FSW pin to GND, the switching frequency can be programmed as desired between 500kHz and 1.2MHz as shown in Equation 1. Tying the FSW pin to the A VIN pin forces the switching frequency to 800kHz. Using resistors with values below 40k (1.2MHz) or with values higher than 97k (500kHz) may damage the ER2120QI. COMP (Pin 7) and FB (Pin 8) The switching regulator employs a single voltage control loop. The FB pin is the negative input to the voltage loop error amplifier. The output voltage is set by an external resistor divider connected to FB. With a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. Loop compensation is achieved by connecting an AC network across the COMP pin and the FB pin. The FB pin is also monitored for undervoltage events. SS (Pin 9) Connect a capacitor from the SS pin to ground. This capacitor, along with an internal 30µA current source, sets the soft-start interval of the converter, tSS, as shown in Equation 2. PGND (Pins 10-13) The PGND pins are used as the ground connection of the power train. SW (Pins 14-17) The SW pins are the SW node connections to the inductor. These pins are connected to the source of the control MOSFET and the drain of the synchronous MOSFET. PVIN (Pins 18-21) Connect the input rail to the PVIN pins. These pins are the input to the regulator as well as the source for the internal linear regulator that supplies the bias for the IC. It is recommended that the DC voltage applied to the PVIN pins does not exceed 14V . This recommendation allows for transient spikes and voltage ringing to occur while not exceeding Absolute Maximum Ratings. BOOT (Pin 22) The BOOT pin provides ground-referenced bias voltage to the upper MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive the internal N-channel MOSFET. The boot diode is included within the ER2120QI. RT k 48000 CSS F 50 t SS S= (EQ. 2)
ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs March 2014 Altera Corporation A VINO (Pin 23) The A VINO pin is the output of the internal linear regulator that supplies the bias and gate voltage for the IC. A minimum 4.7µF decoupling capacitor is recommended. A VIN (Pin 24) The A VIN pin supplies the bias voltage for the IC. This pin should be tied to the A VINO pin through an RC low pass filter. A 10 resistor and 0.1µF capacitor are recommended.
ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs March 2014 Altera Corporation Block Diagram GATE DRIVE AND ADAPTIVE SHOOT THRU PROTECTION POK SS FB BOOT SW (x4) OC MONITOR SYNC M/S AGND EN FSW COMP AVINO CLOCK AND OSCILLATOR GENERATOR PVIN SERIES REGULATOR 0.6V REFERENCE AVINO VOLTAGE MONITOR PVIN (x4) AVINO PGND (x4) OC MONITOR 30A AVIN BIAS FAULT MONITORING POR MONITOR
ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs March 2014 Altera Corporation Functional Description Initialization The ER2120QI automatically initializes upon receipt of input power. The Power-On Reset (POR) function continuously monitors the voltage on the A VIN pin. If the voltage on the EN pin exceeds its rising threshold, then the POR function initiates soft-start operation after the bias voltage has exceeded the POR threshold. Stand-alone Operation The ER2120QI can be configured to function as a stand-alone single channel voltage mode synchronous buck PWM voltage regulator. The “Typical Application Schematics” on page 3 show the two configurations for stand-alone operation. The internal series linear regulator requires at least 5.5V to create the proper bias for the IC. If the input voltage is between 5.5V and 15V , simply connect the PVIN pins to the input rail, and the series linear regulator creates the bias for the IC. The A VIN pin should be tied to a capacitor for decoupling. If the input voltage is 5V 10%, then tie the PVIN pins and the A VIN pin to the input rail. The ER2120QI uses the 5V rail as the bias. A decoupling capacitor should be placed as close as possible to the A VIN pin. Multi-Channel (Master/Slave) Operation The ER2120QI can be configured to function in a multi-channel system. “ER2120QI With Multiple Slaved Channels” on page 4 shows a typical configuration for the multi-channel system. In the multi-channel system, each ER2120QI IC regulates a separate rail while sharing the same input rail. By configuring the devices in a master/slave configuration, the clocks of each IC can be synchronized. There can only be one master IC in a multi-channel system. To configure an IC as the master, the M/S pin must be shorted to the A VIN pin. The SYNC pins of all the ER2120QI controller ICs in the multi-channel system must be tied together. The frequency set resistor value (RT) used on the master device must be used on every slave device. Each slave device must have a 5kresistor connecting it from M/S pin to ground. The master device and all slave devices can have their EN pins tied to an enable “bus.” Since the EN pin is bi-directional, it allows for options on how each IC is tied to the enable bus. If the EN pin of any ER2120QI is tied directly to the enable bus, then that device is capable of disabling all the other devices that have their EN pins tied directly to the enable bus. If the EN pin of an ER2120QI is tied to the enable bus through a diode (anode tied to ER2120QI EN pin, cathode tied to enable bus), then the part does not disable other devices on the enable bus if it disables itself for any reason. If the master device is disabled via the EN pin, it continues to send the clock signal from the SYNC pin. This allows slave devices to continue operating. Fault Protection The ER2120QI monitors the output of the regulator for overcurrent and undervoltage events. The ER2120QI also provides protection from excessive junction temperatures. OVERCURRENT PROTECTION The overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through both the upper and lower MOSFETs. Upon detection of any overcurrent condition, the upper MOSFET is immediately turned off and is not turned on again until the next switching cycle. Upon detection of the initial overcurrent condition, the Overcurrent Fault Counter is set to 1, and the Overcurrent Condition Flag is set from LOW to HIGH. If, on the subsequent cycle, another overcurrent condition is detected, the OC Fault Counter is incremented. If there are eight sequential OC fault detections, the regulator is shut down under an Overcurrent Fault Condition, and the EN pin is pulled LOW. An Overcurrent Fault Condition results, with the regulator attempting to restart in hiccup mode. The delay between restarts is four soft-start periods. At the end of the fourth soft-start wait period, the fault counters are reset, the EN pin is released, and soft-start is attempted again. If the overcurrent condition goes away prior to the OC Fault Counter reaching a count of four, the Overcurrent Condition Flag is set back to LOW. If the Overcurrent Condition Flag is HIGH, the Overcurrent Fault Counter is less than four, and an undervoltage event is detected, the regulator shuts down immediately.
ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs March 2014 Altera Corporation UNDERVOLTAGE PROTECTION If the voltage detected on the FB pin falls 18% below the internal reference voltage, and if the overcurrent condition flag is LOW, then the regulator is shut down immediately under an Undervoltage Fault Condition, and the EN pin is pulled LOW. An Undervoltage Fault Condition results in the regulator attempting to restart in hiccup mode, with the delay between restarts being four soft-start periods. At the end of the fourth soft-start wait period, the fault counters are reset, the EN pin is released, and soft- start is attempted again. THERMAL PROTECTION If the ER2120QI IC junction temperature reaches a nominal temperature of +150°C, the regulator is disabled. The ER2120QI does not re-enable the regulator until the junction temperature drops below +130°C. SHOOT-THROUGH PROTECTION A shoot-through condition occurs when both the upper and lower MOSFETs are turned on simultaneously, effectively shorting the input voltage to ground. To protect from a shoot-through condition, the ER2120QI incorporates specialized circuitry, which ensures that the complementary MOSFETs are not ON simultaneously. Application Guidelines Operating Frequency The ER2120QI can operate at switching frequencies from 500kHz to 1.2MHz. A resistor tied from the FSW pin to ground is used to program the switching frequency (Equation 3). Output V oltage Selection The output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier (see Figure 36). The output voltage programming resistor, R4, depends on the value chosen for the feedback resistor and the desired output voltage of the regulator. The value for the feedback resistor is typically between 1k and 10k. If the output voltage desired is 0.6V , then R4 is left unpopulated. Output Capacitor Selection An output capacitor is required to filter the inductor current and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. The shape of the output voltage waveform during a load transient that represents the worst-case loading conditions ultimately determines the number of output capacitors and their type. When this load transient is applied to the converter, most of the energy required by the load is initially delivered from the output capacitors. This is due to the finite amount of time required for the inductor current to slew up to the level of the output current required by the load. This phenomenon results in a temporary dip in the output voltage. At the very edge of the transient, the Equivalent Series Inductance (ESL) of each capacitor induces a spike that adds on top of the existing voltage drop due to the Equivalent Series Resistance (ESR). RT k 48000 R1 0.6V
consequence of the amount of capacitance on the output. output. Figure 35 shows a typical response to a load transient. The amplitudes of the different types of voltage excursions can be approximated using Equation 5. where: Itran = Output Load Current Transient, and Cout = Total Output Capacitance. increased. In this situation, a trade-off between output inductance and output capacitance may be necessary. The ESL of the capacitors, which is an important parameter in the previous equations, is not usually listed in databooks. where fres is the frequency at which the lowest impedance is achieved (resonant frequency). FIGURE 35. TYPICAL TRANSIENT RESPONSE
ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs March 2014 Altera Corporation Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and to minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current, and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by using Equation 8: Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter response time to a load transient. One of the parameters limiting conve rter response to a load transient is the time required to change the inductor current. Give n a sufficiently fast control loop design, the ER2120QI provides either 0% or 100% duty cycle in response to a load transient. Th e response time is the time required to slew the inductor current from an initial current value to the transient current level. D uring this interval, the difference between the inductor current and the tr ansient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. Equation 9 gives the approximate response time interval for application and removal of a transient load: where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst-case response time can be either at the application or removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst-case response time. Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high- frequency decoupling, and bulk capacitors to supply the current needed each time the upper MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of the upper MOSFET and the source of the lower MOSFET. The important parameters for bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. Their voltage rating should be at least 1.25x greater than the maximum input voltage, while a voltage rating of 1.5x is a conservative guideline. For most cases, the RMS current rating requirement for the input capacitor of a buck regulator is approximately one-half the DC load current. The maximum RMS current through the input capacitors can be closely approximated using Equation 10: For a through-hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge current at power-up. Some capacitor series available from reputable manufacturers are surge current tested. Feedback Compensation Figure 36 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the reference voltage level. The error amplifier output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VPVIN at the SW node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR. The DC gain of the modulator is simply the input voltage (VPVIN) divided by the peak-to-peak oscillator voltage, DVOSC. The ER2120QI incorporates a feed-forward loop that accounts for changes in the input voltage. This configuration maintains a constant modulator gain. DI = VIN - VOUT FSW x L VOUT VIN DVOUT = DI x ESRx (EQ. 8) tRISE = L x ITRAN VIN - VOUT tFALL = L x ITRAN VOUT (EQ. 9) VOUT VPVIN 2 1 VOUT VPVIN 1 IN VOUT– VPVIN (EQ. 10)
The compensation network consists of the error amplifier (internal to the ER2120QI) and the impedance networks, ZIN and ZFB.
- Pick Gain (R 2/R1) for desired converter bandwidth.
- Place first zero below filter’s double pole (~75% FLC).
- Place second zero at filter’s double pole.
- Place first pole at ESR Zero.
- Place second pole at half the switching frequency.
- Check gain against error amplifier’s open-loop gain.
- Estimate phase margin; repeat if necessary.
FIGURE 36. VOLTAGE-MODE BUCK CONVERTER COMPENSATION
compensation transfer function and plotting the gain. component variations when determining phase margin. device overvoltage stress. Careful component layout and printed circuit board design minimize these voltage spikes. of the critical components, and short, wide traces minimize the magnitude of voltage spikes. components, which connect to sensitive nodes or supply critical bypass current and signal coupling. A multi-layer printed circuit board is recommended. Figure 38 shows the connections of the critical components in the converter. FIGURE 37. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
the load. Make the PGND and the output capacitors as short as possible. as possible to the FB pin, with vias tied straight to the ground plane as required. The table lists the revision history for this document. FIGURE 38. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS March 2014 1.0 Initial release.
ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs March 2014 Altera Corporation Package Outline Drawing L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
0 . 90 ± 0 . 1 5C 0 . 2 REF TYPICAL RECOMMENDED LAND PATTERN 0 . 05 MAX.( 24X 0 . 6 ) DETAIL "X" ( 24X 0 . 25 ) 0 . 00 MIN. ( 20X 0 . 5 ) ( 2 . 50 ) SIDE VIEW ( 3 . 8 TYP ) BASE PLANE TOP VIEW BOTTOM VIEW 712 24X 0 . 4 ± 0 . 1 4.00 PIN 1 18INDEX AREA 2419 4.00 2.5 0.5020X SEE DETAIL "X" - 0 . 05 + 0 . 0724X 0 . 23 2 . 50 ± 0 . 15 PIN #1 CORNER (C 0 . 25) SEATING PLANE 0.08 C 0.10 C C
0.10 M C A B
A B (4X) 0.15 located within the zone indicated. The pin #1 identifier may be Unless otherwise specified, tolerance : Decimal ± 0.05 Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. Dimension b applies to the metallized terminal and is measured Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. either a mold or mark feature. Dimensions are in millimeters.1. NOTES: