EPXA1

EPXA1 ALTERA | Alldatasheet

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DS-EXCARM-2.0 Altera Corporation 1 Excalibur Device Overview May 2002, ver. 2.0 Data Sheet Features... I Combination of a world-class RISC processor system with industry- leading programmable logic on a single device I Industry-standard ARM922T™ 32-bit RISC processor core operating at up to 200 MHz – ARMv4T instruction set with Thumb ® extensions – Memory management unit (MMU) included for real-time operating system (RTOS) support – Harvard cache architecture with 64-way set associative separate 8-Kbyte instruction and 8-Kbyte data caches I APEX™ 20KE-like programmable logic architecture ranging from 100,000 to 1,000,000 gates (see Table 1 on page 3) I Advanced bus architecture based on advanced microcontroller bus architecture (AMBA™ ) high-performance bus (AHB) I Embedded programmable on-chip peripherals – ETM9 embedded trace module to assist software debugging – Flexible interrupt controller – Universal asynchronous receiver/transmitter (UART) – General-purpose timer – Watchdog timer I Advanced memory support – Internal single-port SRAM up to 256 Kbytes – Internal dual-port SRAM up to 128 Kbytes – Internal SDRAM controller - Single data-rate (SDR) and double data-rate (DDR) support - Up to 512 Mbytes - Data rates to 133 (266) MHz – Expansion bus interface (EBI) - Compatible with industry-standard flash memory, SRAMs, and peripheral devices - Four devices, each up to 32 Mbytes I PLD configuration/reconfiguration possible via the embedded processor software I Fully configurable memory map I Extensive embedded system debug facilities – SignalTap ™ embedded logic analyzer – ARM® JTAG processor debug support – Real-time data/instruction processor trace – Background debug monitoring via the IEEE Std. 1149.1 (JTAG) interface

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I Multiple and separate clock domains controlled by software- programmable phased-lock loops (PLLs) for embedded processor, SDRAM, and PLD – ClockBoost ™ circuitry provides clock multiplication for the embedded stripe and the PLD – ClockLock™ circuitry reduces clock delay and skew in the PLD I Advanced packaging options (see Tables 2 and 3 on page 3) I 1.8-V supply voltage, but many I/O standards supported: – SSTL-3 – LVTTL – GTL+ – LVDS I SOPC Builder system development tool – Intuitive graphical user interface (GUI) simplifies system definition and customization – Wizard interface facilitates function customization for each component – Automatically-generated logic integrates processors, memories, peripherals, IP cores, on-chip buses and bus arbiters – VHDL or Verilog HDL code created for system connection – Software develoment environment generated to match the target hardware I Extended Quartus™ II development environment for Excalibur™ support – Integrated hardware and software development environment – MegaWizard ® Plug-In interface configures the embedded processor, PLD, bus connections, and peripherals – C/C++ compiler, source-level debugger, and RTOS support /G6This document provides updated information about Excalibur devices and should be used together with the APEX 20K Programmable Logic Device Family Data Sheet.

(1) I/O counts include dedicated input and clock pins. Table 1. Excalibur Device Overview Table 2. Excalibur Device FineLine™ BGA Package Sizes

484 Pin 672 Pin 1,020 Pin

Table 3. Excalibur Device FineLine BGA Package Options & User I/O

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Description

Devices belonging to the Excalibur family combine an unparalleled degree of integration and programmability. They offer an outstanding embedded system development platform, providing a cost-efficient access to leading-edge embedded processors and PLD performance. The Excalibur family offers a variety of PLD densities and memory sizes to fit a wide range of applications and requirements. The high- performance embedded architecture is ideal for compute-intensive as well as high data-bandwidth applications. Figure 1 shows the structure of the Excalibur devices. The embedded stripe contains the processor core, peripherals, and memory subsystem. The amounts of single- and dual-port memory vary as listed in Table 1 on page 3. Figure 2 on page 5 shows the system architecture of the embedded stripe and the interfaces to the PLD portion of the devices. This architecture promotes maximum integration with minimal system cost and allows the embedded stripe and PLD to be independently optimized for maximum performance. Figure 1. Excalibur Architecture

128 Kbytes SRAM

64 Kbytes DPRAM

32 Kbytes SRAM

16 Kbytes DPRAM

256 Kbytes SRAM

128 Kbytes DPRAM

Figure 2. Excalibur System Architecture

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Two AMBA-compliant AHBs ensure that the embedded processor activity is unaffected by peripheral and memory operation. Three bidirectional AHB-to-AHB bridges enable embedded peripherals and PLD-implemented peripherals to exchange data with the embedded processor or with other peripherals. The Excalibur family is supported by the following development tools: I SOPC Builder from Altera® I Quartus II from Altera I ADS, GNUPro and other third-party tools Functional The Excalibur system architecture (embedded processor bus structure, on-chip memory, and peripherals) combines the performance advantages of ASIC integration with the flexibility and time-to-market advantages of PLDs. The Embedded Processor The ARM922T is a member of the ARM9 family of processor cores. Its Harvard architecture, implemented using a five-stage pipeline, allows single clock-cycle instruction operation through simultaneous fetch, decode, execute, memory, and write stages. Figure 3 on page 7 shows the Excalibur embedded processor, the ARM922T.

Figure 3. ARM922T Embedded Processor Internal Organization

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minimal time but with maximum customization. entire 4-Gbyte address range (32-bit address bus). implemented in their systems. The embedded stripe contains both single-port and dual-port SRAM. bus master while the other block is accessed by the other bus master. 2 × 128 Kbytes. Each single-port SRAM block is byte-addressable. Table 1. Byte, half-word and word accesses are allowed and are reads is controlled by the system endianness.

In addition, there are either one or two blocks of dual-port SRAM in the embedded stripe, depending on the device type. The outputs of the dual-port memories can be registered. One of the ports gives dedicated access to the PLD; the other port can be configured for access by AHB masters or by the PLD. The width of the data port to the PLD is configurable as ×8, ×16, or ×32 bits. For the larger devices, the dual-port SRAM blocks can be combined to form a ×64-bit data- width interface. This allows the designer to build deeper and wider memories and multiplex the data outputs within the stripe. External Memory Controllers The Excalibur family provides two embedded memory controllers that can be accessed by any of the bus masters: one for external SDRAM, and a second for external flash memory or SRAM. The SDRAM memory controller supports the following commonly- available memory standards, without the addition of any logic: I Single-data rate (SDR) 133-MHz data rates I Double-data rate (DDR) 266-MHz data rates An embedded stripe PLL supplies the appropriate timing to the SDRAM memory controller subsystem. Users can program the frequency to match the chosen memory components. The EBI supports the interface to system ROM, allowing external flash memory access and reprogramming. In addition, static RAM and simple peripherals can be connected to this interface externally. Embedded Peripherals A single 16-Kbyte memory region in the embedded stripe contains configuration and control registers, plus status and control registers for the embedded peripherals. The region contains the following modules: I Configuration Registers I Embedded Stripe PLLs I UART I Timer I Watchdog timer I General Purpose I/O Port I Interrupt controller

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In a co-development environment where both the hardware and software components constitute an integral part of the embedded processor PLD design process, Altera provides seamless support with SOPC Builder and Quartus II; ADS, GNUPro and third-party development tools are also available. /G21See the Altera web site, http://www.altera.com, for details of the software development tools. /G6Excalibur devices are compatible with any available tools for the ARM922T from ARM or third parties. SOPC Builder SOPC Builder allows embedded system designers to create system- on-a-programmable-chip (SOPC) designs in a fraction of the time traditionally required for embedded system-on-chip (SOC) design. It provides an intuitive GUI that simplifies the definition and customization of a user’s system. Designers select and parameterize IP blocks from a drop-down list of communication, digital signal processing (DSP), microprocessor, and bus interface cores. Then SOPC Builder automatically generates all of the logic necessary to integrate them and also uses the specified system information to create appropriate VHDL or Verilog HDL code to connect the system components together, resulting in an HDL description of the entire system. SOPC Builder automatically generates a software development environment that matches the target hardware, saving days or weeks of software design time, and jump-starts software development with components such as the following: I Header files that define memory maps, interrupt priorities and data structures corresponding to each hardware peripheral I Routines to access hardware peripherals in the system I OS/RTOS kernels with appropriate hardware drivers SOPC Builder automatically generates a simulation model of the system, a test bench for the system, and a full environment for immediate system simulation. Figure 4 on page 11 shows an example of an SOPC Builder screen.

Figure 4. Sample SOPC Builder Screen using SignalTap logic analyzer.

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UNIX workstation-based electronic design automation (EDA) tools. Figure 5 shows the Quartus II development tool flow. Figure 5. Quartus II Development Tool Flow

Altera supplies a variety of embedded software functions to support flash memory programming and PLD configuration. Configuration Excalibur devices are configured at system power-up with data stored in a configuration device or flash memory. The same memory can store application software for the embedded processor. The user can reconfigure the device in-circuit by using the on-chip processor, using configuration data stored anywhere in its memory system. The user can make real-time changes during system operation, which enables innovative reconfigurable computing applications. Simulation Model Initial simulation models of the ARM922T are compatible with the following simulators: I Quartus II simulator I Cadence NC-Verilog and NC-VHDL simulators I ModelSim simulator I Synopsys VCS simulator Trace A trace port provided on the ETM9 is compatible with the external trace analysis tools. This feature allows real-time visibility of embedded processor execution, and is tightly integrated with the source-level debugging tools. Excalibur Development Kit Altera offers separately an Excalibur development kit, which includes a development board compatible with the EPXA10 device. Figure 6 on page 14 illustrates the Altera Excalibur development board, showing the provision for board expansion.

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Figure 6. Excalibur Development Board

Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera ’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com Excalibur Device Overview

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Revision History This document provides updated information as described below. Version 2.0 This version provides updated information, including: I Device features and package sizes I Functional description I Software development tools I Excalibur development boards Version 1.2 This version provides updated information, including: I Operating speed and other device features I Updated system architecture (Figure 2) I Minor textual changes Version 1.1 This version provides updated information, including: I Revised maximum amount of external SDRAM supported I Minor formatting and textual changes