EPM9480

EPM9320LI84-20 ALTERA | Alldatasheet

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Technical content

■ 5.0-V in-system programmability (ISP) through built-in IEEE Std.

1149.1 Joint Test Action Group (JTAG) interface

144 MHz

Table 1. MAX 9000 Device Features

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MAX 9000 Programmable Logic Device Family Data Sheet ...and More

Features

■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls ■ Programmable security bit for protection of proprietary designs ■ Software design support and automatic place-and-route provided by Altera’s MAX+PLUS ® II development system on Windows-based PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest ■ Programming support with Altera’s Master Programming Unit (MPU), BitBlasterTM serial download cable, ByteBlasterTM parallel port download cable, and ByteBlasterMVTM parallel port download cable, as well as programming hardware from third-party manufacturers ■ Offered in a variety of package options with 84 to 356 pins (see Table 2) Notes: (1) MAX 9000 device package types include plastic J-lead chip carrier (PLCC), power quad flat pack (RQFP), ceramic pin-grid array (PGA), and ball-grid array (BGA) packages. (2) Perform a complete thermal analysis before committing a design to this device package. See Application Note 74 (Evaluating Power for Altera Devices) . Table 2. MAX 9000 Package Options & I/O Counts Note (1)

MAX 9000 Programmable Logic Device Family Data Sheet General

Description

The MAX 9000 family of in-system-programmable, high-density, high- performance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROM- based MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed grade of the MAX 9000 family is compliant with the PCI Local Bus Specification, Revision 2.2. Table 3 shows the speed grades available for MAX 9000 devices. Table 4 shows the performance of MAX 9000 devices for typical functions. Note: (1) Internal logic array block (LAB) performance is shown. Numbers in parentheses show external delays from row input pin to row I/O pin. The MAX 9000 architecture supports high-density integration of system- level logic functions. It easily integrates multiple programmable logic devices ranging from PALs, GALs, and 22V10s to field-programmable gate array (FPGA) devices and EPLDs. Table 3. MAX 9000 Speed Grade Availability Table 4. MAX 9000 Performance Note (1)

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MAX 9000 Programmable Logic Device Family Data Sheet All MAX 9000 device packages provide four dedicated inputs for global control signals with large fan-outs. Each I/O pin has an associated I/O cell register with a clock enable control on the periphery of the device. As outputs, these registers provide fast clock-to-output times; as inputs, they offer quick setup times. MAX 9000 EPLDs provide 5.0-V in-system programmability (ISP). This feature allows the devices to be programmed and reprogrammed on the printed circuit board (PCB) for quick and efficient iterations during design development and debug cycles. MAX 9000 devices are guaranteed for 100 program and erase cycles. MAX 9000 EPLDs contain 320 to 560 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. For increased flexibility, each macrocell offers a dual-output structure that allows the register and the product terms to be used independently. This feature allows register-rich and combinatorial- intensive designs to be implemented efficiently. The dual-output structure of the MAX 9000 macrocell also improves logic utilization, thus increasing the effective capacity of the devices. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and high-speed parallel expander product terms to provide up to 32 product terms per macrocell. The MAX 9000 family provides programmable speed/power optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the user to configure one or more macrocells to operate at 50% or less power while adding only a nominal timing delay. MAX 9000 devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. MAX 9000 devices offer the MultiVolt feature, which allows output drivers to be set for either 3.3-V or 5.0-V operation in mixed- voltage systems.

MAX 9000 Programmable Logic Device Family Data Sheet The MAX 9000 family is supported by Altera’s MAX+PLUS II development system, a single, integrated software package that offers schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX- workstation-based EDA tools. The MAX+PLUS II software runs on Windows-based PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. f For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet. Functional MAX 9000 devices use a third-generation MAX architecture that yields both high performance and a high degree of utilization for most applications. The MAX 9000 architecture includes the following elements: ■ Logic array blocks ■ Macrocells ■ Expander product terms (shareable and parallel) ■ FastTrack Interconnect ■ Dedicated inputs ■ I/O cells Figure 1 shows a block diagram of the MAX 9000 architecture.

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Figure 1. MAX 9000 Device Block Diagram path of the FastTrack Interconnect. clear that can be used for register control signals in all 16 macrocells.

or column interconnect, signals can traverse to other LABs or to the IOCs. Figure 2. MAX 9000 Logic Array Block

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terms, the product-term select matrix, and the programmable register. combinatorial logic operation. See Figure 3. Figure 3. MAX 9000 Macrocell & Local Array allocation according to the logic requirements of the design.

16 Local

33 Row

MAX 9000 Programmable Logic Device Family Data Sheet For registered functions, each macrocell register can be individually programmed for D, T, JK, or SR operation with programmable clock control. The flipflop can also be bypassed for combinatorial operation. During design entry, the user specifies the desired register type; the MAX+PLUS II software then selects the most efficient register operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes: ■ By either global clock signal. This mode achieves the fastest clock-to- output performance. ■ By a global clock signal and enabled by an active-high clock enable. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. ■ By an array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. Two global clock signals are available. As shown in Figure 2, these global clock signals can be the true or the complement of either of the global clock pins (DIN1 and DIN2). Each register also supports asynchronous preset and clear functions. As shown in Figure 3, the product-term select matrix allocates product terms to control these operations. Although the product-term-driven preset and clear inputs to registers are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the dedicated global clear pin (DIN3). The global clear can be programmed for active-high or active-low operation. All MAX 9000 macrocells offer a dual-output structure that provides independent register and combinatorial logic output within the same macrocell. This function is implemented by a process called register packing. When register packing is used, the product-term select matrix allocates one product term to the D input of the register, while the remaining product terms can be used to implement unrelated combinatorial logic. Both the registered and the combinatorial output of the macrocell can feed either the FastTrack Interconnect or the LAB local array.

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logic resources to obtain the fastest possible speed. expanders can feed multiple macrocells. Figure 4. MAX 9000 Shareable Expanders

16 Shared

Shareable expanders can be shared by any or all macrocells in the LAB.

neighboring macrocell to implement fast, complex logic functions. 15 parallel expanders provided by neighboring macrocells in the LAB. Figure 5. MAX 9000 Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell.

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MAX 9000 Programmable Logic Device Family Data Sheet The MAX+PLUS II Compiler automatically allocates as many as three sets of up to five parallel expanders to macrocells that require additional product terms. Each set of expanders incurs a small, incremental timing delay (t PEXP). For example, if a macrocell requires 14 product terms, the Compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms and the second set includes four product terms, increasing the total delay by 2 × t PEXP. Two groups of eight macrocells within each LAB (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lower- numbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can only lend parallel expanders and the highest-numbered macrocell can only borrow them. FastTrack Interconnect In the MAX 9000 architecture, connections between macrocells and device I/O pins are provided by the FastTrack Interconnect, a series of continuous horizontal and vertical routing channels that traverse the entire device. This device-wide routing structure provides predictable performance even in complex designs. In contrast, the segmented routing in FPGAs requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. Figure 6 shows the interconnection of four adjacent LABs with row and column interconnects.

Figure 6. MAX 9000 Device Interconnect Resources Each LAB is named on the basis of its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device. Table 5. MAX 9000 Rows & Columns

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Figure 7. MAX 9000 LAB Connections to Row & Column Interconnect

96 Row Channels

48 Column

macrocell drives row channel.

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Figure 9. MAX 9000 Column-to-IOC Connections typically used for global clock, clear, and output enable control signals. FastTrack Interconnect (see Figure 2 on page 7). ends of the row and column interconnect channels.

Figure 10. MAX 9000 IOC output register for data that requires fast clock-to-output performance. control-signal paths are designed to minimize the skew across the device. clock signals, up to six clock enable signals, and up to two clear signals. how the IOC control signals share the peripheral bus.

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slew rate control affects both rising and falling edges of the output signals. The VCCINT pins must always be connected to a 5.0-V power supply. therefore compatible with 3.3-V and 5.0-V inputs. Table 6. Peripheral Bus Sources

MAX 9000 Programmable Logic Device Family Data Sheet The VCCIO pins can be connected to either a 3.3-V or 5.0-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 5.0-V power supply, the output levels are compatible with 5.0-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is at 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with V CCIO levels lower than 4.75 V incur a nominally greater timing delay of tOD2 instead of tOD1. In-System Programma- bility (ISP) MAX 9000 devices can be programmed in-system through a 4-pin JTAG interface. ISP offers quick and efficient iterations during design development and debug cycles. The MAX 9000 architecture internally generates the 12.0-V programming voltage required to program EEPROM cells, eliminating the need for an external 12.0-V power supply to program the devices on the board. During ISP, the I/O pins are tri-stated to eliminate board conflicts. ISP simplifies the manufacturing flow by allowing the devices to be mounted on a printed circuit board with standard pick-and-place equipment before they are programmed. MAX 9000 devices can be programmed by downloading the information via in-circuit testers, embedded processors, or the Altera BitBlaster, ByteBlaster, or ByteBlasterMV download cable. (The ByteBlaster cable is obsolete and has been replaced by the ByteBlasterMV cable, which can interface with 2.5-V, 3.3-V, and 5.0-V devices.) Programming the devices after they are placed on the board eliminates lead damage on high pin-count packages (e.g., QFP packages) due to device handling. MAX 9000 devices can also be reprogrammed in the field (i.e., product upgrades can be performed in the field via software or modem). In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. Because some in-circuit testers platforms have difficulties supporting an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm have an “F” suffix in the ordering code.

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MAX 9000 Programmable Logic Device Family Data Sheet Programming Sequence During in-system programming, instructions, addresses, and data are shifted into the MAX 9000 device through the TDI input pin. Data is shifted out through the TDO output pin and compared against the expected data. Programming a pattern into the device requires the following six ISP stages. A stand-alone verification of a programmed pattern involves only stages 1, 2, 5, and 6. 1. Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1m s . 2. Check ID. Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time. 3. Bulk Erase. Erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms. 4. Program. Programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells. This process is repeated for each EEPROM address. 5. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address. 6. Exit ISP. An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. The exit ISP stage requires 1m s . Programming Times The time required to implement each of the six programming stages can be broken into the following two elements: ■ A pulse time to erase, program, or read the EEPROM cells. ■ A shifting time based on the test clock (TCK) frequency and the number of TCK cycles to shift instructions, address, and data into the device.

MAX 9000 Programmable Logic Device Family Data Sheet By combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the TCK frequency, the number of devices, and specific target device(s). Because different ISP-capable devices have a different number of EEPROM cells, both the total fixed and total variable times are unique for a single device. Programming a Single MAX 9000 Device The time required to program a single MAX 9000 device in-system can be calculated from the following formula: where: t PROG = Programming time tPPULSE = Sum of the fixed times to erase, program, and verify the EEPROM cells CyclePTCK =N u m b e r o f TCK cycles to program a device fTCK = TCK frequency The ISP times for a stand-alone verification of a single MAX 9000 device can be calculated from the following formula: where: tVER =V e r i f y t i m e tVPULSE = Sum of the fixed times to verify the EEPROM cells CycleVTCK =N u m b e r o f TCK cycles to verify a device tPROG tPPULSE Cycle PTC K fTCK tVER tVPULSE Cycle VTC K fTCK

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with the worst-case method using the ISP algorithm. verification times for several common test clock frequencies. Table 7. MAX 9000 tPULSE & CycleTCK Values Table 8. MAX 9000 In-System Programming Times for Different Test Clock Frequencies

10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz

Table 9. MAX 9000 Stand-Alone Verification Times for Different Test Clock Frequencies

f For more information, see the Altera Programming Hardware Data Sheet. MAX 9000 device with the results of simulation. manufacturers also provide programming support for Altera devices. f For more information, see Programming Hardware Manufacturers. MAX 9000 devices support JTAG BST circuitry as specified by IEEE Std. not required, the JTAG pins are available as user I/O pins. Table 10. MAX 9000 JTAG Instructions normal device operation, and permits an initial data pattern output at the device pins. pattern at the output pins and capturing test results at the input pins. be shifted out of TDO serially. This instruction is supported by MAX 9000A devices only.

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information for MAX 9000 devices. (1) The IDCODE’s least significant bit (LSB) is always 1. (2) The most significant bit (MSB) is on the left. the EPM9320 and EPM9560 devices do not. Figure 11 shows the timing requirements for the JTAG signals. Table 11. MAX 9000 Boundary-Scan Register Length Table 12. 32-Bit MAX 9000 Device IDCODE Note (1)

Figure 11. MAX 9000 JTAG Waveforms Table 13. JTAG Timing Parameters & Values for MAX 9000 Devices

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reset only when the device is erased. erased during the early stages of the production flow. Figure 12. MAX 9000 AC Test Conditions observable noise immunity can result. for 5.0-V devices or outputs.

capacitance for MAX 9000 devices. Table 14. MAX 9000 Device Absolute Maximum Ratings Note (1) Table 15. MAX 9000 Device Recommended Operating Conditions

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Table 16. MAX 9000 Device DC Operating Conditions Notes (5), (6) Table 17. MAX 9000 Device Capacitance: EPM9320, EPM9400, EPM9480 & EPM9560 Devices Note (10) Table 18. MAX 9000A Device Capacitance: EPM9320A & EPM9560A Devices Note (10) Table 19. MAX 9000 Device Typical ICC Supply Current Values

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MAX 9000 Programmable Logic Device Family Data Sheet Timing Model The continuous, high-performance FastTrack Interconnect ensures predictable performance and accurate simulation and timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and hence have unpredictable performance. Timing simulation and delay prediction are available with the MAX+PLUS II Simulator and Timing Analyzer, or with industry- standard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer provides point- to-point timing delay information, setup and hold time prediction, and device-wide performance analysis. The MAX 9000 timing model in Figure 14 shows the delays that correspond to various paths and functions in the circuit. This model contains three distinct parts: the macrocell, IOC, and interconnect, including the row and column FastTrack Interconnect and LAB local array paths. Each parameter shown in Figure 14 is expressed as a worst-case value in the internal timing characteristics tables in this data sheet. Hand- calculations that use the MAX 9000 timing model and these timing parameters can be used to estimate MAX 9000 device performance. f For more information on calculating MAX 9000 timing delays, see Application Note 77 (Understanding MAX 9000 Timing).

Figure 14. MAX 9000 Timing Model

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Tables 21 through 24 show timing for MAX 9000 devices. Table 21. MAX 9000 External Timing Characteristics Note (1)

Table 22. MAX 9000 Internal Timing Characteristics Note (1)

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Table 23. IOC Delays

parameter applies for both global and array clocking as well as both macrocell and I/O cell registers. (4) Measured with a 16-bit loadable, enabled, up/down counter programmed in each LAB. The tLPA parameter must be added to the tLOCAL parameter for macrocells running in low-power mode . or timing analysis is required to determine actual worst-case performance. depends on the switching frequency and the application logic. Table 24. Interconnect Delays

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pattern in the device and the environmental operating conditions. Table 25. MAX 9000 ICC Equation Constants

Figure 15. ICC vs. Frequency for MAX 9000 Devices (Part 1 of 2)

118 MHz

144 MH z

42 MHz

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Figure 15. ICC vs. Frequency for MAX 9000 Devices (Part 2 of 2)

42 MHz 59 MHz

Table 26. EPM9320 & EPM9320A Dedicated Pin-Outs (Part 1 of 2) Note (1)

Table 26. EPM9320 & EPM9320A Dedicated Pin-Outs (Part 2 of 2) Note (1)

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(1) All pins not listed are user I/O pins. (Evaluating Power for Altera Devices) . (3) EPM9320A devices are not offered in this package. (5) The user I/O pin count includes dedicated input pins and all I/O pins. (1) All pins not listed are user I/O pins. (Evaluating Power for Altera Devices) for more information. (4) The user I/O pin count includes dedicated input pins and all I/O pins. Table 27. EPM9400 Dedicated Pin-Outs Note (1)

(1) All pins not listed are user I/O pins. internally and can be connected to the 5.0-V supply or left unconnected. (3) The user I/O pin count includes dedicated input pins and all I/O pins. Table 28. EPM9480 Dedicated Pin-Outs Note (1)

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Table 29. EPM9560 & EPM9560A Dedicated Pin-Outs (Part 1 of 2) Note (1)

(1) All pins not listed are user I/O pins. (2) EPM9560A devices are not offered in this package. (4) The user I/O pin count includes dedicated input pins and all I/O pins. Table 29. EPM9560 & EPM9560A Dedicated Pin-Outs (Part 2 of 2) Note (1)

Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Alte ra Corporation in the U.S. and other countries. All other product or service names are the property of the ir respective holders. Altera products are protected under numerous U.S. and foreign patents and pendin g applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make chang es to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein ex cept as expressly agreed to in wri tin g by Altera Corpo ration . Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com MAX 9000 Programmable Logic Device Family Data Sheet

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Printed on Recycled Paper. Revision History Information contained in the MAX 9000 Programmable Logic Device Family Data Sheet version 6.5 supersedes information published in previous versions. Version 6.5 Version 6.6 of the MAX 9000 Programmable Logic Device Family Data Sheet contains the following change: ■ Added Tables 7 through 9. ■ Added “Programming Sequence” on page 20 and “Programming Times” on page 20 Version 6.4 Version 6.4 of the MAX 9000 Programmable Logic Device Family Data Sheet contains the following change: Updated text on page 23. Version 6.3 Version 6.3 of the MAX 9000 Programmable Logic Device Family Data Sheet contains the following change: added Note (7) to Table 16.

MAX 9000 Programmable Logic Device Family Data Sheet

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MAX 9000 Programmable Logic Device Family Data Sheet