EPLD

EPLD ALTERA | Alldatasheet

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Features

n Complete device family with logic densities of 300 to 900 usable gates (see Table 1) n Device erasure and reprogramming with non-volatile EPROM configuration elements n Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz n 24 to 68 pins available in dual in-line package (DIP), plastic J-lead chip carrier (PLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages n Programmable security bit for protection of proprietary designs n 100 generically tested to provide 100 programming yield n Programmable registers providing D, T, JK, and SR flipflops with individual clear and clock controls n Software design support featuring the Altera MAX+PLUS II development system on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000 workstations, and third-party development systems n Programming support with Altera’s Master Programming Unit (MPU); programming hardware from Data I/O, BP Microsystems, and other third-party programming vendors n Additional design entry and simulation support provided by EDIF, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Table 1. Classic Device Features

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Classic EPLD Family Data Sheet General

Description

device family offers a solution to high-speed, low- power logic integration. Fabricated on advanced CMOS technology, Classic devices also have a Turbo-only version, which is described in this data sheet. Classic devices support 100 TTL emulation and can easily integrate multiple PAL- and GAL-type devices with densities ranging from 300 to 900 usable gates. The Classic family provides pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz. Classic devices are available in a wide range of packages, including ceramic dual in-line package (CerDIP), plastic dual in-line package (PDIP), plastic J-lead chip carrier (PLCC), ceramic J-lead chip carrier (JLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages. EPROM-based Classic devices can reduce active power consumption without sacrificing performance. This reduced power consumption makes the Classic family well suited for a wide range of low-power applications. Classic devices are 100 generically tested devices in windowed packages and can be erased with ultra-violet (UV) light, allowing design changes to be implemented quickly. Classic devices use sum-of-products logic and a programmable register. The sum-of-products logic provides a programmable- AND /fixed- OR structure that can implement logic with up to eight product terms. The programmable register can be individually programmed for D, T, SR, or JK flipflop operation or can be bypassed for combinatorial operation. In addition, macrocell registers can be individually clocked either by a global clock or by any input or feedback path to the AND array. Altera’s proprietary programmable I/O architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. These features make it possible to implement a variety of logic functions simultaneously. Classic devices are supported by Altera’s MAX+PLUS II development system, a single, integrated package that offers schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry , compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and workstation- based EDA tools. The MAX+PLUS II software runs on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. These devices also contain on-board logic test circuitry to allow verification of function and AC specifications during standard production flow.

Classic EPLD Family Data Sheet f For more information, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet Functional The Classic architecture includes the following elements: n Macrocells n Programmable registers n Output enable/clock select n Feedback select Macrocells Classic macrocells, shown in Figure 1, can be individually configured for both sequential and combinatorial logic operation. Eight product terms form a programmable- AND array that feeds an OR gate for combinatorial logic implementation. An additional product term is used for asynchronous clear control of the internal register; another product term implements either an output enable or a logic-array-generated clock. Inputs to the programmable- AND array come from both the true and complement signals of the dedicated inputs, feedbacks from I/O pins that are configured as inputs, and feedbacks from macrocell outputs. Signals from dedicated inputs are globally routed and can feed the inputs of all device macrocells. The feedback multiplexer controls the routing of feedback signals from macrocells and from I/O pins. For additional information on feedback select configurations, see Figure 3 on page 749. Figure 1. Classic Device Macrocell

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Classic EPLD Family Data Sheet The eight product terms of the programmable- AND array feed the 8-input OR gate, which then feeds one input to an XOR gate. The other input to the XOR gate is connected to a programmable bit that allows the array output to be inverted. Altera’s MAX+PLUS II software uses the XOR gate to implement either active-high or active-low logic, or De Morgan’s inversion to reduce the number of product terms needed to implement a function. Programmable Registers To implement registered functions, each macrocell register can be individually programmed for D, T, JK, or SR operation. If necessary, the register can be bypassed for combinatorial operation. During design compilation, the MAX+PLUS II software selects the most efficient register operation for each registered function to minimize the logic resources needed by the design. Registers have an individual asynchronous clear function that is controlled by a dedicated product term. These registers are cleared automatically during power-up. In addition, macrocell registers can be individually clocked by either a global clock or any input or feedback path to the AND array. Altera’s proprietary programmable I/O architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. These features make it possible to simultaneously implement a variety of logic functions. Output Enable/Clock Select Figure 2 shows the two operating modes (Modes 0 and 1) provided by the output enable/clock ( OE CLK ) select. The OE CLK select, which is controlled by a single programmable bit, can be individually configured for each macrocell. In Mode 0, the tri-state output buffer is controlled by a single product term. If the output enable is high, the output buffer is enabled. If the output enable is low, the output has a high-impedance value. In Mode 0, the macrocell flipflop is clocked by its global clock input signal. In Mode 1, the output enable buffer is always enabled, and the macrocell register can be triggered by an array clock signal generated by a product term. This mode allows registers to be individually clocked by any signal on the AND array. With both true and complement signals in the AND array, the register can be configured to trigger on a rising or falling edge. This product-term-controlled clock configuration also supports gated clock structures.

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level performance evaluation. Figure 4. Classic Timing Model

Classic EPLD Family Data Sheet Timing information can be derived from the timing model and parameters for a particular device. External timing parameters represent pin-to-pin timing delays, and can be calculated from the sum of internal parameters. Figure 5 shows the internal timing relationship for internal and external delay parameters. f For more information on device timing, refer to Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book.

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Figure 5. Classic Switching Waveforms

Classic device that supports the Turbo mode. AC specifications during standard production flow. Figure 6. AC Test Conditions

Notes:

n High-performance, 16-macrocell Classic EPLD – Combinatorial speeds with t PD as fast as 10 ns – Counter frequencies of up to 100 MHz – Pipelined data rates of up to 125 MHz n Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins n EP610 and EP610I devices are pin-, function-, and programming file-compatible n Programmable clock option for independent clocking of all registers n Macrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation n Available in the following packages (see Figure 7): – 24-pin small-outline integrated circuit (plastic SOIC only) – 24-pin ceramic and plastic dual in-line package (CerDIP and PDIP) – 28-pin plastic J-lead chip carrier (PLCC) Figure 7. EP610 Package Pin-Out Diagrams Package outlines not drawn to scale. Windows in ceramic packages only.

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Classic EPLD Family Data Sheet General EP610 devices have 16 macrocells, 4 dedicated input pins, 16 I/O pins, and 2 global clock pins (see Figure 8). Each macrocell can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the I/O input. The CLK1 signal is a dedicated global clock input for the registers in macrocells 9 through 16. The CLK2 signal is a dedicated global clock input for registers in macrocells 1 through 8. Figure 8. EP610 Block Diagram Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages. Figure 9. ICC vs. Frequency of EP610 Devices

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capacitance for EP610 and EP610I devices. Table 2. EP610 & EP610I Device Absolute Maximum Ratings Notes (1), (2) Table 3. EP610 & EP610I Device Recommended Operating Conditions Note (2) Table 4. EP610 & EP610I Device DC Operating Conditions Note (6)

Table 5. EP610 & EP610I Device Capacitance Note (9) Table 6. EP610 Device ICC Supply Current Notes (2), (10) Table 7. EP610I Device ICC Supply Current Note (10)

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Classic EPLD Family Data Sheet Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet in this data book. (2) Numbers in parentheses are for industrial-temperature-range devices. (3) The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V (EP610) or –0.5 V (EP610I) or overshoot to 7.0 V (EP610) or VCC + 0.5 V (EP610I) for input currents less than 100 mA and periods less than 20 ns. (4) For EP610 devices, maximum VCC rise time is 50 ms. For EP610I devices, maximum VCC rise time is unlimited with monotonic rise. (5) For EP610-15 and EP610-20 devices: tR and tF = 40 ns. For EP610-15 and EP610-20 clocks: tR and tF = 20 ns. (6) These values are specified in Table 3 on page 758. (7) The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL output current. (8) This parameter does not apply to EP610I devices. (9) The device capacitance is measured at 25° C and is sample-tested only. (10) Typical values are for TA = 25° C and V CC = 5 V. (11) When the Turbo Bit option is not set (non-Turbo mode), EP610 devices enter standby mode if no logic transitions occur for 100 ns after the last transition. When the Turbo Bit option is not set, EP610I devices enter standby mode if no logic transitions occur for 75 ns after the last transition. (12) Measured with a device programmed as a 16-bit counter.

Table 8. EP610-15 & EP610-20 External Timing Parameters Notes (1), (2) Table 9. EP610-15 & EP610-20 Internal Timing Parameters (Part 1 of 2)

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Table 9. EP610-15 & EP610-20 Internal Timing Parameters (Part 2 of 2) Table 10. EP610-25, EP610-30 & EP610-35 External Timing Parameters Notes (1), (2)

(1) These values are specified in Table 3 on page 758. (3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (5) The fMAX values represent the highest frequency for pipelined data. (6) Measured with a device programmed as a 16-bit counter. applies for both global and array clocking. Table 11. EP610-25, EP610-30 & EP610-35 Internal Timing Parameters

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Tables 12 and 13 show the timing parameters for EP610I devices. Table 12. EP610I External Timing Parameters Notes (1), (2) fMAX Maximum frequency (5) 125.0 100.

(1) These values are specified in Table 3 on page 758. (3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (5) The fMAX values represent the highest frequency for pipelined data. (6) Measured with a device programmed as a 16-bit counter. applies for both global and array clocking. Table 13. EP610 Internal Timing Parameters

Notes:

Figure 11. EP910 Package Pin-Out Diagrams Package outlines are not drawn to scale. Windows in ceramic packages only.

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Classic EPLD Family Data Sheet General Altera EP910 devices can implement up to 450 usable gates of SSI and MSI logic functions. EP910 devices have 24 macrocells, 12 dedicated input pins, 24 I/O pins, and 2 global clock pins (see Figure 12). Each macrocell can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the I/O input. The CLK1 and CLK2 signals are the dedicated clock inputs for the registers in macrocells 13 through 24 and 1 through 12, respectively. Figure 12. EP910 Block Diagram Numbers without parentheses are for DIP packages. Numbers in parentheses are for J-lead packages.

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capacitance for EP910 and EP910I devices. Table 14. EP910 & EP910I Device Absolute Maximum Ratings Notes (1), (2) Table 15. EP910 & EP910I Device Recommended Operating Conditions Note (2) Table 16. EP910 & EP910I Device DC Operating Conditions Notes (6), (7)

(1) See the Operating Requirements for Altera Devices Data Sheet in this data book. (2) Numbers in parentheses are for industrial-temperature-range devices. (5) For all clocks: tR and tF = 100 ns (50 ns for the industrial-temperature-range version). (6) These values are specified in Table 15 on page 770. (7) The device capacitance is measured at 25° C and is sample-tested only. (9) This parameter does not apply to EP910I devices. transitions occur for 75 ns after the last transition. (11) Measured with a device programmed as a 24-bit counter. Table 17. EP910 & EP910I Device Capacitance Note (6) Table 18. EP910 & EP910I Device ICC Supply Current Notes (2), (6), (7)

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Tables 19 and 20 show the timing parameters for EP910 devices. Table 19. EP910 External Timing Parameters Notes (1), (2)

(1) These values are specified in Table 15 on page 770. (3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (5) The fMAX values represent the highest frequency for pipelined data. (6) Measured with a device programmed as a 24-bit counter. Table 20. EP910 Internal Timing Parameters

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Tables 21 and 22 show the timing parameters for EP910I devices. Table 21. EP910I External Timing Parameters Notes (1), (2)

(1) These values are specified in Table 15 on page 770. (3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (5) The fMAX values represent the highest frequency for pipelined data. (6) Measured with the device programmed as a 24-bit counter. Table 22. EP910I Internal Timing Parameters

Notes:

Figure 15. EP1810 Package Pin-Out Diagrams Package outlines not drawn to scale. See Table 32 on page 785 of this data sheet for PGA package pin-out information. Windows in ceramic packages only.

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Classic EPLD Family Data Sheet General Altera EP1810 devices offer LSI density, TTL-equivalent speed, and low- power consumption. EP1810 devices have 48 macrocells, 16 dedicated input pins, and 48 I/O pins (see Figure 16). EP1810 devices are divided into four quadrants, each containing 12 macrocells. Of the 12 macrocells in each quadrant, 8 have quadrant feedback and are “local” macrocells (see “Feedback Select” on page 749 of this data sheet for more information). The remaining 4 macrocells in the quadrant are “global” macrocells. Both local and global macrocells can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of the feedbacks from the global macrocells. EP1810 devices also have four dedicated inputs (one in each quadrant) that can be used as quadrant clock inputs. If the dedicated input is used as a clock pin, the input feeds the clock input of all registers in that particular quadrant.

Figure 16. EP1810 Block Diagram Pin numbers are for J-lead packages. Pin numbers in parentheses are for PGA packages.

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Figure 17. ICC vs. Frequency of EP1810 Devices Figure 18 shows the output drive characteristics of EP1810 devices. Figure 18. Output Drive Characteristics of EP1810 Devices Drive characteristics may exceed shown curves.

capacitance for EP1810 devices. Table 23. EP1810 Device Absolute Maximum Ratings Notes (1), (2) Table 24. EP1810 Device Recommended Operating Conditions Note (2) Table 25. EP1810 Device DC Operating Conditions Notes (6), (7)

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(1) See the Operating Requirements for Altera Devices Data Sheet in this data book. (2) Numbers in parentheses are for industrial-temperature-range devices. input currents less than 100 mA and periods less than 20 ns. (4) Maximum VCC rise time is 50 ms. (5) For EP1810 clocks: tR and tF = 100 ns (50 ns for industrial-temperature-range versions). (6) Typical values are for TA = 25° C and VCC = 5 V. (7) These values are specified in Table 24 on page 781. (9) The device capacitance is measured at 25° C and is sample-tested only. (10) Measured with a device programmed as four 12-bit counters. Table 26. EP1810 Device Capacitance Note (9) Table 27. EP1810 Device ICC Supply Current Notes (2), (6), (7)

Table 28. EP1810-20 & EP1810-25 External Timing Parameters Note (1) Table 29. EP1810-20 and EP1810-25 Internal Timing Parameters

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Table 30. EP1810-35 & EP1810-45 External Timing Parameters Note (1) Table 31. EP1810-35 & EP1810-45 Internal Timing Parameters

(1) These values are specified in Table 24 on page 781. (2) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (3) Measured with a device programmed as four 12-bit counters. applies for both global and array clocking. (5) The fMAX values represent the highest frequency for pipelined data. (6) Sample-tested only for an output change of 500 mV. Table 32. EP1810 PGA Pin-Outs

Notes: