EPL09060 EMC | Alldatasheet
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Datasheet sections
- 10 Absolute Maximum Ratings
- 12 AC Characteristics
- 13 Application Circuit
Datasheet sections
9 COM/ 60 SEG
DOC. VERSION 1.0 ELAN MICROELECTRONICS CORP. December 2005
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2005 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre
68 Mody Road, Tsimshatsui
Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk USA: Elan Information Technology Group (U.S.A) 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8225 Fax: +1 408 366-8220 Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105
8050 Zurich, SWITZERLAND
Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 Shanghai: Elan Microelectronics Shanghai, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 21 5080-3866 Fax: +86 21 5080-4600
9 COM/60 SEG LCD Driver
Product Specification (V1.0) 12.28.2005
- 5
1 General Description
The EPL09060 is a driver and controller LSI for graphic dot-matrix liquid crystal display systems. It can be interfaced to the MPU via serial or 8-bit interface. It contains 9 common and 60 segment driver circuits. A single chip can drive a graphic display system with a maximum of 60 × 9 dots.
2 Features
Direct Correspondence between Display Data RAM and LCD Pixel Display Data RAM : 43 × 102 = 4386 bits
69 LCD Drivers : 60-seg segment drivers, 8-common drivers and 1-icon
Serial Interface (SPI) or 8-Bit Parallel Interface Mode (80-/68-series MPU) On-chip oscillator circuit Programmable Duty Ratio: Duty Ratio Common Segment 1: 8 (+ ICON) 8 (+ ICON) 1:16 (+ICON) 16 (+ICON) Note: ICON = “0” : Pin disable ICON = “1” : Pin enable Selectable LCD driving bias level : Selectable LCD display clock frequency Electronic contrast control function (64 steps) Built-in useful Instruction Set : Display data read/write, Display on/off, Inverse display, Page address set, Common address set, LCD display contrast control, Set Sleep mode, Standby mode, etc. Operating Voltage range : − Supply voltage : 2.2V to 3.4 V − LCD driving voltage : 3.0V to 6 V Package (Ordering information): Part Number Package
Description
Package Information
Note: The EPL09060 series has the following sub-codes, depending on their shapes. H: Bare die (Aluminum pad without bump); GH: Gold bumped die F: COF package; T: TAB (TCP) package Example: EPL09060H Æ EPL09060 Elan; H: Bare die
6 • Product Specification (V1.0) 12.28.2005
3 Applications
Handy Terminals (PDA)
4 Pin Configuration (Package)
Figure 1 Pin Configuration NOTE With the Elan logo at the right bottom corner (as shown in the figure) and DDRAM (black color) at the right side, Pin 1 is at the upper left corner. Pad Configuration Size Item Pad No. X Y Unit Chip size 4040 2070 Pad size (Type A) Pad size (Type B) 2, 14~15, 22~29 Pad size (Type C) 4~13, 16, 53~68 Type A 105 Pad pitch Type B 110 µm
Product Specification (V1.0) 12.28.2005 Pad Coordinates Table Pad No. Symbol X Y Pad No. Symbol X Y COMI1 -3852.5 -75.3 SEG51 -75.1 -1774.2 VDD -3860.0 -229.15 SEG50 -75.1 -1669.2 VDD -3860.0 -353.9 SEG49 -75.1 -1564.2 C1+ -3868.1 -473.1 SEG48 -75.1 -1459.2 C1- -3868.1 -578.1 SEG47 -75.1 -1354.2 C2+ -3868.1 -683.1 SEG46 -75.1 -1249.2 VOUT -3868.1 -788.1 SEG45 -75.1 -1144.2 -3868.1 -893.1 SEG44 -75.1 -1039.2 -3868.1 -998.1 SEG43 -75.1 -934.2 -3868.1 -1103.1 SEG42 -75.1 -829.2 -3868.1 -1208.1 SEG41 -75.1 -724.2 -3868.1 -1313.1 SEG40 -75.1 -619.2 VR -3868.1 -1418.1 SEG39 -75.1 -514.2 GND -3860.0 -1541.3 SEG38 -75.1 -409.2 GND -3860.0 -1651.3 SEG37 -75.1 -304.2 PS -3868.1 -1774.2 SEG36 -75.1 -199.2 C86 -3870.7 -1898.1 SEG35 -72.5 -75.3 CLS -3765.7 -1898.1 SEG34 -177.5 -75.3 OSC -3660.7 -1898.1 SEG33 -282.5 -75.3 IRS -3555.7 -1898.1 SEG32 -387.5 -75.3 /RES -3450.7 -1898.1 SEG31 -492.5 -75.3 -3318.2 -1890.0 SEG30 -597.5 -75.3 -3208.2 -1890.0 SEG29 -702.5 -75.3 -3098.2 -1890.0 SEG28 -807.5 -75.3 -2988.2 -1890.0 SEG27 -912.5 -75.3 -2878.2 -1890.0 SEG26 -1017.5 -75.3 -2768.2 -1890.0 SEG25 -1122.5 -75.3 -2658.2 -1890.0 SEG24 -1227.5 -75.3 -2548.2 -1890.0 SEG23 -1332.5 -75.3 CS2 -2403.5 -1898.1 SEG22 -1437.5 -75.3 /CS1 -2298.5 -1898.1 SEG21 -1542.5 -75.3 -2193.5 -1898.1 SEG20 -1647.5 -75.3 /WR -2088.5 -1898.1 SEG19 -1752.5 -75.3 /RD -1983.5 -1898.1 SEG18 -1857.5 -75.3 TEST -1878.5 -1898.1 SEG17 -1962.5 -75.3 COM7 -1752.5 -1898.1 SEG16 -2067.5 -75.3 COM6 -1647.5 -1898.1 SEG15 -2172.5 -75.3 COM5 -1542.5 -1898.1 SEG14 -2277.5 -75.3 COM4 -1437.5 -1898.1 SEG13 -2382.5 -75.3 COM3 -1332.5 -1898.1 SEG12 -2487.5 -75.3 COM2 -1227.5 -1898.1 SEG11 -2592.5 -75.3 COM1 -1122.5 -1898.1 SEG10 -2697.5 -75.3 COM0 -1017.5 -1898.1 SEG9 -2802.5 -75.3 COMI2 -912.5 -1898.1 SEG8 -2907.5 -75.3 SEG59 -807.5 -1898.1 SEG7 -3012.5 -75.3 SEG58 -702.5 -1898.1 SEG6 -3117.5 -75.3 SEG57 -597.5 -1898.1 SEG5 -3222.5 -75.3 SEG56 -492.5 -1898.1 100 SEG4 -3327.5 -75.3 SEG55 -387.5 -1898.1 101 SEG3 -3432.5 -75.3 SEG54 -282.5 -1898.1 102 SEG2 -3537.5 -75.3 SEG53 -177.5 -1898.1 103 SEG1 -3642.5 -75.3 SEG52 -72.5 -1898.1 104 SEG0 -3747.5 -75.3 Note: For PCB layout, the IC substrate must be connected to VSS or floating.
8 • Product Specification (V1.0) 12.28.2005
5 Functional Block Diagram
Figure 2 System Block Diagram DISPLAY DATA RAM LINE ADDRESS DECODE LINE COUNTER INITIAL DISPLAY LINE REGISTER LOW ADDRESS DECODER COLUMN ADDRESS DECODER COLUMN ADDRESS COUNTER COLUMN ADDRESS REGISTER PAGE ADDRESS REGISTER Oscillator Display Timing Generator Circuit CLS SEGMENT DRIVER CIRCUITS VSS COMI SEG0 SEG59 LATCH CIRCUIT I/O Buffer ( Serial / Parallel ) MPU Interface Bus holder INSTRUCTION REGISTER STATUS REGISTER INSTRUCTION DECODER D7 D6 D5 D4 D3 D2 D1 D0 /CS1CS2A0 /RD/WRC86 P/S /RES (E) (R/W) (SDI)(SCK) Voltage Followers Voltage Regulator Voltage Converter Connect the capacitor VOUT VR COMMON DRIVER CIRCUITS COM0 COM7 SHIFT REGISTER (SDO) IRS OSC
Product Specification (V1.0) 12.28.2005
6 Pin Description
0V (GND) LCD driver supply voltages. The voltage applied is determined by the LCD pixel and is changed through changing the impedance using an operational amplifier (OPA) for various applications. Voltage levels are determined based on V0, and must maintain the relative magnitudes shown below: When the internal power circuit is active, these voltages are generated according to the state of LCD bias, The selection of voltages is determined by the “LCD bias select” instruction, as shown in the table below. LCD Bias 1/8 Bias 7/8 × V0 6/8 × V0 2/8 × V0 1/8 × V0 1/7.5 Bias 6.5/7.5 × V0 5.5/7.5 × V0 2/7.5 × V0 1/7.5 × V0 1/7 Bias 6/7 × V0 5/7 × V0 2/7 × V0 1/7 × V0 1/6.5 Bias 5.5/6.5 × V0 4.5/6.5 × V0 2/6.5 × V0 1/6.5 × V0 1/6 Bias 5/6 × V0 4/6 × V0 2/6 × V0 1/6 × V0 1/5.5 Bias 4.5/5.5 × V0 3.5/5.5 × V0 2/5.5 × V0 1/5.5 × V0 1/5 Bias 4/5 × V0 3/5 × V0 2/5 × V0 1/5 × V0 1/4.5 Bias 3.5/4.5 × V0 2.5/4.5 × V0 2/4.5 × V0 1/4.5 × V0 1/4 Bias 3/4 × V0 2/4 × V0 2/4 × V0 1/4 × V0 1/3.5 Bias 2.5/3.5 × V0 1.5/3.5 × V0 2/3.5 × V0 1/3.5 × V0 1/3 Bias 2/3 × V0 1/3 × V0 2/3 × V0 1/3 × V0 Power LCD Driver Supply Name I/O O Boosted capacitor connecting terminals used for voltage booster. C2+ O Boosted capacitor connecting terminals used for voltage booster. VOUT I/O Voltage converter output VR I V0 voltage adjustment pin
10 • Product Specification (V1.0) 12.28.2005 System Control Name I/O I Select theInterface mode with the MPU. When PS = "High": Parallel interface mode When PS = "Low": Serial interface mode C86 I Select the kinds of the MPU to interface. When C86 = "High": 68-series MPU interface mode When C86 = "Low": 80-series MPU interface CLS I Internal oscillator circuit enable / disable select pin. CLS = “H”: Enable the Internal oscillator circuit CLS = “L”: Disable the Internal oscillator circuit (External display clock input to the OSC pin) OSC I When using an external oscillator, input the clock to the OSC pin. When using an internal oscillator, leave this pin open. IRS I Internal resistor select pin. This pin selects the resistors for adjusting the V0 voltage level and is available only in master mode. - IRS = "H": Internal resistors are used. - IRS = "L": External resistors are used. V0 voltage is controlled using the external divider resistor connecting the VR pin. TEST I Test pin. Must be fixed at VSS. MPU Interface Name I/O /RES I Hardware reset input The LSI is reset when this signal is pulled low (Active low) Chip select signals. The Chip Select of the LSI becomes active when CS1 is "L" and CS2 is "H", which allows input/output of data or commands. /CS1 CS2 Status “L” “L” The device is not active (D7~D0 is Hi-Z) “L” “H” Data and instruction are available. “H” “L” The device is not active (D7~D0 is Hi-Z) “H” “H” The device is not active (D7~D0 is Hi-Z) /CS1, CS2 I I Used as register selection input When A0 = "High", Data register When A0 = "Low", Instruction register /WR (R/W) I When C86 = "High"(68-series MPU interface), used as read (/WR = "High"), write (/WR = "Low") When C86 = "Low " (80-series MPU interface), used as write enable input (/WR) /RD (E) I When C86 = "High"(68-series MPU interface), used as read/write enable input (E). When C86 = "Low "(80-series MPU interface), used as read enable input (/RD) D0 to D7 I/O When in serial mode, D6 (SCK) is used as serial clock input pin, D7 (SDI) is used as serial data input pin, D5 (SDO) is used as serial data output pin and the others are not used. When in parallel mode, D0 to D7 are used as bidirectional data bus pin.
Product Specification (V1.0) 12.28.2005 LCD Driver Output Name I/O H Vss H L H L L Power Save Mode Vss COM0 to COM7 O COMI O There are two icon display pins. Both pins output the same signal. Leave these pins open when they are not used. LCD segment output pins SEGs Output Voltage Display Data FR Normal Display Reverse Display H H L Vss H L L Vss Power Save Mode Vss SEG0 to SEG59 O
12 • Product Specification (V1.0) 12.28.2005
7 Functional Description
7.1 MPU Interface
7.1.1 Chip Select
The EPL09060 has two chip select pins /CS1 and CS2. When /CS1="L" and CS2=”H”, MPU interface is available. When the chip select pin is inactive (other /CS1 and CS2 condition), D7 to D0 are high impedance (invalid) and input of A0, /RD, or /WR inputs are not effective. If serial interface is selected, the shift register and the counter are both reset. However, reset is always operated in any conditions of /CS1 and CS2. P/S C86 WR /RD D0~D4 Serial Mode (L) SPI interface ( − ) R/W SDO SCK SDI 80-series (L) /WR /RD D0~D7 Parallel Mode (H) 68-series (H) R/W E D0~D7 Note: “ * ” Don’t care (“High”, “Low” or “Open”) “−” Indicates that it is fixed to either “High” (VDD) or “Low” (VSS) I/O Buffer ( Serial/Parallel ) MPU Interface Bus Holder Instruction Register Status Register Instruction Decoder D6 D5 D4 D3 D2 /CS1 CS2 A0 /RD /WR C86 P/S /RES (E) (R/W) (SDI)(SCK)(SDO) BUSY
Product Specification (V1.0) 12.28.2005
7.1.2 Selecting the Interface Type
The EPL09060 can be operated with serial interface (SPI) and parallel interface (80- series or 68-series) as selected by P/S pin. Serial Interface (SPI) When serial mode (PS = "L"), D6 (SCK) is used as serial clock input pin, D7 (SDI) is used as serial data input pin, D5 (SDO) is used as serial data output pin. When the LSI is active (/CS1=”L”, CS2=”H”), serial data input (D7), serial clock input (D6) inputs and serial data output (D5) are enabled. The 8-bit shift register and 3-bit counter are reset to the initial condition when the chip is not selected. The data input/output from SDI/SDO terminal is MSB first as in the order of D7, D6…D0, and is latched at the rising edge of the serial clock SCK. Serial input data is display data when A0="H" and instruction when A0="L". The A0 input is read in and identified at the rising edge of the (8 x n) serial clock pulse. Since the clock signal (D6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. Figure 4 Serial Interface Signal Chart /WR (R/W) D7 (SDI) D5 (SDO) Instruction Write Status Read Invalid Status Read Display Data Write Status Read Invalid Display Data Read SDI (D7) SDO (D5) SCK (D6) /CS1 CS2
14 • Product Specification (V1.0) 12.28.2005 Parallel Interface (8-bit Length) Parallel mode (8-bit length): When parallel input is selected (PS = ”H”), D0~D7 can be connected directly to the 80-series or 68-series MPU by setting the C86 pin to high or low. Figure 5 Write and Read Timing Diagrams Common 80-Series 68-Series /RD /WR R/W H L H H Display data read H H L L Display data write L L H H Register status read L H L L Writes to Instruction register
7.2 Data Transfer
The EPL09060 uses a bus holder and an internal data bus for data transfer with the MPU. When writing data from the MPU to the DDRAM, data is automatically transferred from the bus holder to the DDRAM. When reading data from the DDRAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from the bus holder for the next data read cycle. D7~D0 /WR /RD D7~D0 N Dummy D(N) D(N+1) D(N+3) D(N+2) N D(N) D(N+1) D(N+2) D(N+3) D(N+4) /RD /WR Write Timing Diagram Read Timing Diagram
Product Specification (V1.0) 12.28.2005
7.2.1 Display Data RAM (DDRAM)
Figure 6 Display Data RAM Diagram The display data RAM (DDRAM) stores pixel data for the LCD. It is a 43-row × 102- column addressable array. It is possible to access any required bit by specifying the page address and the column address. The 43 rows are divided into five pages of eight lines, one page with two lines (D0, D1) and the seventh page with a single line (D0 only). Each bit in the Display Data RAM corresponds to each pixel of the LCD panel. Each bit in the Display Data RAM corresponds to each pixel of the LCD panel and controls the display by applying the following bit data. When in Normal Display : On="1" , Off="0" When in Inverse Display : On="0" , Off="1" (Refer to “Inverse Display On/Off” instruction for more details.) Figure 7 Display Data RAM, Normal and Inverse Liquid Crystal Display Diagrams D is p la y D a ta R A M Line Address Decoder Line Counter Initial Display Line Register Low Address Decoder C o lu m n A d d re s s D e c o d e r C o lu m n A d d re s s C o u n te r C o lu m n A d d re s s R e g is te r Page Address Register Display Data RAM Normal Display Inverse Display
16 • Product Specification (V1.0) 12.28.2005
7.2.2 Programmable Duty Ratio
The duty ratio is selected by using the “Set Duty Ratio” instruction. The common output circuits are shown in the following figure. They are separated into three shift registers and controlled by the "duty ratio register". Figure 8 Common Output Circuits Common Output Pins COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COMI Duty SHL Line Address COMI COMI F E D C B A Relationship between Duty Ratio and Common Output It should be noted that when using 1/16 duty (SHL=0), the MCU writes data to the LCD DRAM (Page 0: line addresses 0~7; Page 1: line addresses 8~15) and it will correspond to common output pins (Page 0: COM0~7; Page 1: COM34~41). But the EPL09060 have real output common pins COM0~7 and COMI, the others are invalid. Initial Display Line Register The initial display line register assigns a DDRAM line address which corresponds to COM0 by using the “Initial display line set” instruction. It is used not only for normal display but also for vertical display scrolling and page switching without changing the contents of the DDRAM. However, the 9th address for the icon display cannot be assigned for the initial display line address. Line Counter The line counter provides a DDRAM line address. It initializes its contents at the switching of frame reversal signal (FR (internal)), and also counts-up in synchronization with the common timing signal. 8-bit Shift Register 1-bit Shift Register Common Driver (8) Common Driver (1) Duty Ratio Register COM0 COM7 COMI
Product Specification (V1.0) 12.28.2005 Column Address Counter The column address counter is an 8-bit preset counter which provides a DDRAM column address, and is independent of page address register. It will increment (+1) the column address whenever “display data read” or “display data write” instructions are issued. However, the incrementing of column address is stopped at column address 65H. The count-lock will be released by the “column address set” instruction again. The counter can inverts the correspondence between the column address and segment driver direction by means of “ADC select” instruction. Page Address Register The page address register provides a DDRAM page address. The Page Address 6 is used for icon display, and only D0 is valid.
7.3 LCD Driver Circuits
Figure 9 LCD Driver Circuits This driver circuit is configured by 8-common drivers, 60-segment drivers and 1-icon- common driver. This LCD panel driver voltage depends on the combination of display data and FR (internal) signal.
7.3.1 Display Data Latch Circuit
The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. “Display on/off”, “Inverse display on/off” and “Entire display on/off” instructions control only the contents of this latch circuit, they cannot change the contents of the DDRAM. Common Driver Circuits Segment Driver Circuits VSS COM0 COMI COM7 SEG0 SEG59 Shift Register Latch Circuit Display Timing Generator Circuit From the Display Data RAM
18 • Product Specification (V1.0) 12.28.2005
7.3.2 Shift Register Circuit
The circuit contains a 42-bit shift register to shift the turn-on data required for the LCD drive common signals and 1-bit shift register used for icon. The clock of this shift register is generated by display clock CL (internal). Examples of 1/17 duty (ICON enable) driving waveform Figure 10 1/17 Duty Driving Waveform CO M 7 C O M I FR (internal) CO M 0 CO M 1 CL (internal) 1/17 Duty
Product Specification (V1.0) 12.28.2005 Examples of 1/16 duty (ICON disable) driving waveform Figure 11 1/17 Duty Driving Waveform CO M 7 FR (internal) CO M 0 CO M 1 CL (internal) 1/16 Duty
20 • Product Specification (V1.0) 12.28.2005 VSS Shift Data FR (internal) COM0~7,COMI VCON VCOFF VSS Display Data FR (internal) SEG0~59 VSON VSOFF
7.3.3 Common Driver Circuit
The Common driver circuit consists of nine drive circuits. One of the four LCD driving level is selected by the combination of FR (internal) and the data from the sift register. Figure 12 Common Driver Circuit
7.3.4 Segment Driver Circuit
The Segment driver circuit consists of 60 driver circuits. One the four LCD driving level is selected by the combination of FR (internal) and the display data transferred from the latch circuit. Figure 13 Common Driver Circuit Scan Data FR COMs Output Voltage H VSS H L H L L Power save mode VSS SEGs Output Voltage Display Data FR Normal Display Inverse Display H H L VSS H L L VSS Power save mode VSS
Product Specification (V1.0) 12.28.2005
7.3.5 LCD Driving Waveform
The following illustration is an example of how the common and segment drivers are attached to an LCD panel. Figure 14 LCD Driver Circuits CL (internal) FR (internal) COM0 COM1 SEG0 VSS VSS VSS SEG0-COM0 -V0 COM0 COM1 SEG0
22 • Product Specification (V1.0) 12.28.2005
7.4 Internal Power Circuits
Figure 15 Internal Power Circuits The internal power supply circuits can generate the voltage levels necessary to drive the liquid crystal driver circuits, with low power consumption and the least components. They comprise of voltage converter (V/C) circuits, voltage regulator (V/R) circuits, and voltage follower (V/F) circuits. User Setup Power Control (VC VR VF) V/C Circuits V/R Circuits V/F Circuits VOUT V1 ~ V4 Only the internal power supply circuits are used 1 1 1 On On On Open Open Open Only the voltage Regulator circuits and voltage follower circuits are used 0 1 1 Off On On External Input Open Open Only the voltage follower circuits are used 0 0 1 Off Off On Open External Input Open Only the external power supply circuits are used 0 0 0 Off Off Off Open External Input External Input Voltage Followers Voltage Regulator Voltage Converter Connect the capacitor VOUT VR LCD Driving Voltage Supply IRS
Product Specification (V1.0) 12.28.2005
7.4.1 Voltage Converter Circuits
These circuits boost up the electric potential between VDD and VSS to 2 times toward the positive side and the boosted voltage is outputted from VOUT pin. The boosting magnitude of the internal booster circuit is selected by means of the capacitor connection (Refer to Figure 16 below). The internal oscillator is required to be operating when using this converter, since the divided signal provided from the oscillator is used for the internal timing of this circuit. Figure 16 Capacitor Connections
7.4.2 Voltage Regulator Circuits
The voltage regulator determines the LCD driving voltage V0, by adjusting resistors Ra and Rb, within the range of |V0| < |VOUT|. Since VOUT is the operating voltage of the operational-amplifier circuits, it is necessary to be applied either internally or externally. For Equation 1, V0 is determined by Ra, Rb and VEV. Ra and Rb are connected internally or externally through the IRS pin. VEV which is the electronic volume voltage, is determined by Equation 2, where the parameter α is the value selected by the instruction "Set Contrast Control Mode," within the range 0 to 63. VREF, a constant voltage source is 2 V at TA=25°C. C1+ C1- C2+ VOUT Boost Capacitors = 1uF~4.7uF
24 • Product Specification (V1.0) 12.28.2005 Figure 17 Resistor Connections VEV Ra Rb V VREF VEV 252 α ……….Equation 2 Register Value (R2, R1, R0) 1 + (Rb/Ra) (0, 0, 0) 3.5 Refer to “Regulator Resistor Select” instruction for details. Refer to “Set Contrast Control Mode” instruction for details. Using Internal Resistors, Ra and Rb (IRS = "H") When the IRS pin is “H”, resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V0 and VR. V0 is determined by using the two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Rb Ra VR VSS VOUT VEV (Constant reference voltage + electronic volume)
Product Specification (V1.0) 12.28.2005 Using External Resistors, Ra and Rb ( IRS = "L") When IRS pin is “L”, it is necessary to connect the external regulator resistor Ra between VR and VSS, and Rb between V0 and VR. For a particular liquid, the optimum VLCD can be calculated for a given multiplex rate. For a 1/9 duty ratio, the optimum operating voltage of the liquid can be calculated as: th th LCD V V V 464 where Vth is the threshold voltage of the liquid crystal material used.
7.4.3 Voltage Follower Circuits
Figure 18 OTP Voltage Follower The VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3, V4), and those output impedance are converted by the voltage follower (OPA) to increase the drive capability. Total 6 levels LCD reference voltage (V0, V1, V2, V3, V4, VSS) is generated by the voltage follower circuits. LCD Bias 0.875×V0 0.750×V0 0.250×V0 0.125×V0 1/7.5 0.865×V0 0.735×V0 0.265×V0 0.135×V0 0.855×V0 0.715×V0 0.285×V0 0.145×V0 1/6.5 0.845×V0 0.690×V0 0.310×V0 0.155×V0 0.835×V0 0.665×V0 0.335×V0 0.165×V0 1/5.5 0.820×V0 0.635×V0 0.365×V0 0.180×V0 0.800×V0 0.600×V0 0.400×V0 0.200×V0 Bypass Capacitor = 0.47uF~1uF Switching Network 0.890xV0 0.880xV0 0.110xV0 0.120xV0 From the Voltage Regulator Total Req = 4M
26 • Product Specification (V1.0) 12.28.2005 LCD Bias 1/4.5 0.780×V0 0.555×V0 0.445×V0 0.220×V0 0.750×V0 0.500×V0 0.500×V0 0.250×V0 1/3.5 0.715×V0 0.430×V0 0.570×V0 0.285×V0 0.665×V0 0.335×V0 0.665×V0 0.335×V0 Different duty radio requires different bias level. For optimum bias level, BL can be calculated using the following equation: ratio Duty BL Changing the bias system from the optimum will have an effect on the contrast and viewing angle. The LCD Bias affects the display quality. But to reduce the current consumption, an unsuitable bias may be selected. Hence, the LCD Bias could be selected by “Select LCD bias” instruction.
7.4.4 Oscillator
The on-chip RC type oscillator provides the display clock and voltage converter timing clock. It has low power consumption and its frequency is nearly independent of VDD. When “CLS”=”H”, the oscillator circuit is enabled. When CLS=”L”, the oscillator is stopped, and the oscillator clock has to be input to the OSC pin. Figure 19 RC Oscillator
7.4.5 Oscillator Frequency
The EPL09060 contains an RC oscillator. The frame frequency (fFM) is derived from the RC circuit’s oscillation frequency (fOSC) by giving it an appropriate value. The relationship between the oscillation frequency (fOSC), display clock frequency (fCL) and the frame frequency (fFM) is shown below. The fOSC could be selected from an internal or external oscillator via the CLS pin, fCL could be selected via “Set display clock CL frequency” instruction, and frame frequency could be calculated using the following equation. fCL = (Duty ratio) × (Frame frequency) RC Oscillator OSC CLS To the Internal Circuit Sleep Mode
Product Specification (V1.0) 12.28.2005 7.5 Reset Circuit When the /RES input comes to the “L” level, this LSI returns to its default state. The default settings are as follows: Display OFF Normal display ADC select: Normal (ADC select instruction D0 = “L”) SHL select: Normal (SHL select instruction D3 = “L”) Power Control Register: (D2, D1, D0) = (0, 0, 0) Serial interface internal register data clear Duty ratio = 1/43, (D3~D0) = (1, 1, 0, 1) CL frequency Register (D4, D3, D2, D1, D0) = (0, 0, 0, 0, 1, 1) LCD power supply bias level = (1/8), (D3~D0) = (1, 0, 1, 0) Entire display OFF (Entire display instruction D0 = “L”) Power saving clear Modify-Read OFF Display initial line set to first line : 0 Column address set to Address : 0 Page address set to Page : 0 V0 voltage regulator internal resistor ratio set mode clear: (R2, R1, R0) = (0, 0, 0) Contrast control set mode clear Contrast control register : (D5, D4, D3, D2, D1,D0) = (1, 0, 0, 0, 0, 0) NOTE After issuing the command “reset”, the registers “Duty ratio” and “bias” must be set with a suitable value.
28 • Product Specification (V1.0) 12.28.2005
8 Control Register
- ICO N D2 D1 D0 Select the duty ratio Set CL frequency Mode Set CL frequency Mode CL frequency Register * D4 D3 D2 D1 D0 Set CL frequency Register Set LCD Bias select Mode Set LCD Bias select Mode LCD Bias select Register D2 D1 D0 Select the LCD Bias Display On/Off
1 Don
When DON=0: display off When DON=1: display on Initial Display Line D2 D1 D0 Specify DDRAM line for COM0 Set Contrast Control Mode Set Contrast Control Mode Set Contrast Control Register D5 D4 D3 D2 D1 D0 Set Contrast Control Register Set Page Address Page Address Set page address Set Column Address MSB Higher order Column Add DDRAM column address of Higher 4-bits Set Column Address LSB Lower order Column Add DDRAM column address of lower 4-bits ADC Select
0 ADC
When ADC=0: normal direction (SEG0 ÆSEG59) When ADC=1: reverse direction (SEG59ÆSEG0) Inverse Display ON/OFF
1 REV
Select normal/inverse display 0 : Normal display 1 : Inverse display on Entire Display ON/OFF
0 EON
Select normal/entire display ON When EON=0: normal display. When EON=1: entire display ON Set Modify-read Set modify-read mode Reset Modify-read Release modify-read mode Reset Initialize the internal functions SHL Select SHL Select COM output direction When SHL=0: normal direction (COM0 -> COM7) When SHL=1: reverse direction (COM7 -> COM0) Power Control VC VR VF Control power circuit operation Regulator Resistor Select Select internal resistance ratio ofthe regulator resistor Power Save Compound instruction of display OFF and entire display ON Note: * : Don’t care
Product Specification (V1.0) 12.28.2005 Read Display Data The 8-bit data from the display data RAM specified by the column address and page address can be read by this instruction. As the column address is automatically incremented by 1 after each instruction execution, the microprocessor can continuously read data from the addressed page. /RD /WR Read Data Write Display Data The 8-bit display data from the microprocessor can be written to the RAM location specified by the column address and page address. After writing the display data, the column address is automatically incremented so that the microprocessor can continuously write data to the addressed page. /RD /WR Write Data Read Status This instruction reads out the internal status regarding “ADC select”, “Display On/Off” and “Reset”. /RD /WR ADC On/Off RESET Flag It shows the correspondence between the column address and segment drivers. ADC = 0 : Normal direction (SEG0 → SEG59) ADC = 1 : Reverse direction (SEG59 → SEG0) On/Off This bit indicates the ON/OFF state of the display. 0 : Display ON 1 : Display OFF RESET Indicates that the initialization is in progress, by the RESETB signal. RESET = 0 : Normal display operation state RESET = 1 : Internal reset operation state with reset command. Set Duty Ratio (Two-Byte instruction) The first instruction sets the duty ratio mode, the second one updates the contents of the duty ratio register. After the second instruction, the set duty mode is released. The LSI cannot accept any instructions except the “Set duty ratio register” during the set duty ratio mode. Set Duty Ratio Mode (First Instruction) /RD /WR
30 • Product Specification (V1.0) 12.28.2005 Set Duty Ratio Register (Second Instruction) /RD /WR Duty Ratio ICON 8 (+ICON) 16 (+ICON) 24 (+ICON) 32 (+ICON) 36 (+ICON) 42 (+ICON) Note: “*” means “Don’t care” ICON: “0” Disable COMI (icon display) pin “1” Enable COMI (icon display) pin Set Display Clock CL Frequency (Two-Byte Instruction) The display clock CL affects the current consumption and the frame frequency affects the flicker, so fine adjustment is required for the display clock CL (internal) and the frame frequency. Set CL Frequency Select Mode (First Instruction) /RD /WR Set CL Frequency Select Register (Second Instruction) /RD /WR CL Frquency fOSC fOSC / 2 fOSC / 3 fOSC / 4 fOSC / 5 fOSC / 6 fOSC / 7 fOSC / 8 fOSC / 9 fOSC / 10 fOSC / 11 fOSC / 12 fOSC / 13 fOSC / 14 fOSC / 15 fOSC / 16 fOSC / 32 Note: “*” means “Don’t care” Select LCD Bias (Two-Byte Instruction) This instruction selects the LCD bias ratio of the voltage required for driving the LCD. Set LCD Bias Select Mode (First Instruction) /RD /WR
Product Specification (V1.0) 12.28.2005 Set LCD Bias select Register (Second instruction) /RD /WR LCD Bias 1/3.5 1/4.5 1/5.5 1/6.5 1/7.5 Note: “*” means “Don’t care” Display ON/OFF This instruction is used to control the turning on or off of the LCD panel, regardless of the contents of the DDRAM. /RD /WR Display On or Off 0 :Off 1 :On Initial Display Line This instruction sets the line address of the display RAM to determine the initial display line. The initial display line corresponds to COM0. The display area read from the display data RAM corresponds to the number of the lines set by the Duty select command. /RD /WR Line Address for COM0 Electronic Contrast Control Set (Two-Byte instruction) The first instruction sets the contrast control mode, the second one updates the contents of the contrast control register. After the second instruction, the contrast control mode is released. The LSI cannot accept any instructions except for the “Set Contrast Control Register” during the Contrast Control Mode. Set Contrast Control Mode (First instruction) /RD /WR
32 • Product Specification (V1.0) 12.28.2005 Set Contrast Control Register (Second instruction) /RD /WR D0 Electronic Volume Value (α)
0 Minimum
This instruction sets the page address of the display data RAM from the microprocessor into the page address register. It is possible to access any required bit in the display data RAM by specifying the page address and the column address. Along with the column address, the page address defines the address of the display RAM used to write or read the display data. Changing the page address does not affect the display status. Page 6 is assigned for the icon display. Only D0 is valid. /RD /WR Page Address Set Column Address This instruction sets the column address of the display data RAM from the microprocessor into the column address register. When accessing the display data RAM from the MPU, the column address is incremented. The incrementing of the column address is stopped at address 65H. /RD /WR Column Address Setting Upper 4-bit Lower 4-bit Column Address
Product Specification (V1.0) 12.28.2005 ADC Select This instruction selects the segment driver direction. Normal or reverse can be selected in the correlation between the display data RAM column address and the segment output terminal. /RD /WR Segment Driver Direction Normal Reverse D0 = 0 Normal Column addresses 00H to 3BH corresponds to segment outputs 0 to 59. D0 = 1 Reverse Column addresses 2AH to 65H corresponds to segment outputs 59 to 0. Inverse Display ON/OFF This instruction is used to invert the display status on the LCD panel without rewriting the contents of the display data RAM. /RD /WR Display Status Normal Inverse D0 = 0 Normal Display data “1” makes the LCD on. D0 = 1 Inverse Display data “0” makes the LCD on. Entire Display ON/OFF This instruction forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM will be retained. This instruction has priority over the Reverse Display On/Off instruction. /RD /WR Entire display on/off Normal Entire display on Set Modify-Read This instruction stops the automatic increment of the column address by the Read Display Data instruction, but the column address is still incremented by the Write Display Data instruction. This instruction can reduce the load of the MPU, during the display, the data in a specific DDRAM area is repeatedly changed for cursor blinking or others. This mode is canceled by the Reset Modify-read instruction. /RD /WR
34 • Product Specification (V1.0) 12.28.2005 Reset Modify-Read This instruction cancels the Modify-read mode. The column address of the display data RAM returns to the address before the Read Modify Write is executed. /RD /WR Reset This instruction resets the initial display line, column address, page address, and the common output status is reset to their initial status, but does not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is initialized by the /RES pin. /RD /WR Reset status by “Reset” instruction: Read modify write off Initial display line address : (00)H Column address : (00)H Page address : (0) page SHL select : Normal mode (D3=0) Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Sets contrast control set mode off and contrast control register : (20)H SHL Select COM output scanning direction is selected by this instruction which determines the LCD driver output status. /RD /WR Common Driver Direction Normal Reverse Note: “*” means “Don’t care” D3 =0 Normal Normal direction (COM0 → COM 7) → (1/16duty ratio, Page 0) D3 =1 Reverse Reverse direction (COM7 → COM 0) → (1/16duty ratio, Page 1)
Product Specification (V1.0) 12.28.2005 Power Control Selects one of eight power circuit functions by using the 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. /RD /WR VC VR VF VC: Voltage converter VR: Voltage regulator VF: Voltage follower 0: Off 1: ON Regulator Resistor Select Selects the resistance ratio of the internal resistor used in the internal voltage regulator. See the voltage regulator section in power supply circuit for more details. /RD /WR [Rb/Ra] Ratio 3.5 Power Save (Compound Instruction) The current consumption can be greatly reduced by entering the power save status and inputting the “Entire Display ON” instruction while the display is in OFF mode. According to the status in static indicator mode, power save is entered through one of two modes (sleep and standby mode). Power Save mode is released by the “Display ON” & “Entire Display OFF” instructions. Static indicator OFF Static indicator ON Pow er saver (com pound com m and) [ Display OFF ] [ Entire Display ON ] Standby m ode Sleep m ode Pow er Save OFF ( Com pound Instruction ) [ Entire Display OFF ] [ Display ON ] [ Static Indicator ON ] Pow er Save OFF ( Com pound Instruction ) [ Entire Display OFF ] [ Display ON ] Standby mode cancel Sleep m ode cancel Static Indicator ON Reset instruction
36 • Product Specification (V1.0) 12.28.2005 Sleep Mode This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the current consumption is reduced to a value near the static current. The internal modes during sleep mode are as follows: The oscillator circuit and the LCD power supply circuit are stopped. All liquid crystal drive circuits are stopped, as well as the segment and common driver output VSS level. When a “static indicator on” instruction is issued in the sleep mode, the LSI goes into the standby mode. Standby Mode All operations of the dynamic LCD display section are stopped, only the static display circuits for the indicators operate and hence the current consumption will be the minimum necessary for static drive. The internal conditions in the standby state are as follows: The power supply circuit for LCD drive is stopped. The oscillator circuit will still be operating. The LCD drive circuits for dynamic display are stopped and the segment and common driver outputs will be at the VSS level. The static display section will still be operating. When a reset instruction is issued in the standby mode, the LSI goes into a sleep mode.
Product Specification (V1.0) 12.28.2005
9 Application Information
9.1 Instruction Procedure Examples
9.1.1 Initial Setup
(From power application to display ON using internal power supply circuits) V D D - V S S P o w e r O N P o w e r S t a b iliz a t io n I n p u t R e s e t S ig n a l W a it f o r m o r e t h a n 2 0 m s I n it ia l s e t t in g s s t a t e ( d e f a u lt ) U s e r s e t t in g s v ia in s t r u c t io n in p u t ( 1 ) D U T Y s e le c t L C D b i a s s e le c t C L f r e q u e n c y s e le c t A D C s e le c t S H L s e le c t U s e r s e t t i n g s v ia c o m m a n d in p u t ( 2 ) C o n t r a s t c o n t r o l v o lu m e U s e r s e t t i n g s v ia c o m m a n d in p u t ( 3 ) P o w e r c o n t r o l V C , V R , V F = ( 1 , 1 , 1 ) E n d o f in it ia l s e t t in g s L C D d is p la y s c r e e n s e t t in g s D is p la y s t a r t lin e s e t W r it in g s c r e e n d a t a , e t c . D is p la y O N W a it in g f o r m o r e t h a n 3 0 0 m s t o s t a b iliz e t h e L C D p o w e r le v e ls
38 • Product Specification (V1.0) 12.28.2005 The “Modify-read” sequence The “External oscillator input” sequence Set CL frequency select mode Set CL frequency select register Input the clock to OSC pin End Page address set Column address set Set modify-read Dummy read Data read Data write End Change complete No Yes
Product Specification (V1.0) 12.28.2005 PROGRAM EXAMPLES Use Elan Risc II MCU assembly Initialization Setting Example of EPL09060 INI_DRIVER_IC: MOV A,#LCD_COM_RESET ;INITIAL SETTINGS STATE (DEFAULT) CALL WRITE_LCD_1BYTE MOV A,#LCD_COM_DUTY ;SET DUTY 1ST INSTRUCTION CALL WRITE_LCD_1BYTE MOV A,#DUTY_SET ;SET DUTY 2ND INSTRUCTION CALL WRITE_LCD_1BYTE MOV A,#LCD_COM_BIAS ;SET LCD BIAS 1ST INSTRUCTION CALL WRITE_LCD_1BYTE MOV A,BIAS_SET ;SET BIAS 2ND INSTRUCTION CALL WRITE_LCD_1BYTE MOV A,#LCD_COM_FREQ ;SET LCD CL FREQUENCY 1ST INSTRUCTION CALL WRITE_LCD_1BYTE MOV A,#CL_FREQ ;SET CL FREQUENCY 2ND INSTRUCTION CALL WRITE_LCD_1BYTE MOV A,#LCD_ADC_SET ;SET ADC FUNCTION SELECT CALL WRITE_LCD_1BYTE MOV A,#LCD_SHL_SET ;SET SHL FUNCTION SELECT CALL WRITE_LCD_1BYTE MOV A,#LCD_REGULATOR_RES_SET ;SET REGULATOR RESISTOR 1+(Rb/Ra) CALL WRITE_LCD_1BYTE MOV A,#LCD_COM_CONTRAST ;SET CONTRAST 1ST INSTRUCTION CALL WRITE_LCD_1BYTE MOV A,#CONTRAST_SET ;SET CONTRAST 2ND INSTRUCTION CALL WRITE_LCD_1BYTE MOV A,#LCD_POWER_CONTROL_SET ;SET POWER CONTROL (INTERNAL OR EXTERNAL) CALL WRITE_LCD_1BYTE BS REG_CPUCON,F_CKS ;ADD CLOCK BY OSC PIN (CLOCK FROM CPU) MOV A,#150 ;WAITING FOR LCD POWER TO STABILIZE CALL WAIT_A_MS CALL LCD_DISPLAY_ON ;TURN ON LCD MOV A,#LCD_DISPLAY_INI_LINE ;SET INITIAL DISPLAY LINE CALL WRITE_LCD_1BYTE CALL LCD_DATA_WRITE ;WRITING SCREEN DATA RET
40 • Product Specification (V1.0) 12.28.2005 ; Write Display_Picture Data into Display Data Ram of EPL09060 DATA_WRITE: TBPTL #DISPLAY_PICTURE*2 ;DEFINE DISPLAY PICTURE DATA INDEX TBPTM #DISPLAY_PICTURE/0x80 TBPTH #DISPLAY_PICTURE/0x8000 DATA_WRITE_09060: MOV A,#LINE_Y_MAX ;MAX PAGES OF DDRAM MOV REG_LCDARH,A DATA_W1: MOV A,#LINE_X_MAX ;SET MAX SEGMENTS OF DDRAM MOV REG_LCDARL,A BC REG_PORTB,F_LCD_A0 ;SET LCD /A0 = 0 INSTRUCTION OUTPUT MOV A,#LCD_COM_PAGE ADD A,REG_LCDARH CALL WRITE_LCD_1BYTE MOV A,#0b00000000 ;SET LOWER ORDER COLUMN ADDRESS=0000 CALL WRITE_LCD_1BYTE MOV A,#0b00010000 ;SET HIGHER ORDER COLUMN ADDRESS=0000 CALL WRITE_LCD_1BYTE BS REG_PORTB,F_LCD_A0 ;SET LCD /A0 = 1 DATA OUTPUT DATA_W2: TBRD 01,REG_ACC ;ACCESS THE DATA OF DISPLAY_PICTURE CALL WRITE_LCD_1BYTE DEC REG_LCDARL JBS REG_STATUS,F_C,DATA_W2 ;IDENTIFY RES_STATUS CARRY BIT SET OR NOT DEC REG_LCDARH JBS REG_STATUS,F_C,DATA_W1 BC REG_PORTB,F_LCD_A0 ;LCD /A0 = 0 FOR INSTRUCTION OUTPUT RET
Product Specification (V1.0) 12.28.2005 ; Write One Byte Data Into DDRAM (Parallel Mode 80 Series) ;AT FIRST DEFINE A0 TO IDENTIFY DATA OR INSTRUCTION WRITE WRITE_LCD_1BYTE: JBS REG_DCRG,F_LAHEN,WRITE_LCD_1BYTE_1 ;CHECK REG_DCRG LAHEN BIT=1 OR NOT BC REG_PORTC,F_LCD_WR ;SET /WR=0 ENABLE WRITE MOV REG_DATA,A ;MOVE A==> PORT_G NOP ;Write low pulse( Wait for ;2 instruction cycles) NOP BS REG_PORTC,F_LCD_WR ;SET /WR=1 DISABLE WRITE NOP NOP NOP NOP RET WRITE_LCD_1BYTE_1: MOV REG_DATA,A ;MOVE A==> PORT_G RET ;; Read One Byte Data Into DDRAM (Parallel Mode 80 Series) ;AT FIRST DEFINE A0 TO IDENTIFY DATA OR INSTRUCTION READ READ_LCD_1BYTE: BC REG_PORTB,F_LCD_RD ;SET /RD=0 ENABLE READ NOP NOP MOV A,REG_DATA ;MOVE PORT_G ==> A NOP BS REG_PORTB,F_LCD_RD ;SET /RD=1 DISABLE READ NOP RET
42 • Product Specification (V1.0) 12.28.2005
9 Relationship between Setting and Common/Display RAM
The microprocessor (MPU) can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM simultaneously as data is being displayed without causing the LCD to flicker. Page Address P3,P2,P1,P0 Data Column Address Line Address (HEX) 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 A 0 B 0 C 0 D 0 E 0 F 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 A 1 B 1 C 1 D 1 E 1 F 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 COMI COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 PAGE0 PAGE1 PAGE2 PAGE3 PAGE4 PAGE5 PAGE6 ADC = 0 ADC = 1 A B S E G M E N T S E G M E N T S E G M E N T S E G M E N T S E G M E N T S E G M E N T S E G M E N T S E G M E N T A B C D None segment Column Address (HEX) LCD Output COM3 COM2 COM1 COM0 COMI Common Output pins SHL=0 (1/16) Common Output pins SHL=1 (1/16) Common Output pins SHL=1 (1/8) Common Output pins SHL=0 (1/8) COM4 COM5 COM6 COM7 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 Note: 1. The data on Page Address 2~5 would not be output to the common pins, but can be regarded as general data RAM. 2. The EPL09060 will output RAM data (Page 0) to COM0 ~ COM7 (COMI) when using 1/16 (1/17) duty and SHL=0.
Product Specification (V1.0) 12.28.2005 Parameter Applicable Pins Symbol Condition Rate Value Unit Power supply voltage VDD VDD -0.3 to +7 Driver supply voltage VOUT VLCD -0.3 to +17 Input voltage All Input VIN -0.3 to VDD+0.3 V Operating temperature range TA -30 to +80 Storage temperature range -55 to +125 Recommended Operating Conditions Rated Value Parameter Applicable Pins Symbol Condition Min. Typ. Max. Unit Power supply Voltage VDD VDD 2.2 3.4 Voltage converter output voltage VOUT VOUT 4.0 6.8 V0 output voltage 3.0 6.0 VOH 0.7VDD VDD Output voltage VOL VSS 0.3VDD VIH 0.7VDD VDD Input voltage VIL VSS 0.3VDD V Operating temperature range TA OC
44 • Product Specification (V1.0) 12.28.2005
11 DC Characteristics
VSS = 0V, VDD = 2.6 to 3.3V, TA = -30~80°C Rated Value Parameter Applicable Pins Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD VDD 2.2 3.4 Voltage Converter Input Voltage VDD VDD2 2 × boost 2.2 3.4 VREF0 TA=0°C 2.07 2.16 2.25 VREF20 TA=20°C 1.96 1.98 2.05 Reference Voltage VREF40 TA=40°C 1.86 1.94 2.02 Regulated Voltage TA=0~40°C V0-4% V0+4% V VOUT0 VOUT1 VOUT2 VOUT3 OP Amp Voltage Output of LCD Power supply VOUT4 No load 2 and mV Voltage Converter Output Voltage VOUT VOUT × 2 (no-load) 100 LCD Driver ON Resistance COMn SEGn RON Current load load= 50 µA VDD=3V, Vin=0V 400 800 1200 Reset Resistor /RES RRESET VDD=3V, Vin=1.7V kΩ IOH VDD=3V, VOH=2.4V Output Current (Source and Drain) IOL VDD=3V, VOL=0.2V 1.2 2.2 3.2 mA Input Leakage Current All Input IIL VIN=VDD or 0V Output Tri-state ± 3 Dynamic Current Consumption (1/17 duty) IDDD1 VDD=3V, 2 boosting, TA=25°C, internal OSC. fOSC=22kHz, 1/17 duty ratio,1/4.5 bias ratio, DV value=10H, regulator=(0, 0,0), CL=(0, 0, 0), all display pattern off, no load V1 Sink Capability Isv1 V0=3.6V, V1=2.4V (No load) VOH=2.8V 0.75 V4 Source Capability Isv4 V0=3.6V, V4=1.2V (No load) VOL=0.8V -0.75 Current Consumption IDD1 Standby mode Current Consumption IDD2 Sleep mode µA Frame Frequency fFM Hz Internal Oscillator Frequency fOSC TA=25°C External Input Oscillator OSC fOSC TA=25°C kHz
Product Specification (V1.0) 12.28.2005 Note VEV Ra Rb V VREF VEV 252 α LCD Bias 1/8 Bias (7/8) × V0 (6/8) × V0 (2/8) × V0 (1/8) × V0 1/7.5 Bias (6.5/7.5) × V0 (5.5/7.5) × V0 (2/7.5) × V0 (1/7.5) × V0 1/7 Bias (6/7) × V0 (5/7) × V0 (2/7) × V0 (1/7) × V0 1/6.5 Bias (5.5/6.5) × V0 (4.5/6.5) × V0 (2/6.5) × V0 (1/6.5) × V0 1/6 Bias (5/6) × V0 (4/6) × V0 (2/6) × V0 (1/6) × V0 1/5.5 Bias (4.5/5.5) × V0 (3.5/5.5) × V0 (2/5.5) × V0 (1/5.5) × V0 1/5 Bias (4/5) × V0 (3/5) × V0 (2/5) × V0 (1/5) × V0 1/4.5 Bias (3.5/4.5) × V0 (2.5/4.5) × V0 (2/4.5) × V0 (1/4.5) × V0 1/4 Bias (3/4) × V0 (2/4) × V0 (2/4) × V0 (1/4) × V0 1/3.5 Bias (2.5/3.5) × V0 (1.5/3.5) × V0 (2/3.5) × V0 (1/3.5) × V0 1/3 Bias (2/3) × V0 (1/3) × V0 (2/3) × V0 (1/3) × V0 3: The target value of V0~V4 is Theoretical Value ± 50 mV : Input pin D0~D7, A0, /RD, /WR, /CS1, CS2, CLS, C86, IRS : Output pin D0~D7
12 AC Characteristics
/CS1, CS2 tCYCS (SCK) (SDI) (SDO) tDSS tDHS /WR (R/W) tCSS tASS tCLLS tCLHS tCHS tDDS tOHS tAHS
46 • Product Specification (V1.0) 12.28.2005 Serial Interface Timing Characteristics Rated Value Parameter Applicable Pins Symbol Condition Min. Max. Unit Chip Select Setup Time Chip Select Hold Time /CS1 CS2 tCSS tCHS 100 100 Address Setup time Address Hold time R/W tASS tAHS 100 100 Data Setup Time Data Hold Time (SDI) tDSS tDHS DATAÆSCK↑ SCK↑ÆDATA Clock Cycle Time Clock L Time Clock H Time (SCK) tCYCS tCLLS tCLHS 300 100 100 Data Delay Time Data Disable Time (SDO) tDDS tOHS CL= 100 pF ns 80-Family MPU Read/Write Timing Characteristics (VSS= 0V, VDD= 2.6~3.3V, TA=0~40°C) Rated value Parameter Applicable pins Symbol Condition Min. Max. Unit Address Setup Time Address Hold Time tAW8 tAH8 System Cycle Time tCYC8 500 Pulse Width(/WR) Pulse Width(/RD) /WR /RD tCC8 160 200 Data Setup Time Data Hold Time tDS8 tDH8 Read Access Time Output Disable Time D0~D7 tACC8 tOH8 CL=100pF ns /CS1 (CS2) /WR,/RD D0 to D7 (Write) D0 to D7 (Read) tCC8 tCYC8 tDH8 tAH8 tDS8 tACC8 tOH8 tAW8
Product Specification (V1.0) 12.28.2005 68-Family MPU Read/Write Timing Characteristics (VSS = 0V, VDD = 2.6~3.3V, TA=0~40°C) Rated Value Parameter Applicable Pins Symbol Condition Min. Max. Unit Address Setup Time Address Hold Time R/W tAW6 tAH6 System Cycle Time tCYC6 500 Pulse Width (/WR) Pulse Width (/RD) E tEW 160 200 Data Setup Time Data Hold Time tDS6 tDH6 Read Access Time Output Disable Time D0~D7 tACC6 tOH6 CL=100pF ns E /CS1 (CS2) R/W D0 to D7 (Write) D0 to D7 (Read) tcyc6 tEW tAW6 tAH6 tDH6 tOH6 tDS6 tACC6
48 • Product Specification (V1.0) 12.28.2005 Input Pin Configuration (VSS = 0V, VDD = 2.6V~3.3V, TA = 0~40°C) Input/Output Pin Configuration VDD Output data Output enable Input enable VDD
Product Specification (V1.0) 12.28.2005 Output Pin Configuration Reset Input Pin Configuration VDD VDD
50 • Product Specification (V1.0) 12.28.2005 LCD Output Pin Configuration MPU Interface Elan 8-bit MPU (with external memory) COMMON OUTPUT VSS VSS SEGMENT OUTPUT VCC PORT D_1 PORT A,B PORT D_4 PORT D_5 RISC2 M PU PORT G PORT D_2 PORT D_3 /RES GND A0 VCC /CS1 C86 CS2 EPL09060 D0 ~D7 /RD /W R PS /RES GND VDD VDD /RESET VCC /OE R/W /CE FLASH D0 ~D7 A0~An GND VDD LCD PANEL
Product Specification (V1.0) 12.28.2005 Serial Interface (SPI) 80-Family MPU VCC PORT3_1 MPU PORT2 PORT1 PORT0 /RES GND A0 VCC /CS1 C86 CS2 EPL09060 SDI (D7) SCK (D6) SDO (D5) PS /RES GND VDD VDD OR VSS /RESET VDD LCD PANEL VCC A0 A1~A7 /IORQ 80 type MPU D0 ~D7 /RD /WR /RES GND DECODER A0 VCC /CS1 C86 CS2 EPL09060 D0 ~D7 /RD /WR PS /RES GND VDD VDD /RESET
52 • Product Specification (V1.0) 12.28.2005 68-Family MPU VCC A0 A1~A15 VMA 68-Type MPU D0 ~D7 E R/W /RES GND Decoder A0 VCC /CS1 C86 CS2 EPL09060 D0 ~D7 /RD /WR PS /RES GND VDD VDD VDD /RESET
Product Specification (V1.0) 12.28.2005 For customer application circuit V D D COM I1 V D D C1+ C1- C2+ V OU T V 0 V 1 V 2 V 3 V 4 V R GN D GN D PS C86 SEG0 SEG1 CL S OSC IRS /RES D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 CS2 /CS1 A 0 /W R /RD TEST COM 7 COM 6 COM 0 COM I2 SEG59 SEG52 SEG51 SEG50 SEG35 SEG36 SEG37 SEG34 SEG33 EPL 09060 CL S /RES IRS SD I SCK SD O CS2 /CS1 A 0 GN D L CD COM 0 COM 1 COM 2 COM 3 SEG59 SEG0 COM 7 COM 6 COM 5 COM 4 COM I V D D V D D 1uF 1uF 1uF 1uF 1uF 1uF 1uF M CU
54 • Product Specification (V1.0) 12.28.2005