EPF6024A

EPF6010A ALTERA | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 52

Technical content

(1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates. Table 1. FLEX 6000 Device Features

2 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet ...and More

Features

■ Powerful I/O pins – Individual tri-state output enable control for each pin – Programmable output slew-rate control to reduce switching noise – Fast path from register to I/O pin for fast clock-to-output time ■ Flexible interconnect –F a s t T r a c k® Interconnect continuous routing structure for fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – Dedicated cascade chain that implements high-speed, high-fan- in logic functions (automatically used by software tools and megafunctions) – Tri-state emulation that implem ents internal tri-state networks – Four low-skew global paths for clock, clear, preset, or logic signals ■ Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 ■ Flexible package options – Available in a variety of packag es with 100 to 256 pins, including the innovative FineLine BGA TM packages (see Table 2) –S a m e F r a m eTM pin-compatibility (with other FLEX® 6000 devices) across device densities and pin counts – Thin quad flat pack (TQFP), plas tic quad flat pack (PQFP), and ball-grid array (BGA) packages (see Table 2) – Footprint- and pin-compatibility with other FLEX 6000 devices in the same package ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, the library of parameterized modules (LPM), Verilog HDL, VHDL, DesignWare components, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic Table 2. FLEX 6000 Package Options & I/O Pin Count

FLEX 6000 Programmable Logic Device Family Data Sheet General

Description

The Altera® FLEX 6000 programmable logic device (PLD) family provides a low-cost alternative to high-volume gate array designs. FLEX 6000 devices are based on the OptiFLEX architecture, which minimizes die size while maintaining high performance and routability. The devices have reconfigurable SRAM elements, which give designers the flexibility to quickly change their designs during prototyping and design testing. Designers can also change functionality during operation via in-circuit reconfiguration. FLEX 6000 devices are reprogrammable, and they are 100% tested prior to shipment. As a result, designers are not required to generate test vectors for fault coverage purposes, allowing them to focus on simulation and design verification. In addition, the designer does not need to manage inventories of different gate array designs. FLEX 6000 devices are configured on the board for the specific functionality required. Table 3 shows FLEX 6000 performance for some common designs. All performance values shown were obtained using Synopsys DesignWare or LPM functions. Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file. Note: (1) This performance value is measured as a pin-to-pin delay. Table 3. FLEX 6000 Device Performance for Common Designs

4 Altera Corporation

Table 4 shows FLEX 6000 performance for more complex designs. (1) The applications in this table were created using Altera MegaCoreTM functions. Verilog HDL files for simulation with tools such as Cadence Verilog-XL. functions that are optimized for the FLEX 6000 architecture. SPARCstations, and HP 9000 Series 700/800. Software Data Sheet for more information. Table 4. FLEX 6000 Device Performance for Complex Designs Note (1)

FLEX 6000 Programmable Logic Device Family Data Sheet Functional The FLEX 6000 OptiFLEX architecture consists of logic elements (LEs). Each LE includes a 4-input look-up table (LUT), which can implement any 4-input function, a register, and dedicated paths for carry and cascade chain functions. Because each LE contains a register, a design can be easily pipelined without consuming more LEs. The specified gate count for FLEX 6000 devices includes all LUTs and registers. LEs are combined into groups called logic array blocks (LABs); each LAB contains 10 LEs. The Altera software automatically places related LEs into the same LAB, minimizing the number of required interconnects. Each LAB can implement a medium-sized block of logic, such as a counter or multiplexer. Signal interconnections within FLEX 6000 devices—and to and from device pins—are provided via the routing structure of the FastTrack Interconnect. The routing structure is a series of fast, continuous row and column channels that run the entire length and width of the device. Any LE or pin can feed or be fed by any other LE or pin via the FastTrack Interconnect. See “FastTrack Interconnect” on page 17 of this data sheet for more information. Each I/O pin is fed by an I/O element (IOE) located at the end of each row and column of the FastTrack Interconnect. Each IOE contains a bidirectional I/O buffer. Each IOE is placed next to an LAB, where it can be driven by the local interconnect of that LAB. This feature allows fast clock-to-output times of less than 8 ns when a pin is driven by any of the 10 LEs in the adjacent LAB. Also, any LE can drive any pin via the row and column interconnect. I/O pins can drive the LE registers via the row and column interconnect, providing setup times as low as 2 ns and hold times of 0 ns. IOEs provide a variety of features, such as JTAG BST support, slew-rate control, and tri-state buffers. Figure 1 shows a block diagram of the FLEX 6000 OptiFLEX architecture. Each group of ten LEs is combined into an LAB, and the LABs are arranged into rows and columns. The LABs are interconnected by the FastTrack Interconnect. IOEs are located at the end of each FastTrack Interconnect row and column.

6 Altera Corporation

Figure 1. OptiFLEX Architecture Block Diagram need to create a clock tree. efficient routing with optimum device utilization and high performance.

Figure 2. Logic Array Block In most designs, the registers only use global clock and clear signals. two local interconnect areas.

8 Altera Corporation

Figure 3. LAB Control Signals FastTrack Interconnect. See Figure 4. signals are used in counter mode).

Figure 4. Logic Element interconnect and the FastTrack Interconnect. should be limited to speed-critical portions of a design.

10 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Carry Chain The carry chain provides a very fast (0.1 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit drives forward into the higher-order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature allows the FLEX 6000 architecture to implement high-speed counters, adders, and comparators of arbitrary width. Carry chain logic can be created automatically by the Altera software during design processing, or manually by the designer during design entry. Parameterized functions such as LPM and DesignWare functions automatically take advantage of carry chains for the appropriate functions. Because the first LE of each LAB can generate control signals for that LAB, the first LE in each LAB is not included in carry chains. In addition, the inputs of the first LE in each LAB may be used to generate synchronous clear and load enable signals for counters implemented with carry chains. Carry chains longer than nine LEs are implemented automatically by linking LABs together. For enhanced fitting, a long carry chain skips alternate LABs in a row. A carry chain longer than one LAB skips either from an even-numbered LAB to another even-numbered LAB, or from an odd-numbered LAB to another odd-numbered LAB. For example, the last LE of the first LAB in a row carries to the second LE of the third LAB in the row. In addition, the carry chain does not cross the middle of the row. For instance, in the EPF6016 device, the carry chain stops at the 11th LAB in a row and a new carry chain begins at the 12th LAB. Figure 5 shows how an n-bit full adder can be implemented in n + 1 LEs with the carry chain. One portion of the LUT generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the LE. Although the register can be bypassed for simple adders, it can be used for an accumulator function. Another portion of the LUT and the carry chain logic generates the carry-out signal, which is routed directly to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is driven onto the FastTrack Interconnect.

Figure 5. Carry Chain Operation

12 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Cascade Chain The cascade chain enables the FLEX 6000 architecture to implement very wide fan-in functions. Adjacent LUTs can be used to implement portions of the function in parallel; the cascade chain serially connects the intermediate values. The cascade chain can use a logical AND or logical OR gate (via De Morgan’s inversion) to connect the outputs of adjacent LEs. Each additional LE provides four more inputs to the effective width of a function, with a delay as low as 0.5 ns per LE. Cascade chain logic can be created automatically by the Altera software during design processing, or manually by the designer during design entry. Parameterized functions such as LPM and DesignWare functions automatically take advantage of cascade chains for the appropriate functions. A cascade chain implementing an AND gate can use the register in the last LE; a cascade chain implementing an OR gate cannot use this register because of the inversion required to implement the OR gate. Because the first LE of an LAB can generate control signals for that LAB, the first LE in each LAB is not included in cascade chains. Moreover, cascade chains longer than nine bits are automatically implemented by linking several LABs together. For easier routing, a long cascade chain skips every other LAB in a row. A cascade chain longer than one LAB skips either from an even-numbered LAB to another even-numbered LAB, or from an odd-numbered LAB to another odd-numbered LAB. For example, the last LE of the first LAB in a row cascades to the second LE of the third LAB. The cascade chain does not cross the center of the row. For example, in an EPF6016 device, the cascade chain stops at the 11th LAB in a row and a new cascade chain begins at the 12th LAB. Figure 6 shows how the cascade function can connect adjacent LEs to form functions with a wide fan-in. In this example, functions of 4n variables are implemented with n LEs. The cascade chain requires 3.4 ns to decode a 16-bit address.

14 Altera Corporation

Figure 7. LE Operating Modes (1) The register feedback multiplexer is available on LE 2 of each LAB. all LEs other than the second LE in an LAB. (3) The LAB-wide synchronous clear and LAB-wide sy nchronous load affect all registers in an LAB.

FLEX 6000 Programmable Logic Device Family Data Sheet Normal Mode The normal mode is suitable for general logic applications, combinatorial functions, or wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in are inputs to a 4-input LUT. The Altera software automatically selects the carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT output can be combined with the cascade- in signal to form a cascade chain through the cascade-out signal. Arithmetic Mode The arithmetic mode is ideal for implementing adders, accumulators, and comparators. An LE in arithmetic mode uses two 3-input LUTs. One LUT computes a 3-input function; the other generates a carry output. As shown in Figure 7, the first LUT uses the carry-in signal and two data inputs from the LAB local interconnect to generate a combinatorial or registered output. For example, when implementing an adder, this output is the sum of three signals: DATA1, DATA2, and carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports simultaneous use of the cascade chain. The Altera software implements logic functions to use the arithmetic mode automatically where appropriate; the designer does not have to decide how the carry chain will be used. Counter Mode The counter mode offers counter enable, synchronous up/down control, synchronous clear, and synchronous load options. The counter enable and synchronous up/down control signals are generated from the data inputs of the LAB local interconnect. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. Consequently, if any of the LEs in a LAB use counter mode, other LEs in that LAB must be used as part of the same counter or be used for a combinatorial function. In addition, the Altera software automatically places registers that are not in the counter into other LABs. The counter mode uses two 3-input LUTs: one generates the counter data and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading, and another AND gate provides synchronous clearing. If the cascade function is used by an LE in counter mode, the synchronous clear or load will override any signal carried on the cascade chain. The synchronous clear overrides the synchronous load.

16 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Either the counter enable or the up/down control may be used for a given counter. Moreover, the synchronous load can be used as a count enable by routing the register output into the data input automatically when requested by the designer. The second LE of each LAB has a special function for counter mode; the carry-in of the LE can be driven by a fast feedback path from the register. This function gives a faster counter speed for counter carry chains starting in the second LE of an LAB. The Altera software implements functions to use the counter mode automatically where appropriate. The designer does not have to decide how the carry chain will be used. Internal Tri-State Emulation Internal tri-state emulation provides internal tri-states without the limitations of a physical tri-state bus. In a physical tri-state bus, the tri-state buffers’ output enable (OE) signals select which signal drives the bus. However, if multiple OE signals are active, contending signals can be driven onto the bus. Conversely, if no OE signals are active, the bus will float. Internal tri-state emulation resolves contending tri-state buffers to a low value and floating buses to a high value, thereby eliminating these problems. The Altera software automatically implements tri-state bus functionality with a multiplexer. Clear & Preset Logic Control Logic for the programmable register’s clear and preset functions is controlled by the LAB-wide signals LABCTRL1 and LABCTRL2. The LE register has an asynchronous clear that can implement an asynchronous preset. Either LABCTRL1 or LABCTRL2 can control the asynchronous clear or preset. Because the clear and preset functions are active-low, the Altera software automatically assigns a logic high to an unused clear or preset signal. The clear and preset logic is implemented in either the asynchronous clear or asynchronous preset mode, which is chosen during design entry (see Figure 8).

Figure 8. LE Clear & Preset Modes The flipflop can be cleared by either LABCTRL1 or LABCTRL2. a register drives logic or drives a pin. a chip-wide reset pin (DEV_CLRn) that can reset all registers in the device. The option to use this pin is set in the Altera software before compilation. technique to emulate simultaneous preset and clear or asynchronous load. However, this technique uses an additional three LEs per register. increasing the delays between logic resources and reducing performance.

18 Altera Corporation

routes signals from I/O pins to rows. drive I/O pins via the local interconnect. Figure 9. FastTrack Interconnect Architecture n = 186 channels and m = 30 channels.

FLEX 6000 Programmable Logic Device Family Data Sheet A row channel can be driven by an LE or by one of two column channels. These three signals feed a 3-to-1 multiplexer that connects to six specific row channels. Row channels drive into the local interconnect via multiplexers. Each column of LABs is served by a dedicated column interconnect. The LEs in an LAB can drive the column interconnect. The LEs in an LAB, a column IOE, or a row interconnect can drive the column interconnect. The column interconnect can then drive another row’s interconnect to route the signals to other LABs in the device. A signal from the column interconnect must be routed to the row interconnect before it can enter an LAB. Each LE has a FastTrack Interconnect output and a local output. The FastTrack interconnect output can drive six row and two column lines directly; the local output drives the local interconnect. Each local interconnect channel driven by an LE can drive four row and two column channels. This feature provides additional flexibility, because each LE can drive any of ten row lines and four column lines. In addition, LEs can drive global control signals. This feature is useful for distributing internally generated clock, asynchronous clear, and asynchronous preset signals. A pin-driven global signal can also drive data signals, which is useful for high-fan-out data signals. Each LAB drives two groups of local interconnects, which allows an LE to drive two LABs, or 20 LEs, via the local interconnect. The row-to-local multiplexers are used more efficiently, because the multiplexers can now drive two LABs. Figure 10 shows how an LAB connects to row and column interconnects.

20 Altera Corporation

Figure 10. LAB Connections to Row & Column Interconnects output can drive six row channels. from two local interconnect areas.

a fast path for high fan-out signals. Table 5. FLEX 6000 FastTrack Interconnect Resources

22 Altera Corporation

Figure 11. Global Clock & Clear Distribution Note (1) LABs in rows B and C drive global signals. In EPF6024A devices, LABs in rows C and E drive global signals. (2) The local interconnect from LABs C1 and D1 can drive two global control signals on the left side. (3) Global signals drive into every LAB as clock, asynchronous clear, preset, and data signals. (4) The local interconnect from LABs C22 and D22 can drive two global control signals on the right side.

24 Altera Corporation

connects to a column interconnect. Figure 13. IOE Connection to Row Interconnect local interconnect for faster clock-to-output times.

Figure 14. IOE Connection to Column Interconnect count packages form a subset of the higher-ball-count packages. EPF6024A device in a 256-pin FineLine BGA package. out a board to take advantage of this migration (see Figure 15). column interconnect channels. driven to a local interconnect.

26 Altera Corporation

Figure 15. SameFrame Pin-Out Example power sequencing, and hot-socketing for FLEX 6000 devices. Table 6. 3.3-V FLEX 6000 Devices with SameFrame Pin-Outs

TTL levels and are therefore compatible with 3.3-V and 5.0-V inputs. 3.3-V or 5.0-V power supply, depending on the output requirements. on 100-pin TQFP or 100-pin FineLine BGA packages. Table 7 describes FLEX 6000 MultiVolt I/O support. Table 7. FLEX 6000 MultiVolt I/O Support

28 Altera Corporation

require a VIH of 3.5 V. When the open-drain pin is active, it will drive low. When the pin is inactive, the trace will be pulled up to 5.0 V by the resistor. The open-drain pin will only drive low or tri-state; it will never drive high. selecting a pull-up resistor. exceeds 3.3 V. Therefore, the pin does not have to be open-drain. FLEX 6000 devices operate as specified by the user. Table 8. FLEX 6000 JTAG Instructions normal device operation, and permits an initial data pattern to be output at the device pins. pattern at the output pins and capturing test result at the input pins.

30 Altera Corporation

Figure 17. AC Test Conditions Table 10. JTAG Timing Parameters & Values not be performed under AC conditions.

capacitance for 5.0-V and 3.3-V FLEX 6000 devices. Table 11. FLEX 6000 5.0-V Device Absolute Maximum Ratings Note (1) Table 12. FLEX 6000 5.0-V Device Recommended Operating Conditions

32 Altera Corporation

(1) See the Operating Requirements for Altera Devices Data Sheet. input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. (4) Maximum V CC rise time to 100 ms. VCC must rise monotonically. (5) Typical values are for T A = 25° C and VCC = 5.0 V. (7) The I OH parameter refers to high-level TTL or CMOS output current. (9) Capacitance is sample-tested only. Table 13. FLEX 6000 5.0-V Device DC Operating Conditions Notes (5), (6) Table 14. FLEX 6000 5.0-V Device Capacitance Note (9)

Table 15. FLEX 6000 3.3-V Device Absolute Maximum Ratings Note (1) Table 16. FLEX 6000 3.3-V Device Recommended Operating Conditions

34 Altera Corporation

(1) See the Operating Requirements for Altera Devices Data Sheet. 5.75 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. (4) Maximum V CC rise time is 100 ms. VCC must rise monotonically. (5) Typical values are for T A = 25° C and VCC = 3.3 V. (6) These values are specified under Table 16 on page 33. (7) The I OH parameter refers to high-level TTL or CMOS output current. (9) Capacitance is sample-tested only. Table 17. FLEX 6000 3.3-V Device DC Operating Conditions Notes (5), (6) Table 18. FLEX 6000 3.3-V Device Capacitance Note (9)

Figure 18. Output Drive Characteristics

75 IOL

36 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Timing Model The continuous, high-performance FastTrack Interconnect routing resources ensure predictable performance and accurate simulation and timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and therefore have unpredictable performance. Device performance can be estimated by following the signal path from a source, through the interconnect, to the destination. For example, the registered performance between two LEs on the same row can be calculated by adding the following parameters: ■ LE register clock-to-output delay (tCO + tREG_TO_OUT) ■ Routing delay (tROW + tLOCAL) ■ LE LUT delay (tDATA_TO_REG) ■ LE register setup time (tSU) The routing delay depends on the placement of the source and destination LEs. A more complex registered path may involve multiple combinatorial LEs between the source and destination LEs. Timing simulation and delay prediction are available with the Simulator and Timing Analyzer, or with industry-standard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer provides point-to-point timing delay information, setup and hold time analysis, and device-wide performance analysis. Figure 19 shows the overall timing model, which maps the possible routing paths to and from the various elements of the FLEX 6000 device.

Figure 19. FLEX 6000 Timing Model

38 Altera Corporation

Table 19. LE Timing Microparameters Note (1)

Table 20. IOE Timing Microparameters Note (1) Table 21. Interconnect Timing Microparameters Note (1) Table 22. External Reference Timing Parameters

40 Altera Corporation

VCCIO = 5.0 V ± 5% for commercial use in 5.0-V FLEX 6000 devices. VCCIO = 5.0 V ± 10% for industrial use in 5.0-V FLEX 6000 devices. VCCIO = 3.3 V ± 10% for commercial or industrial use in 3.3-V FLEX 6000 devices. VCCIO = 3.3 V ± 10% for commercial or industrial use in 5.0-V FLEX 6000 devices. VCCIO = 2.5 V ± 0.2 V for commercial or industrial use in 3.3-V FLEX 6000 devices. analysis are required to determine actual worst-case performance. (6) This timing parameter shows the delay of a register-to-register test pattern and is used to determine speed grades. (7) This timing parameter is shown for refere nce and is specified by characterization. (8) This timing parameter is sp ecified by characterization. Table 23. External Timing Parameters Table 24. LE Timing Microparameters for EPF6010A & EPF6016A Devices (Part 1 of 2)

Table 25. IOE Timing Microparameters for EPF6010A & EPF6016A Devices Table 24. LE Timing Microparameters for EPF6010A & EPF6016A Devices (Part 2 of 2)

42 Altera Corporation

Increase Input Delay option turned off. (2) Hold time is zero when the Increase Input Delay option is turned on. Table 26. Interconnect Timing Microparameters for EPF6010A & EPF6016A Devices Table 27. External Reference Timing Parameters for EPF6010A & EPF6016A Devices Table 28. External Timing Parameters for EPF6010A & EPF6016A Devices

Tables 29 through 33 show the timing information for EPF6016 devices. Table 29. LE Timing Microparameters for EPF6016 Devices Table 30. IOE Timing Microparameters for EPF6016 Devices

44 Altera Corporation

Table 31. Interconnect Timing Microparameters for EPF6016 Devices Table 32. External Reference Timing Parameters for EPF6016 Devices

Tables 34 through 38 show the timing information for EPF6024A devices. Table 33. External Timing Parameters for EPF6016 Devices Table 34. LE Timing Microparameters for EPF6024A Devices

46 Altera Corporation

Table 35. IOE Timing Microparameters for EPF6024A Devices Table 36. Interconnect Timing Microparameters for EPF6024A Devices Table 37. External Reference Timing Parameters for EPF6024A Devices

Increase Input Delay option turned off. (2) Hold time is zero when the Increase Input Delay option is turned on. guidelines given in Application Note 74 (Evaluating Power for Altera Devices). Table 38. External Timing Parameters for EPF6024A Devices Table 39. K Constant Values

48 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet This calculation provides an ICC estimate based on typical conditions with no output load. The actual ICC should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. To better reflect actual designs, the power model (and the constant K in the power calculation equations shown above) for continuous interconnect FLEX devices assumes that LEs drive FastTrack Interconnect channels. In contrast, the power model of segmented FPGAs assumes that all LEs drive only one short interconnect segment. This assumption may lead to inaccurate results, compared to measured power consumption for an actual design in a segmented interconnect FPGA. Figure 20 shows the relationship between the current and operating frequency for EPF6010A, EPF6016, EPF6016A, and EPF6024A devices.

Figure 20. ICCACTIVE vs. Operating Frequency pins names, and timing parameters.

50 Altera Corporation

than 100 ms and is used to dynamically reconfigure an entire system. (nCE) and configuration enable output (nCEO) pins on each device. Table 40 shows the data sources for each configuration scheme. Table 40. Configuration Schemes

FLEX 6000 Programmable Logic Device Family Data Sheet Device Pin- Outs See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information.

Altera, BitBlaster, ByteBlasterMV, Fa stFlex, FastTrack, FineLine BGA, FLEX, MasterBlaster, MAX+PLUS II, MegaCore, MultiVolt, OptiFLEX, Quartus, SameFrame, and specific device designations are trademarks and/or service marks of Altera Corporation in the United States and other countries. Altera acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, specifically: Verilog is a registered trademark of and Verilog-XL is a trademarks of Cadence Design Systems, Inc. DATA I/O is a registered trademark of Data I/O Corporation. HP is a registered trademark of Hewlett- Packard Company. Exemplar Logic is a registered trademark of Exemplar Logic, Inc. Pentium is a registered trademark of Intel Corporation. Mentor Graphics is a registered trademark of Mentor Graphics Corporation. OrCAD is a registered trademark of OrCAD Systems, Corporation. SPARCstation is a registered trademark of SPARC International, Inc. and is licensed exclusively to Sun Microsystems, Inc. Sun Workstation is a registered trademark of, and Sun is a registered trademark of Sun Microsystems, Inc. Synopsys is a registered trademark and DesignTime, HDL Compiler, and De signWare are trademarks of Synopsys, Inc. VeriBest is a registered trademark of Viewlogic System s, Inc. Viewlogic is a registered trad emark of Viewlogic Sy stems, Inc. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writin g by Altera Corporation. Altera customers are advised to obtain the latest version of device specif ications before relying on any published information and before placing orders for products or services. Copyright © 2001 Altera Corporation. All rights reserved.

101 Innovation Drive

San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: (888) 3-ALTERA lit_req@altera.com FLEX 6000 Programmable Logic Device Family Data Sheet

52 Altera Corporation

Printed on Recycled Paper.