EPF10K200S

EPF10K30E ALTERA | Alldatasheet

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33 MHz or 66 MHz

FLEX 10K Embedded Programmable Logic Family Data Sheet. Table 1. FLEX 10KE Device Features

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FLEX 10KE Embedded Programmable Logic Devices Data Sheet Note to tables: (1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum system gates. (2) New EPF10K100B designs should use EPF10K100E devices. ...and More

Features

– Fabricated on an advanced process and operate with a 2.5-V internal supply voltage – In-circuit reconfigurability (ICR) via external configuration devices, intelligent controller, or JTAG port – ClockLock TM and ClockBoostTM options for reduced clock delay/skew and clock multiplication – Built-in low-skew clock distribution trees –1 0 0 % functional testing of all devices; test vectors or scan chains are not required – Pull-up on I/O pins before and during configuration ■ Flexible interconnect –F a s t T r a c k® Interconnect continuous routing structure for fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) – Tri-state emulation that implements internal tri-state buses – Up to six global clock signals and four global clear signals ■ Powerful I/O pins – Individual tri-state output enable control for each pin – Open-drain option on each I/O pin – Programmable output slew-rate control to reduce switching noise –C l a m p t o VCCIO user-selectable on a pin-by-pin basis – Supports hot-socketing Table 2. FLEX 10KE Device Features

pack (RQFP), pin-grid array (PGA), and ball-grid array (BGA) packages. planning device migration, use the I/O pins that are common to all devices. Table 3. FLEX 10KE Package Options & I/O Pin Count Notes (1), (2)

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FLEX 10KE Embedded Programmable Logic Devices Data Sheet General

Description

Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices. Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions. With up to 200,000 typical gates, FLEX 10KE devices provide the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device. The ability to reconfigure FLEX 10KE devices enables 100% testing prior to shipment and allows the designer to focus on simulation and design verification. FLEX 10KE reconfigurability eliminates inventory management for gate array designs and generation of test vectors for fault coverage. Table 5 shows FLEX 10KE performance for some common designs. All performance values were obtained with Synopsys DesignWare or LPM functions. Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file. Table 4. FLEX 10KE Package Sizes

(1) This application uses combinatorial inputs and outputs. (2) This application uses registered inputs and outputs. designs are available as Altera MegaCore® functions. Table 5. FLEX 10KE Performance Table 6. FLEX 10KE Performance for Complex Designs

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FLEX 10KE Embedded Programmable Logic Devices Data Sheet Similar to the FLEX 10KE architecture, embedded gate arrays are the fastest-growing segment of the gate array market. As with standard gate arrays, embedded gate arrays implement general logic in a conventional “sea-of-gates” architecture. Additionally, embedded gate arrays have dedicated die areas for implementing large, specialized functions. By embedding functions in silicon, embedded gate arrays reduce die area and increase speed when compared to standard gate arrays. While embedded megafunctions typically cannot be customized, FLEX 10KE devices are programmable, providing the designer with full control over embedded megafunctions and general logic, while facilitating iterative design changes during debugging. Each FLEX 10KE device contains an embedded array and a logic array. The embedded array is used to implement a variety of memory functions or complex logic functions, such as digital signal processing (DSP), wide data-path manipulation, microcontroller applications, and data- transformation functions. The logic array performs the same function as the sea-of-gates in the gate array and is used to implement general logic such as counters, adders, state machines, and multiplexers. The combination of embedded and logic arrays provides the high performance and high density of embedded gate arrays, enabling designers to implement an entire system on a single device. FLEX 10KE devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers the EPC1, EPC2, and EPC16 configuration devices, which configure FLEX 10KE devices via a serial data stream. Configuration data can also be downloaded from system RAM or via the Altera BitBlaster TM, ByteBlasterMVTM, or MasterBlaster download cables. After a FLEX 10KE device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Because reconfiguration requires less than 85 ms, real-time changes can be made during system operation. FLEX 10KE devices contain an interface that permits microprocessors to configure FLEX 10KE devices serially or in-parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat a FLEX 10KE device as memory and configure it by writing to a virtual memory location, making it easy to reconfigure the device.

FLEX 10KE Embedded Programmable Logic Devices Data Sheet f For more information on FLEX device configuration, see the following documents: ■ Configuration Devices for APEX & FLEX Devices Data Sheet ■ BitBlaster Serial Download Cable Data Sheet ■ ByteBlasterMV Parallel Port Download Cable Data Sheet ■ MasterBlaster Download Cable Data Sheet ■ Application Note 116 (Configuring APEX 20K, FLEX 10K, & FLEX 6000 Devices) FLEX 10KE devices are supported by the Altera development systems, which are integrated packages that offer schematic, text (including AHDL), and waveform design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, and device configuration. The Altera software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX workstation-based EDA tools. The Altera software works easily with common gate array EDA tools for synthesis and simulation. For example, the Altera software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the Altera software contains EDA libraries that use device- specific features such as carry chains, which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the Altera development system includes DesignWare functions that are optimized for the FLEX 10KE architecture. The Altera development system runs on Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800. f See the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet for more information.

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FLEX 10KE Embedded Programmable Logic Devices Data Sheet Functional Each FLEX 10KE device contains an enhanced embedded array to implement memory and specialized logic functions, and a logic array to implement general logic. The embedded array consists of a series of EABs. When implementing memory functions, each EAB provides 4,096 bits, which can be used to create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions. When implementing logic, each EAB can contribute 100 to 600 gates towards complex logic functions, such as multipliers, microcontrollers, state machines, and DSP functions. EABs can be used independently, or multiple EABs can be combined to implement larger functions. The logic array consists of logic array blocks (LABs). Each LAB contains eight LEs and a local interconnect. An LE consists of a four-input look-up table (LUT), a programmable flipflop, and dedicated signal paths for carry and cascade functions. The eight LEs can be used to create medium-sized blocks of logic—such as 8-bit counters, address decoders, or state machines—or combined across LABs to create larger logic blocks. Each LAB represents about 96 usable gates of logic. Signal interconnections within FLEX 10KE devices (as well as to and from device pins) are provided by the FastTrack Interconnect routing structure, which is a series of fast, continuous row and column channels that run the entire length and width of the device. Each I/O pin is fed by an I/O element (IOE) located at the end of each row and column of the FastTrack Interconnect routing structure. Each IOE contains a bidirectional I/O buffer and a flipflop that can be used as either an output or input register to feed input, output, or bidirectional signals. When used with a dedicated clock pin, these registers provide exceptional performance. As inputs, they provide setup times as low as 0.9 ns and hold times of 0 ns. As outputs, these registers provide clock-to-output times as low as 3.0 ns. IOEs provide a variety of features, such as JTAG BST support, slew-rate control, tri-state buffers, and open-drain outputs.

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FLEX 10KE Embedded Programmable Logic Devices Data Sheet Embedded Array Block The EAB is a flexible block of RAM, with registers on the input and output ports, that is used to implement common gate array megafunctions. Because it is large and flexible, the EAB is suitable for functions such as multipliers, vector scalars, and error correction circuits. These functions can be combined in applications such as digital filters and microcontrollers. Logic functions are implemented by programming the EAB with a read- only pattern during configuration, thereby creating a large LUT. With LUTs, combinatorial functions are implemented by looking up the results, rather than by computing them. This implementation of combinatorial functions can be faster than using algorithms implemented in general logic, a performance advantage that is further enhanced by the fast access times of EABs. The large capacity of EABs enables designers to implement complex functions in one logic level without the routing delays associated with linked LEs or field-programmable gate array (FPGA) RAM blocks. For example, a single EAB can implement any function with 8 inputs and 16 outputs. Parameterized functions such as LPM functions can take advantage of the EAB automatically. The FLEX 10KE EAB provides advantages over FPGAs, which implement on-board RAM as arrays of small, distributed RAM blocks. These small FPGA RAM blocks must be connected together to make RAM blocks of manageable size. The RAM blocks are connected together using multiplexers implemented with more logic blocks. These extra multiplexers cause extra delay, which slows down the RAM block. FPGA RAM blocks are also prone to routing problems because small blocks of RAM must be connected together to make larger blocks. In contrast, EABs can be used to implement large, dedicated blocks of RAM that eliminate these timing and routing concerns. The FLEX 10KE enhanced EAB adds dual-port capability to the existing EAB structure. The dual-port structure is ideal for FIFO buffers with one or two clocks. The FLEX 10KE EAB can also support up to 16-bit-wide RAM blocks and is backward-compatible with any design containing FLEX 10K EABs. The FLEX 10KE EAB can act in dual-port or single-port mode. When in dual-port mode, separate clocks may be used for EAB read and write sections, which allows the EAB to be written and read at different rates. It also has separate synchronous clock enable signals for the EAB read and write sections, which allow independent control of these sections.

simultaneous read or writes. output registers (see Figure 2). Figure 2. FLEX 10KE Device in Dual-Port RAM Mode Notes (1) (1) All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset. EPF10K200E devices have 104 EAB local interconnect channels.

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applications where both ports can read or write, as shown in Figure 3. Figure 3. FLEX 10KE EAB in Dual-Port RAM Mode backward-compatibility with FLEX 10K designs (see Figure 4).

Figure 4. FLEX 10KE Device in Single-Port RAM Mode EPF10K130E, EPF10K200E, and EPF10K200S devices have 104 EAB local interconnect channels. and hold time specifications of the global clock.

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Figure 5. FLEX 10KE EAB Memory Configurations Figure 6. Examples of Combining FLEX 10KE EABs EABs to meet a designer’s RAM specifications.

FLEX 10KE Embedded Programmable Logic Devices Data Sheet EABs provide flexible options for driving and controlling clock signals. Different clocks and clock enables can be used for reading and writing to the EAB. Registers can be independently inserted on the data input, EAB output, write address, write enable signals, read address, and read enable signals. The global signals and the EAB local interconnect can drive write enable, read enable, and clock enable signals. The global signals, dedicated clock pins, and EAB local interconnect can drive the EAB clock signals. Because the LEs drive the EAB local interconnect, the LEs can control write enable, read enable, clear, clock, and clock enable signals. An EAB is fed by a row interconnect and can drive out to row and column interconnects. Each EAB output can drive up to two row channels and up to two column channels; the unused row channel can be driven by other LEs. This feature increases the routing resources available for EAB outputs (see Figures 2 and 4). The column interconnect, which is adjacent to the EAB, has twice as many channels as other columns in the device. Logic Array Block An LAB consists of eight LEs, their associated carry and cascade chains, LAB control signals, and the LAB local interconnect. The LAB provides the coarse-grained structure to the FLEX 10KE architecture, facilitating efficient routing with optimum device utilization and high performance (see Figure 7).

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Figure 7. FLEX 10KE LAB row; EPF10K100E, EPF10K130E, EPF10K200E, and EPF10K200S devices have 26. EPF10K130E, EPF10K200E, and EPF10K200S devices have 34.

addition, the global control signals can be generated from LE outputs. Interconnect routing structure (see Figure 8). Figure 8. FLEX 10KE Logic Element

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FLEX 10KE Embedded Programmable Logic Devices Data Sheet The programmable flipflop in the LE can be configured for D, T, JK, or SR operation. The clock, clear, and preset control signals on the flipflop can be driven by global signals, general-purpose I/O pins, or any internal logic. For combinatorial functions, the flipflop is bypassed and the output of the LUT drives the output of the LE. The LE has two outputs that drive the interconnect: one drives the local interconnect and the other drives either the row or column FastTrack Interconnect routing structure. The two outputs can be controlled independently. For example, the LUT can drive one output while the register drives the other output. This feature, called register packing, can improve LE utilization because the register and the LUT can be used for unrelated functions. The FLEX 10KE architecture provides two types of dedicated high-speed data paths that connect adjacent LEs without using local interconnect paths: carry chains and cascade chains. The carry chain supports high-speed counters and adders and the cascade chain implements wide-input functions with minimum delay. Carry and cascade chains connect all LEs in a LAB as well as all LABs in the same row. Intensive use of carry and cascade chains can reduce routing flexibility. Therefore, the use of these chains should be limited to speed-critical portions of a design. Carry Chain The carry chain provides a very fast (as low as 0.2 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit drives forward into the higher-order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature allows the FLEX 10KE architecture to implement high-speed counters, adders, and comparators of arbitrary width efficiently. Carry chain logic can be created automatically by the Altera Compiler during design processing, or manually by the designer during design entry. Parameterized functions such as LPM and DesignWare functions automatically take advantage of carry chains. Carry chains longer than eight LEs are automatically implemented by linking LABs together. For enhanced fitting, a long carry chain skips alternate LABs in a row. A carry chain longer than one LAB skips either from even-numbered LAB to even-numbered LAB, or from odd- numbered LAB to odd-numbered LAB. For example, the last LE of the first LAB in a row carries to the first LE of the third LAB in the row. The carry chain does not cross the EAB at the middle of the row. For instance, in the EPF10K50E device, the carry chain stops at the eighteenth LAB and a new one begins at the nineteenth LAB.

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design processing, or manually by the designer during design entry. Figure 10. FLEX 10KE Cascade Chain Operation

FLEX 10KE Embedded Programmable Logic Devices Data Sheet LE Operating Modes The FLEX 10KE LE can operate in the following four modes: ■ Normal mode ■ Arithmetic mode ■ Up/down counter mode ■ Clearable counter mode Each of these modes uses LE resources differently. In each mode, seven available inputs to the LE—the four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous LE—are directed to different destinations to implement the desired logic function. Three inputs to the LE provide clock, clear, and preset control for the register. The Altera software, in conjunction with parameterized functions such as LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers. If required, the designer can also create special-purpose functions that use a specific LE operating mode for optimal performance. The architecture provides a synchronous clock enable to the register in all four modes. The Altera software can set DATA1 to enable the register synchronously, providing easy implementation of fully synchronous designs.

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Figure 11 shows the LE operating modes. Figure 11. FLEX 10KE LE Operating Modes

FLEX 10KE Embedded Programmable Logic Devices Data Sheet Normal Mode The normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in are inputs to a four-input LUT. The Altera Compiler automatically selects the carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal. Either the register or the LUT can be used to drive both the local interconnect and the FastTrack Interconnect routing structure at the same time. The LUT and the register in the LE can be used independently (register packing). To support register packing, the LE has two outputs; one drives the local interconnect, and the other drives the FastTrack Interconnect routing structure. The DATA4 signal can drive the register directly, allowing the LUT to compute a function that is independent of the registered signal; a three-input function can be computed in the LUT, and a fourth independent signal can be registered. Alternatively, a four-input function can be generated, and one of the inputs to this function can be used to drive the register. The register in a packed LE can still use the clock enable, clear, and preset signals in the LE. In a packed LE, the register can drive the FastTrack Interconnect routing structure while the LUT drives the local interconnect, or vice versa. Arithmetic Mode The arithmetic mode offers 2 three-input LUTs that are ideal for implementing adders, accumulators, and comparators. One LUT computes a three-input function; the other generates a carry output. As shown in Figure 11 on page 22, the first LUT uses the carry-in signal and two data inputs from the LAB local interconnect to generate a combinatorial or registered output. For example, in an adder, this output is the sum of three signals: a, b, and carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports simultaneous use of the cascade chain. Up/Down Counter Mode The up/down counter mode offers counter enable, clock enable, synchronous up/down control, and data loading options. These control signals are generated by the data inputs from the LAB local interconnect, the carry-in signal, and output feedback from the programmable register. Use 2 three-input LUTs: one generates the counter data, and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading. Data can also be loaded asynchronously with the clear and preset register control signals without using the LUT resources.

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FLEX 10KE Embedded Programmable Logic Devices Data Sheet Clearable Counter Mode The clearable counter mode is similar to the up/down counter mode, but supports a synchronous clear instead of the up/down control. The clear function is substituted for the cascade-in signal in the up/down counter mode. Use 2 three-input LUTs: one generates the counter data, and the other generates the fast carry bit. Synchronous loading is provided by a 2-to-1 multiplexer. The output of this multiplexer is AND ed with a synchronous clear signal. Internal Tri-State Emulation Internal tri-state emulation provides internal tri-states without the limitations of a physical tri-state bus. In a physical tri-state bus, the tri-state buffers’ output enable (OE) signals select which signal drives the bus. However, if multiple OE signals are active, contending signals can be driven onto the bus. Conversely, if no OE signals are active, the bus will float. Internal tri-state emulation resolves contending tri-state buffers to a low value and floating buses to a high value, thereby eliminating these problems. The Altera software automatically implements tri-state bus functionality with a multiplexer. Clear & Preset Logic Control Logic for the programmable register’s clear and preset functions is controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The clear and preset control structure of the LE asynchronously loads signals into a register. Either LABCTRL1 or LABCTRL2 can control the asynchronous clear. Alternatively, the register can be set up so that LABCTRL1 implements an asynchronous load. The data to be loaded is driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the register. During compilation, the Altera Compiler automatically selects the best control signal implementation. Because the clear and preset functions are active-low, the Compiler automatically assigns a logic high to an unused clear or preset. The clear and preset logic is implemented in one of the following six modes chosen during design entry: ■ Asynchronous clear ■ Asynchronous preset ■ Asynchronous clear and preset ■ Asynchronous load with clear ■ Asynchronous load with preset ■ Asynchronous load without clear or preset

of how to setup the preset and clear inputs for the desired functionality. Figure 12. FLEX 10KE LE Clear & Preset Modes

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FLEX 10KE Embedded Programmable Logic Devices Data Sheet Asynchronous Clear The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this mode, the preset signal is tied to VCC to deactivate it. Asynchronous Preset An asynchronous preset is implemented as an asynchronous load, or with an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRL1 asynchronously loads a one into the register. Alternatively, the Altera software can provide preset control by using the clear and inverting the input and output of the register. Inversion control is available for the inputs to both LEs and IOEs. Therefore, if a register is preset by only one of the two LABCTRL signals, the DATA3 input is not needed and can be used for one of the LE operating modes. Asynchronous Preset & Clear When implementing asynchronous clear and preset, LABCTRL1 controls the preset and LABCTRL2 controls the clear. DATA3 is tied to VCC, so that asserting LABCTRL1 asynchronously loads a one into the register, effectively presetting the register. Asserting LABCTRL2 clears the register. Asynchronous Load with Clear When implementing an asynchronous load in conjunction with the clear, LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear. LABCTRL2 implements the clear by controlling the register clear; LABCTRL2 does not have to feed the preset circuits. Asynchronous Load with Preset When implementing an asynchronous load in conjunction with preset, the Altera software provides preset control by using the clear and inverting the input and output of the register. Asserting LABCTRL2 presets the register, while asserting LABCTRL1 loads the register. The Altera software inverts the signal that drives DATA3 to account for the inversion of the register’s output. Asynchronous Load without Preset or Clear When implementing an asynchronous load without preset or clear, LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear.

FLEX 10KE Embedded Programmable Logic Devices Data Sheet FastTrack Interconnect Routing Structure In the FLEX 10KE architecture, connections between LEs, EABs, and device I/O pins are provided by the FastTrack Interconnect routing structure, which is a series of continuous horizontal and vertical routing channels that traverses the device. This global routing structure provides predictable performance, even in complex designs. In contrast, the segmented routing in FPGAs requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. The FastTrack Interconnect routing structure consists of row and column interconnect channels that span the entire device. Each row of LABs is served by a dedicated row interconnect. The row interconnect can drive I/O pins and feed other LABs in the row. The column interconnect routes signals between rows and can drive I/O pins. Row channels drive into the LAB or EAB local interconnect. The row signal is buffered at every LAB or EAB to reduce the effect of fan-out on delay. A row channel can be driven by an LE or by one of three column channels. These four signals feed dual 4-to-1 multiplexers that connect to two specific row channels. These multiplexers, which are connected to each LE, allow column channels to drive row channels even when all eight LEs in a LAB drive the row interconnect. Each column of LABs or EABs is served by a dedicated column interconnect. The column interconnect that serves the EABs has twice as many channels as other column interconnects. The column interconnect can then drive I/O pins or another row’s interconnect to route the signals to other LABs or EABs in the device. A signal from the column interconnect, which can be either the output of a LE or an input from an I/O pin, must be routed to the row interconnect before it can enter a LAB or EAB. Each row channel that is driven by an IOE or EAB can drive one specific column channel. Access to row and column channels can be switched between LEs in adjacent pairs of LABs. For example, a LE in one LAB can drive the row and column channels normally driven by a particular LE in the adjacent LAB in the same row, and vice versa. This flexibility enables routing resources to be used more efficiently (see Figure 13).

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Figure 13. FLEX 10KE LAB Connections to Row & Column Interconnect

saving the other half of the channel for the other half of the row. resources available in each FLEX 10KE device. they can feed the local interconnect of each LAB in the device. LAB B3 is in row B, column 3. Table 7. FLEX 10KE FastTrack Interconnect Resources

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Figure 14. FLEX 10KE Interconnect Resources

Figure 15. FLEX 10KE Bidirectional I/O Registers

2 Dedicated

4 Dedicated

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FLEX 10KE Embedded Programmable Logic Devices Data Sheet On all FLEX 10KE devices (except EPF10K50E and EPF10K200E devices), the input path from the I/O pad to the FastTrack Interconnect has a programmable delay element that can be used to guarantee a zero hold time. EPF10K50S and EPF10K200S devices also support this feature. Depending on the placement of the IOE relative to what it is driving, the designer may choose to turn on the programmable delay to ensure a zero hold time or turn it off to minimize setup time. This feature is used to reduce setup time for complex pin-to-register paths (e.g., PCI designs). Each IOE selects the clock, clear, clock enable, and output enable controls from a network of I/O control signals called the peripheral control bus. The peripheral control bus uses high-speed drivers to minimize signal skew across the device and provides up to 12 peripheral control signals that can be allocated as follows: ■ Up to eight output enable signals ■ Up to six clock enable signals ■ Up to two clock signals ■ Up to two clear signals If more than six clock enable or eight output enable signals are required, each IOE on the device can be controlled by clock enable and output enable signals driven by specific LEs. In addition to the two clock signals available on the peripheral control bus, each IOE can use one of two dedicated clock pins. Each peripheral control signal can be driven by any of the dedicated input pins or the first LE of each LAB in a particular row. In addition, a LE in a different row can drive a column interconnect, which causes a row interconnect to drive the peripheral control signal. The chip- wide reset signal resets all IOE registers, overriding any other control signals. When a dedicated clock pin drives IOE registers, it can be inverted for all IOEs in the device. All IOEs must use the same sense of the clock. For example, if any IOE uses the inverted clock, all IOEs must use the inverted clock and no IOE can use the non-inverted clock. However, LEs can still use the true or complement of the clock on a LAB-by-LAB basis. The incoming signal may be inverted at the dedicated clock pin and will drive all IOEs. For the true and complement of a clock to be used to drive IOEs, drive it into both global clock pins. One global clock pin will supply the true, and the other will supply the complement. When the true and complement of a dedicated input drives IOE clocks, two signals on the peripheral control bus are consumed, one for each sense of the clock.

Table 8. Peripheral Bus Sources for EPF10K30E, EPF10K50E & EPF10K50S Devices

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driven to a known logic state (such as ground) and not be allowed to float. can also be reset by the chip-wide reset pin. Table 9. Peripheral Bus Sources for EPF10K100E, EPF10K130E, EPF10K200E & EPF10K200S Devices

each row channel (see Figure 16). Figure 16. FLEX 10KE Row-to-IOE Connections Table 10 lists the FLEX 10KE row-to-IOE interconnect resources. The values for m and n are provided in Table 10. Table 10. FLEX 10KE Row-to-IOE Interconnect Resources

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for each IOE (see Figure 17). Figure 17. FLEX 10KE Column-to-IOE Connections Table 11 lists the FLEX 10KE column-to-IOE interconnect resources. The values for m and n are provided in Table 11. Table 11. FLEX 10KE Column-to-IOE Interconnect Resources

count packages form a subset of the higher-ball-count packages. take advantage of this migration (see Figure 18). Figure 18. SameFrame Pin-Out Example

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FLEX 10KE Embedded Programmable Logic Devices Data Sheet ClockLock & ClockBoost To support high-speed designs, FLEX 10KE devices offer optional ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL) used to increase design speed and reduce resource usage. The ClockLock circuitry uses a synchronizing PLL that reduces the clock delay and skew within a device. This reduction minimizes clock-to-output and setup times while maintaining zero hold times. The ClockBoost circuitry, which provides a clock multiplier, allows the designer to enhance device area efficiency by resource sharing within the device. The ClockBoost feature allows the designer to distribute a low-speed clock and multiply that clock on-device. Combined, the ClockLock and ClockBoost features provide significant improvements in system performance and bandwidth. All FLEX 10KE devices, except EPF10K50E and EPF10K200E devices, support ClockLock and ClockBoost circuitry. EPF10K50S and EPF10K200S devices support this circuitry. Devices that support Clock- Lock and ClockBoost circuitry are distinguished with an “X” suffix in the ordering code; for instance, the EPF10K200SFC672-1X device supports this circuit. The ClockLock and ClockBoost features in FLEX 10KE devices are enabled through the Altera software. External devices are not required to use these features. The output of the ClockLock and ClockBoost circuits is not available at any of the device pins. The ClockLock and ClockBoost circuitry locks onto the rising edge of the incoming clock. The circuit output can drive the clock inputs of registers only; the generated clock cannot be gated or inverted. The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and ClockBoost circuitry. When the dedicated clock pin is driving the ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device. For designs that require both a multiplied and non-multiplied clock, the clock trace on the board can be connected to the GCLK1 pin. In the Altera software, the GCLK1 pin can feed both the ClockLock and ClockBoost circuitry in the FLEX 10KE device. However, when both circuits are used, the other clock pin cannot be used.

Figure 19. Specifications for Incoming & Generated Clocks nominal output clock period.

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for -1 and -2 speed-grade devices, respectively. Table 12. ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices

input frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. device operation. Simulation does not reflect this parameter. (2) Twenty-five thousand parts per million (PPM) equates to 2.5 % of input clock period. LOCK value is less than the time required for configuration. tINCLKSTB is lower than 50 ps. Project Device Options dialog box (Assign menu). Table 13. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices

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FLEX 10KE Embedded Programmable Logic Devices Data Sheet PCI Pull-Up Clamping Diode Option FLEX 10KE devices have a pull-up clamping diode on every I/O, dedicated input, and dedicated clock pin. PCI clamping diodes clamp the signal to the VCCIO value and are required for 3.3-V PCI compliance. Clamping diodes can also be used to limit overshoot in other systems. Clamping diodes are controlled on a pin-by-pin basis. When VCCIO is

3.3 V, a pin that has the clamping diode option turned on can be driven by

that has the clamping diode option turned on can be driven by a 2.5-V signal, but not a 3.3-V or 5.0-V signal. Additionally, a clamping diode can be activated for a subset of pins, which would allow a device to bridge between a 3.3-V PCI bus and a 5.0-V device. Slew-Rate Control The output buffer in each IOE has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A slower slew rate reduces system noise and adds a maximum delay of 4.3 ns. The fast slew rate should be used for speed-critical outputs in systems that are adequately protected against noise. Designers can specify the slew rate pin-by-pin or assign a default slew rate to all pins on a device-wide basis. The slow slew rate setting affects the falling edge of the output. Open-Drain Output Option FLEX 10KE devices provide an optional open-drain output (electrically equivalent to open-collector output) for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired-OR plane. MultiVolt I/O Interface The FLEX 10KE device architecture supports the MultiVolt I/O interface feature, which allows FLEX 10KE devices in all packages to interface with systems of differing supply voltages. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO).

The VCCINT pins must always be connected to a 2.5-V power supply. than 3.0 V achieve a faster timing delay of tOD2 instead of tOD1. Table 14 summarizes FLEX 10KE MultiVolt I/O support. FLEX 10KE devices operate as specified by the user. Table 14. FLEX 10KE MultiVolt I/O Support

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performed before or after configuration, but not during configuration. FLEX 10KE devices support the JTAG instructions shown in Table 15. Table 15. FLEX 10KE JTAG Instructions test pattern at the output pins and capturing test results at the input pins. TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. to be serially shifted out of TDO. Jam Byte-Code File (.jbc) via an embedded processor. Table 16. FLEX 10KE Boundary-Scan Register Length

(1) The most significant bit (MSB) is on the left. (2) The least significant bit (LSB) for all JTAG IDCODEs is 1. FLEX 10KE devices include weak pull-up resistors on the JTAG pins. Table 17. 32-Bit IDCODE for FLEX 10KE Devices Note (1)

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Figure 20 shows the timing requirements for the JTAG signals. Figure 20. FLEX 10KE JTAG Waveforms Table 18 shows the timing parameters and values for FLEX 10KE devices. Table 18. FLEX 10KE JTAG Timing Parameters & Values

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Table 20. 2.5-V EPF10K50E & EPF10K200E Device Recommended Operating Conditions Table 21. 2.5-V EPF10K30E, EPF10K50S, EPF10K100E, EPF10K130E & EPF10K200S Device

Table 22. FLEX 10KE 2.5-V Device DC Operating Conditions Notes (6), (7)

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(1) See the Operating Requirements for Altera Devices Data Sheet. less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. CC rise time is 100 ms, and V CC must rise monotonically. (6) Typical values are for T A = 25° C, VCCINT = 2.5 V, and V CCIO = 2.5 V or 3.3 V. (7) These values are specified under the FLEX 10KE Recommended Operating Conditions shown in Tables 20 and 21. (9) The I OH parameter refers to high-level TTL, PCI, or CMOS output current. (11) This value is specified for normal device operation. The value may vary during power-up. (14) Capacitance is sample-tested only. Table 23. FLEX 10KE Device Capacitance Note (14)

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Figure 23. Output Drive Characteristics of FLEX 10KE Devices Note (1) (1) These are transient (AC) currents. LEs between the source and destination LEs.

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Figure 25. FLEX 10KE Device LE Timing Model

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Figure 28. Synchronous Bidirectional Pin External Timing Model parameters and their symbols. Table 24. LE Timing Microparameters (Part 1 of 2) Note (1)

Table 24. LE Timing Microparameters (Part 2 of 2) Note (1) Table 25. IOE Timing Microparameters Note (1)

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Table 26. EAB Timing Microparameters Note (1)

Table 27. EAB Timing Macroparameters Note (1), (6)

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Table 28. Interconnect Timing Microparameters Note (1) Table 29. External Timing Parameters

(2) Operating conditions: VCCIO = 3.3 V ±10 % for commercial or industrial use. EPF10K100E, EPF10K130E, and EPF10K200S devices. (4) Operating conditions: VCCIO = 3.3 V. (5) Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered. these parameters are calculated by summing selected microparameters. analysis are required to determine actual worst-case performance. (8) Contact Altera Applications for test circuit specifications and test conditions. (9) This timing parameter is sample-tested only. Bus Specification, revision 2.2. Table 30. External Bidirectional Timing Parameters Note (9)

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Figure 29. EAB Asynchronous Timing Waveforms

Figure 30. EAB Synchronous Timing Waveforms Table 31. EPF10K30E Device LE Timing Microparameters (Part 1 of 2) Note (1)

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Table 32. EPF10K30E Device IOE Timing Microparameters Note (1) Table 31. EPF10K30E Device LE Timing Microparameters (Part 2 of 2) Note (1)

Table 33. EPF10K30E Device EAB Internal Microparameters Note (1)

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Table 34. EPF10K30E Device EAB Internal Timing Macroparameters Note (1)

Table 35. EPF10K30E Device Interconnect Timing Microparameters Note (1) Table 36. EPF10K30E External Timing Parameters Notes (1), (2)

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(1) All timing parameters are described in Tables 24 through 30 in this data sheet. (2) These parameters are specified by characterization. (3) This parameter is measured without the use of the ClockLock or ClockBoost circuits. (4) This parameter is measured with the use of the ClockLock or ClockBoost circuits. Table 37. EPF10K30E External Bidirectional Timing Parameters Notes (1), (2) Table 38. EPF10K50E Device LE Timing Microparameters (Part 1 of 2) Note (1)

Table 39. EPF10K50E Device IOE Timing Microparameters Note (1) Table 38. EPF10K50E Device LE Timing Microparameters (Part 2 of 2) Note (1)

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Table 40. EPF10K50E Device EAB Internal Microparameters Note (1)

Table 41. EPF10K50E Device EAB Internal Timing Macroparameters Note (1) Table 42. EPF10K50E Device Interconnect Timing Microparameters Note (1)

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(1) All timing parameters are described in Tables 24 through 30 in this data sheet. (2) These parameters are specified by characterization. Table 43. EPF10K50E External Timing Parameters Notes (1), (2) Table 44. EPF10K50E External Bidirectional Timing Parameters Notes (1), (2) Table 45. EPF10K100E Device LE Timing Microparameters Note (1)

Table 46. EPF10K100E Device IOE Timing Microparameters Note (1)

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Table 47. EPF10K100E Device EAB Internal Microparameters Note (1) Table 48. EPF10K100E Device EAB Internal Timing Macroparameters (Part 1 of 2) Note (1)

Table 49. EPF10K100E Device Interconnect Timing Microparameters Note (1) Table 48. EPF10K100E Device EAB Internal Timing Macroparameters (Part 2 of 2) Note (1)

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(1) All timing parameters are described in Tables 24 through 30 in this data sheet. (2) These parameters are specified by characterization. (3) This parameter is measured without the use of the ClockLock or ClockBoost circuits. (4) This parameter is measured with the use of the ClockLock or ClockBoost circuits. Table 50. EPF10K100E External Timing Parameters Notes (1), (2) Table 51. EPF10K100E External Bidirectional Timing Parameters Notes (1), (2)

Table 52. EPF10K130E Device LE Timing Microparameters Note (1) Table 53. EPF10K130E Device IOE Timing Microparameters Note (1)

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Table 54. EPF10K130E Device EAB Internal Microparameters (Part 1 of 2) Note (1)

Table 55. EPF10K130E Device EAB Internal Timing Macroparameters Note (1) Table 54. EPF10K130E Device EAB Internal Microparameters (Part 2 of 2) Note (1)

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Table 56. EPF10K130E Device Interconnect Timing Microparameters Note (1) Table 57. EPF10K130E External Timing Parameters Notes (1), (2)

(1) All timing parameters are described in Tables 24 through 30 in this data sheet. (2) These parameters are specified by characterization. (3) This parameter is measured without the use of the ClockLock or ClockBoost circuits. (4) This parameter is measured with the use of the ClockLock or ClockBoost circuits. Table 58. EPF10K130E External Bidirectional Timing Parameters Notes (1), (2) Table 59. EPF10K200E Device LE Timing Microparameters (Part 1 of 2) Note (1)

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Table 60. EPF10K200E Device IOE Timing Microparameters Note (1) Table 59. EPF10K200E Device LE Timing Microparameters (Part 2 of 2) Note (1)

Table 61. EPF10K200E Device EAB Internal Microparameters Note (1) Table 62. EPF10K200E Device EAB Internal Timing Macroparameters (Part 1 of 2) Note (1)

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Table 63. EPF10K200E Device Interconnect Timing Microparameters Note (1) Table 62. EPF10K200E Device EAB Internal Timing Macroparameters (Part 2 of 2) Note (1)

(1) All timing parameters are described in Tables 24 through 30 in this data sheet. (2) These parameters are specified by characterization. Table 64. EPF10K200E External Timing Parameters Notes (1), (2) Table 65. EPF10K200E External Bidirectional Timing Parameters Notes (1), (2) Table 66. EPF10K50S Device LE Timing Microparameters (Part 1 of 2) Note (1)

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Table 67. EPF10K50S Device IOE Timing Microparameters Note (1) Table 66. EPF10K50S Device LE Timing Microparameters (Part 2 of 2) Note (1)

Table 68. EPF10K50S Device EAB Internal Microparameters Note (1)

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Table 69. EPF10K50S Device EAB Internal Timing Macroparameters Note (1) Table 70. EPF10K50S Device Interconnect Timing Microparameters Note (1)

(1) All timing parameters are described in Tables 24 through 30. (2) This parameter is measured without use of the ClockLock or ClockBoost circuits. Table 71. EPF10K50S External Timing Parameters Note (1) Table 72. EPF10K50S External Bidirectional Timing Parameters Note (1)

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Table 73. EPF10K200S Device Internal & External Timing Parameters Note (1) Table 74. EPF10K200S Device IOE Timing Microparameters (Part 1 of 2) Note (1)

Table 75. EPF10K200S Device EAB Internal Microparameters Note (1) Table 74. EPF10K200S Device IOE Timing Microparameters (Part 2 of 2) Note (1)

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Table 76. EPF10K200S Device EAB Internal Timing Macroparameters Note (1) Table 77. EPF10K200S Device Interconnect Timing Microparameters (Part 1 of 2) Note (1)

(1) All timing parameters are described in Tables 24 through 30 in this data sheet. (2) This parameter is measured without the use of the ClockLock or ClockBoost circuits. (3) This parameter is measured with the use of the ClockLock or ClockBoost circuits. Table 78. EPF10K200S External Timing Parameters Note (1) Table 79. EPF10K200S External Bidirectional Timing Parameters Note (1) Table 77. EPF10K200S Device Interconnect Timing Microparameters (Part 2 of 2) Note (1)

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ignored when calculating supply current. Table 80 provides the constant (K) values for FLEX 10KE devices. and the environmental operating conditions. Table 80. FLEX 10KE K Constant Values

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Figure 31. FLEX 10KE ICCACTIVE vs. Operating Frequency (Part 2 of 2) require configuration data to be loaded every time the circuit powers up. for configuration. The FLEX 10KE POR time does not exceed 50 µs. configuration device data sheet for POR timing information.

FLEX 10KE Embedded Programmable Logic Devices Data Sheet During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. Together, the configuration and initialization processes are called command mode; normal device operation is called user mode. SRAM configuration elements allow FLEX 10KE devices to be reconfigured in-circuit by loading new configuration data into the device. Real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different configuration data, reinitializing the device, and resuming user-mode operation. The entire reconfiguration process requires less than 85 ms and can be used to reconfigure an entire system dynamically. In-field upgrades can be performed by distributing new configuration files. Before and during configuration, all I/O pins (except dedicated inputs, clock, or configuration pins) are pulled high by a weak pull-up resistor. Programming Files Despite being function- and pin-compatible, FLEX 10KE devices are not programming- or configuration file-compatible with FLEX 10K or FLEX 10KA devices. A design therefore must be recompiled before it is transferred from a FLEX 10K or FLEX 10KA device to an equivalent FLEX 10KE device. This recompilation should be performed both to create a new programming or configuration file and to check design timing in FLEX 10KE devices, which has different timing characteristics than FLEX 10K or FLEX 10KA devices. FLEX 10KE devices are generally pin-compatible with equivalent FLEX 10KA devices. In some cases, FLEX 10KE devices have fewer I/O pins than the equivalent FLEX 10KA devices. Table 81 shows which FLEX 10KE devices have fewer I/O pins than equivalent FLEX 10KA devices. However, power, ground, JTAG, and configuration pins are the same on FLEX 10KA and FLEX 10KE devices, enabling migration from a FLEX 10KA design to a FLEX 10KE design.

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future device migration by preventing the use of conflicting I/O pins. configured in the same serial chain. Table 81. I/O Counts for FLEX 10KA & FLEX 10KE Devices Table 82. Data Sources for FLEX 10KE Configuration

FLEX 10KE Embedded Programmable Logic Devices Data Sheet Device Pin-Outs See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. Revision History The information contained in the FLEX 10KE Embedded Programmable Logic Data Sheet version 2.5 supersedes information published in previous versions. Version 2.5 The following changes were made to the FLEX 10KE Embedded Programmable Logic Data Sheet version 2.5: ■ Note (1) added to Figure 23. ■ Text added to “I/O Element” section on page 34. ■ Updated Table 22. Version 2.4 The following changes were made to the FLEX 10KE Embedded Programmable Logic Data Sheet version 2.4: updated text on page 34 and page 63.

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San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Alte ra Corporation in the U.S. and other countries. All other product or service names are the property of the ir respective holders. Altera products are protected under numerous U.S. and foreign patents and pendin g applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services FLEX 10KE Embedded Programmable Logic Devices Data Sheet

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