DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 26

Technical content

Features

Configuration devices for SRAM-based LUT devices offer the following features: ■ Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices ■ Easy-to-use four-pin interface ■ Low current during configuration and near-zero standby mode current ■ Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers ■ A vailable in compact plastic packages ■ 8-pin plastic dual in-line (PDIP) package ■ 20-pin plastic J-lead chip carrier (PLCC) package ■ 32-pin plastic thin quad flat pack (TQFP) package ■ EPC2 device has reprogrammable flash configuration memory Table 1. Altera Configuration Devices

■ 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.

1149.1 JTAG interface

Enhanced Configuration (EPC) Devices Datasheet. Configuration (EPCS) Devices Datasheet. Stratix GX, Stratix II, and Stratix II GX devices. Table 2. Supported Configuration Devices (Part 1 of 4)

Table 2. Supported Configuration Devices (Part 2 of 4)

Table 2. Supported Configuration Devices (Part 3 of 4)

Device Configuration Page 7 Configuration Devices for SRAM-Based LUT DevicesJanuary 2012 Altera Corporation The EPC2 device’s OE and nCS pins have internal programmable pull-up resistors. If you use internal pull-up resistors, do not use external pull-up resistors on these pins. The internal pull-up resistors are set by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when you generate programming files. The configuration device’s OE and nCS pins control the tri-state buffer on its DATA output pin and enable the address counter and oscillator. When the OE pin is driven low, the configuration device resets the address counter and tri-states its DATA pin. The nCS pin controls the DATA output of the configuration device. If the nCS pin is held high after the OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. If the nCS pin is driven low after the OE reset pulse, the counter and DATA output pin are enabled. When OE is driven low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of the nCS pin. If the FPGA’s configuration data exceeds the capacity of a single EPC1 or EPC2 configuration device, you can cascade multiple EPC1 or EPC2 devices together. If multiple EPC1 or EPC2 devices are required, the nCASC and nCS pins provide handshaking between the configuration devices. 1 EPC1441 and EPC1064/EPC1064V devices cannot be cascaded. When configuring ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices with cascaded EPC1 or EPC2 devices, the position of the EPC1 or EPC2 device in the chain determines its mode of operation. The first configuration device in the chain is the master, while subsequent configuration devices are slaves. The nINIT_CONF pin of the EPC2 master device can be connected to the nCONFIG pin of the FPGAs, which allows the INIT_CONF JT AG instruction to begin FPGA configuration. The nCS pin of the master configuration device is connected to the CONF_DONE pin of the FPGAs, while its nCASC pin is connected to the nCS pin of the next slave configuration device in the chain. Additional EPC1 or EPC2 devices can be chained together by connecting the nCASC pin to the nCS pin of the next EPC1 or EPC2 slave device in the chain. The last device’s nCS input comes from the previous device, while its nCASC pin is left floating. All other configuration pins, DCLK, DATA, and OE, are connected to every device in the chain. f For more information about configuration interface connections, including pull-up resistor values, supply voltages, and MSEL pin setting, refer to the configuration chapter in the appropriate device handbook.

Power and Operation Page 9 Configuration Devices for SRAM-Based LUT DevicesJanuary 2012 Altera Corporation configuration bit was sent for the CONF_DONE pin to reach a high state. In this case, the configuration device pulls its OE pin low, which in turn drives the target device’s nSTATUS pin low. Configuration automatically restarts if the Auto-restart configuration on error option is turned on in the Quartus II software from the General tab of the Device & Pin Options dialog box or the MAX+PLUS II software’s Global Project Device Options dialog box (Assign menu). f For more information about FPGA configuration and configuration interface connections between configuration devices and Altera FPGAs, refer to the configuration chapter in the appropriate device handbook. Power and Operation This section describes power-on reset (POR) delay, error detection, and 3.3-V and 5.0-V operation of Altera configuration devices. Power-On Reset During initial power-up, a POR delay occurs to permit voltage levels to stabilize. When configuring an FPGA with one EPC1, EPC2, or EPC1441 device, the POR delay occurs inside the configuration device and the POR delay is a maximum of 200 ms. When configuring a FLEX 8000 device with one EPC1213, EPC1064, or EPC1064V device, the POR delay occurs inside the FLEX 8000 device and the POR delay is typically 100 ms, with a maximum of 200 ms. During POR, the configuration device drives its OE pin low. This low signal delays configuration because the OE pin is connected to the target FPGA’s nSTATUS pin. When the configuration device completes POR, it releases its open-drain OE pin, which is then pulled high by a pull-up resistor.

1 You should power up the FPGA before the configuration device exits POR to avoid

the master configuration device from entering slave mode. If the FPGA is not powered up before the configuration device exits POR, the CONF_DONE/nCS line is high because of the pull-up resistor. When the configuration device exits POR and releases OE, it sees nCS high, which signals the configuration device to enter slave mode. Therefore, configuration will not begin because the DATA output is tri-stated and DCLK is an input pin in slave mode. Error Detection Circuitry The EPC1, EPC2, and EPC1441 configuration devices have built-in error detection circuitry for configuring ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, or Stratix II GX devices. Built-in error detection circuitry uses the nCS pin of the configuration device, which monitors the CONF_DONE pin on the FPGA. If the nCS pin on the EPC1 or EPC2 master device is driven high before all configuration data is transferred, the EPC1 or EPC2 master device drives its OE signal low, which in turn drives the FPGA’s nSTATUS pin low, indicating a configuration error. Additionally, if the configuration device generates its data and detects that the CONF_DONE pin has not gone high, it recognizes

Page 10 Power and Operation Configuration Devices for SRAM-Based LUT Devices January 2012 Altera Corporation that the FPGA has not configured successfully. EPC1 and EPC2 devices wait for

16 DCLK cycles after the last configuration bit was sent for the CONF_DONE pin to reach a

high state. In this case, the configuration device pulls its OE pin low, which in turn drives the target device’s nSTATUS pin low. Configuration automatically restarts if the Auto-restart configuration on error option is turned on in the Quartus II software from the General tab of the Device & Pin Options dialog box or the MAX+PLUS II software’s Global Project Device Options dialog box (Assign menu). In addition, if the FPGA detects a cyclic redundancy check (CRC) error in the received data, it will flag the error by driving the nSTATUS signal low . This low signal on nSTATUS drives the OE pin of the configuration device low, which resets the configuration device. CRC checking is performed when configuring all Altera FPGAs. 3.3-V or 5.0-V Operation Power the EPC1, EPC2, and EPC 1441 configuration device at 3.3 V or 5.0 V . For each configuration device, an option must be set for the 3.3-V or 5.0-V operation. For EPC1 and EPC1441 configuration devices, 3.3-V or 5.0-V operation is controlled by a programming bit in the .pof. The Low-V oltage mode option in the Options tab of the Configuration Device Options dialog box in the Quartus II software or the Use Low-Voltage Configuration EPROM option in the Global Project Device Options dialog box (Assign menu) in the MAX+PLUS II software sets this parameter. For example, EPC1 devices are programmed automatically to operate in 3.3-V mode when configuring FLEX 10KA devices, which have a V CC voltage of 3.3 V . In this example, the EPC1 device’s VCC pin is connected to a 3.3-V power supply. For EPC2 devices, this option is set externally by the VCCSEL pin. In addition, the EPC2 device has an externally controlled option, set by the VPPSEL pin, to adjust the programming voltage to 5.0 V or 3.3 V . The functions of the VCCSEL and VPPSEL pins are described below. These pins are only available in the EPC2 devices. ■ VCCSEL pin—For EPC2 configuration devices, 5.0-V or 3.3-V operation is controlled by the VCCSEL option pin. The device functions in 5.0-V mode when VCCSEL is connected to GND and 3.3-V mode when VCCSEL is connected to VCC. ■ VPPSEL pin—The V PP programming power pin of the EPC2 device is normally tied to VCC. For EPC2 devices operating at 3.3 V , it is possible to improve ISP time by setting VPP to 5.0 V . For all other configuration devices, VPP must be tied to VCC. The VPPSEL pin of the EPC2 device must be set in accordance with the VPP pin of the EPC2 device. If the VPP pin is supplied by a 5.0-V power supply, VPPSEL must be connected to GND and if the VPP pin is supplied by a 3.3-V power supply, VPPSEL must be connected to VCC.

connected to VCC, while a low logic level means the pin should be connected to GND. connected to either 3.3 V or 5.0 V . Table 3. VCCSEL and VPPSEL Pin Functions on the EPC2 Device Table 4. EPC2 Device Input and Bidirectional Pin Voltage Tolerance

Page 12 Programming and Configuration File Support Configuration Devices for SRAM-Based LUT Devices January 2012 Altera Corporation Programming and Configuration File Support The Quartus II and MAX+PLUS II softwares provide programming support for Altera configuration devices. During compilation, the Quartus II and MAX+PLUS II softwares automatically generates a .pof, which is used to program the configuration devices. In a multi-device configuration, the software combines the programming files for multiple ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices into one or more configuration devices. The software allows you to select the appropriate configuration device to store the data for each FPGA. All Altera configuration devices are programmable using Altera programming hardware in conjunction with the Quartus II or MAX+PLUS II software. In addition, many third-party programmers offer programming hardware that supports Altera configuration devices. 1 An EPC2 device can be programmed with a .pof generated for an EPC1 or EPC1441 device. An EPC1 device can be programmed with a .pof generated for an EPC1441 device. EPC2 configuration devices can be programmed in-system through its industry-standard four-pin JTAG interface. ISP capability in the EPC2 devices provide ease in prototyping and FPGA functionality. When programming multiple EPC2 devices in a JTAG chain, the Quartus II and MAX+PLUS II softwares and other programming methods employ concurrent programming to simultaneously program multiple devices and reduce programming time. EPC2 devices can be programmed and erased up to 100 times. After programming an EPC2 device in-system, FPGA configuration is initiated by the INIT_CONF JTAG instruction of the EPC2 device. For more information, refer to Tabl e 6. f For more information about programming and configuration support, refer to the following documents: ■ Altera Programming Hardware Data Sheet ■ USB-Blaster Download Cable User Guide ■ MasterBlaster Serial/USB Communications Cable User Guide ■ ByteBlaster II Download Cable User Guide ■ ByteBlasterMV Download Cable User Guide ■ BitBlaster Serial Download Cable Data Sheet You can also program the configuration devices using the Quartus II or MAX+PLUS II software with the APU or the appropriate configuration device programming adapter.

Tabl e 5 lists the programming adapter to use with each configuration device.

  1. Choose the Quartus II Programmer (T ools menu).
  2. Load the appropriate .pof by clicking Add. The Device column displays the

device for the current programming file.

  1. Insert a blank configuration device into the programming adapter’s socket.
  2. Turn on the Program/Configure. You can also turn on V erify to verify the contents
  3. After successful programming, you can place the configuration device on the PCB

to configure the FPGA device.

  1. Open the MAX+PLUS II Programmer.
  2. Load the appropriate .pof using the Select Programming File dialog box (File

field displays the device for the current programming file.

  1. Insert a blank configuration device into the programming adapter’s socket.
  2. After successful programming, you can place the configuration device on the PCB

to configure the FPGA device. same name as the first, but with a “_1” extension (e.g., top_1.pof). Table 5. Programming Adapters

The EPC2 device provides JTAG BST circuitry that complies with the IEEE Std. Table 6. EPC2 Device JTAG Instructions pattern output at the device pins. device to adjacent devices during normal device operation. resistor after the JTAG state machine goes out of Run-Test/Idle state. also used by the MAX+PLUS II software, .jam files, and .jbc files. .jbc, or .svf file using an embedded processor.

Tabl e 9 lists the timing parameters when using EPC1 and EPC1441 devices at 3.3 V . Table 9. Timing Parameters when Using EPC1 and EPC1441 Devices at 3.3 V (1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay. Table 10. Timing Parameters when Using EPC1, EPC2, and EPC1441 Devices at 5.0 V (Part 1 of 2)

and EPC1441 devices when configuring the FLEX 8000 device. (1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay. Table 10. Timing Parameters when Using EPC1, EPC2, and EPC1441 Devices at 5.0 V (Part 2 of 2) Table 11. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1064, EPC1064V, EPC1213, and EPC1441

Table 12. Absolute Maximum Ratings (1) Table 13. Recommended Operating Conditions Table 14. DC Operating Conditions

Table 15. EPC1064, EPC1064V, and EPC1213 Devices ICC Supply Current Values Table 16. EPC2 Device Values Table 17. EPC1 Device I CC Supply Current Values Table 18. EPC1441 Device I CC Supply Current Values Table 19. Capacitance (7) (1) For more information, refer to the Operating Requirements for Altera Devices Datasheet. 100 mA and periods shorter than 20 ns under no-load conditions. (3) Numbers in parentheses are for industrial temperature range devices. (5) Certain EPC2 device pins are driven to 5.75 V when operated with a 3.3-V V CC. For more information, refer to Table 4 on page 11. (6) The I OH parameter refers to high-level TTL or CMOS output current and the IOL parameter refers to low-level TTL or CMOS output current. (7) Capacitance is sample tested only.

Configuration (EPC) Devices Datasheet. Configuration (EPCS) Devices Datasheet. Table 20. EPC1, EPC2, and EPC1441 Device Pin Functions During Configuration (Part 1 of 3) counter and present the next bit of data on the DATA pin. has not been transferred to the target device. EPC1441 device drive DCLK low. pin connects to the nSTATUS pin of the FPGA. information, refer to “Error Detection Circuitry” on page 9. nCS and OE pull-ups on configuration device option.

is high, the device initializes as a slave device in the chain. nCS and OE pull-ups on configuration device option. Cascade select output (active low). nINIT_CONF pins are left floating. that is always active in EPC2 devices. This pin is only available in EPC2 devices. This pin is only available in EPC2 devices. This pin is only available in EPC2 devices. This pin is only available in EPC2 devices. Table 20. EPC1, EPC2, and EPC1441 Device Pin Functions During Configuration (Part 2 of 3)

This pin is only available in EPC2 devices. GND if the device uses a 5.0-V power supply (VCC = 5.0 V). 3.3-V power supply (VCC = 3.3 V). This pin is only available in EPC2 devices. GND if VPP uses a 5.0-V power supply (VPP = 5.0 V). This pin is only available in EPC2 devices. EPC1441 devices, VPP must be tied to VCC. This pin is only available in EPC2 devices. VCC 7, 8 20 27 Power Power pin. (1) This package is available for EPC1 and EPC1441 devices only. (2) This package is available for EPC2 and EPC1441 devices only. Table 20. EPC1, EPC2, and EPC1441 Device Pin Functions During Configuration (Part 3 of 3)

Tabl e 22 lists the revision history for this document. Table 21. Configuration Device Ordering Codes Table 22. Document Revision History January 2012 3.0 Minor text edits. ■ Updated “Features” section. ■ Removed “Referenced Documents” section. ■ Updated Table 5–2 and Table 5–16. ■ Added “Referenced Documents” section. ■ Updated new document format. April 2007 2.2 Added document revision history. July 2004 2.0 Added Stratix II and Cyclone II device information throughout chapter. September 2003 1.0 Initial Release.

Page 26 Document Revision History Configuration Devices for SRAM-Based LUT Devices January 2012 Altera Corporation