EPC16 ALTERA | Alldatasheet
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December 2002, ver. 12.2 Data Sheet DS-EPROM-12.2 Features ■ Serial device family for configuring APEXTM II, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), MercuryTM, ACEX® 1K, and FLEX® (FLEX 6000, FLEX 10KE, and FLEX 10KA) devices ■ Easy-to-use 4-pin interface to APEX II, APEX 20K, Mercury, ACEX, and FLEX devices ■ Low current during configuration and near-zero standby current ■ 5.0-V and 3.3-V operation ■ Software design support with the Altera® Quartus® II and MAX+PLUS® II development systems for Windows-based PCs as well as Sun SPARCstation, and HP 9000 Series 700/800 ■ Programming support with Altera’s Master Programming Unit (MPU) and programming hardware from Data I/O, BP Microsystems, and other manufacturers ■ Available in compact plastic packages (see Figures 1 and 2) – 8-pin plastic dual in-line package (PDIP) – 20-pin plastic J-lead chip carrier (PLCC) package – 32-pin plastic thin quad flat pack (TQFP) package – 100-pin plastic thin quad flat pack (TQPF) package – 88-pin Ultra FineLine BGA TM package ■ EPC2 device has reprogrammable Flash configuration memory – 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface – Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 – ISP circuitry is compatible with IEEE Std. 1532 for EPC2 configuration device – Supports programming through Serial Vector Format Files (.svf), Jam TM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), and the MAX+PLUS II software via the MasterBlasterTM, ByteBlasterMVTM, or BitBlasterTM download cable – nINIT_CONF pin allows a JTAG instruction to initiate device configuration – Can be programmed with Programmer Object Files ( .pof) for EPC1 and EPC1441 devices – Available in 20-pin PLCC and 32-pin TQFP packages
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32,000,000 bits with compression feature in these devices. Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet. Figure 1. EPC1, EPC1441, EPC1213, EPC1064, & EPC1064V Package Pin-Out Diagrams Note (1) available in these devices because they do not have JTAG pins. a reserved pin and should not be connected.
Configuration Devices for SRAM-Based LUT Devices Data Sheet Figure 2. EPC2 Package Pin-Out Diagrams
Description
With SRAM-based devices, configuration data must be reloaded each time the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based APEX II, APEX 20K, Mercury, ACEX, and FLEX devices. Table 1 lists Altera configuration devices. Note to Table 1: (1) These devices are one-time programable. 32-Pin TQFP20-Pin PLCC 1234 20 19 111091 2 1 3 OE N.C. VCCSEL DCLK N.C. TMS TCK DATA TDO VCC VPP N.C. N.C. N.C. VPPSEL TDI nCASC nCS GND 303132 29 28 N.C. N.C. DCLK N.C. VCCSEL TDI N.C. nCS N.C. GND nINIT_CONF N.C. N.C. N.C. VPP N.C. N.C. TDO TCK DATA N.C. N.C. TMS VCC N.C. 9 16 8N.C. OE N.C. VPPSEL N.C. N.C. 10 11 12 13 14 15 27 26 nCASC nINIT_CONF Table 1. Configuration Devices
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Mercury, ACEX 1K, and FLEX device. Table 2. Configuration Devices Used for Each APEX II, APEX 20K, Mercury, ACEX & FLEX Device
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Figure 3 shows the configuration device block diagram. Figure 3. Configuration Device Block Diagram (1) Do not use EPC2 devices to configure FLEX 6000 devices. devices support data cascading. (3) The OE pin is a bidirectional open-drain pin.
Configuration Devices for SRAM-Based LUT Devices Data Sheet Device Configuration The control signals for configuration devices— nCS, OE, and DCLK— interface directly with APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device control signals. All APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX devices can be configured by a configuration device without requiring an external intelligent controller. The configuration device’s OE and nCS pins control the tri-state buffer on the DATA output pin, and enable the address counter (and the oscillator in EPC4, EPC 8, EPC16, EPC2, EPC1, and EPC1441 devices). When OE is driven low, the configuration device resets the address counter and tri- states its DATA pin. The nCS pin controls the output of the configuration device. If nCS is held high after the OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is driven low, the counter and DATA output pin are enabled. When OE is driven low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of nCS.
1 The EPC4, EPC8, EPC16, EPC2, EPC1, and EPC1441 devices
determine the operation mode and whether the APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, or FLEX 6000 protocols should be used when OE is driven high. When the configuration device has driven out all of its data and has driven nCASC low, the device tri-states the DATA pin to avoid contention with other configuration devices. The EPC2 device allows the user to initiate configuration of the PLD via an additional pin, nINIT_CONF, that can be tied to the nCONFIG pin of the PLD(s) to be configured. A JTAG instruction causes the EPC4, EPC8, EPC16, and EPC2 device to drive nINIT_CONF low, which in turn pulls nCONFIG low. The EPC4, EPC8, EPC16, and EPC2 device then drives nINIT_CONF high to start configuration. When the JTAG state machine exits this state, nINIT_CONF releases nCONFIG and configuration is initiated.
1 An EPC4, EPC8, EPC16, and EPC2 device can be programmed
with a POF generated for an EPC1 or EPC1441 device, however, an EPC2 device cannot configure FLEX 6000 or FLEX 8000 devices. An EPC1 device can be programmed using a POF generated for an EPC1441 device.
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Configuration Devices for SRAM-based LUT Devices Data Sheet APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration APEX 20K, Mercury, ACEX 1K, and FLEX devices can be configured with EPC4, EPC8, EPC16, EPC2, EPC1, or EPC1441 devices. FLEX 6000 devices can be configured with EPC1 or EPC1441 devices. APEX II devices can be configured with EPC2, EPC4, EPC8, and EPC16 devices. The EPC4, EPC8, EPC16, EPC2, EPC1, or EPC1441 device stores configuration data in its EPROM array and serially clocks data out with an internal oscillator. The OE, nCS, and DCLK pins supply the control signals for the address counter and the output tri-state buffer. The configuration device sends a serial bitstream of configuration data to its DATA pin, which is routed to the DATA0 or DATA input pin on the LUT-based PLD device. Figure 4 shows an LUT-based PLD configured with a single EPC2, EPC1, or EPC1441 device.
Figure 4. ACEX 1K, APEX 20K, APEX II, FLEX 10K, FLEX 6000, or Mercury Device Configured with an EPC2, (1) Do not use EPC2 devices to configure FLEX 6000 devices. device option when generating programming files. for APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX devices. (5) The nCEO pin is left unconnected. sequences, pull up nCONFIG to VCCINT. (7) This diagram is for APEX 20KE devices only. only be able to drive low or tri-state.
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Configuration Devices for SRAM-based LUT Devices Data Sheet Table 3 describes EPC2, EPC1, and EPC1441 pin functions during APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device configuration. For information on EPC4, EPC8, and EPC16 devices, refer to Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet. Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K PDIP (3) 20-Pin PLCC 32-Pin TQFP (4) DATA 1 2 31 Output Serial data output. The DATA pin is tri-stated before configuration when the nCS pin is high, and after the configuration device finishes sending its configuration data. This operation is independent of the device’s position in the cascade chain. DCLK 242I / O DCLK is a clock output when configuring with a single configuration device or when the configuration device is the first device in a configuration device chain. DCLK is a clock input for subsequent configuration devices in a configuration device chain. Rising edges on DCLK increment the internal address counter and present the next bit of data to the DATA pin. The counter is incremented only if the OE input is held high, the nCS input is held low, and all configuration data has not been transferred to the target device. When configuring with the first EPC2 or EPC1 device in a configuration device chain or with a single EPC1441 device, the DCLK pin drives low after configuration is complete or when OE is low. OE (5) 387O p e n - Drain I/O Output enable (active high) and reset (active low). A low logic level resets the address counter. A high logic level enables DATA and permits the address counter to count. If this pin is low (reset) during configuration, the internal oscillator becomes inactive and DCLK drives low. See “Error Detection Circuitry” on page 23. nCS (5) 4 9 10 Input Chip select input (active low). A low input allows DCLK to increment the address counter and enables DATA to drive out. If the EPC1 or EPC2 is reset with nCS low, the device initializes as the first device in a configuration chain. If the EPC1 or EPC2 device is reset with nCS high, the device initializes as the subsequent device in the chain.
Configuration Devices for SRAM-Based LUT Devices Data Sheet nCASC (6) 6 12 15 Output Cascade select output (active low). This output goes low when the address counter has reached its maximum value. In a chain of EPC1 or EPC2 devices, the nCASC pin of one device is connected to the nCS pin of the next device, which permits DCLK to clock data from the next EPC1 or EPC2 device in the chain. nINIT_CONF (5), (7) – 13 16 Open- Drain Output Allows the INIT_CONF JTAG instruction to initiate configuration. This pin is connected to the nCONFIG pin of the LUT device to initiate configuration from the EPC2 via a JTAG instruction. If multiple EPC2 devices are used to configure an ACEX, APEX, FLEX or Mercury device, only the first EPC2 has its nINIT_CONF pin tied to the device’s nCONFIG pin. TDI (7) – 11 13 Input JTAG data input pin. Connect this pin to V CC if the JTAG circuitry is not used. TDO (7) – 1 28 Output JTAG data output pin. Do not connect this pin if the JTAG circuitry is not used. TMS (7) – 19 25 Input JTAG mode select pin. Connect this pin to V CC if the JTAG circuitry is not used. TCK (7) – 3 32 Input JTAG clock pin. Connect this pin to ground if the JTAG circuitry is not used. VCCSEL (7) –53I n p u t M o d e s e l e c t f o r V CC supply. VCCSEL must be connected to ground if the device uses a 5.0-V power supply (i.e., VCC = 5.0 V). VCCSEL must be connected to VCC if the device uses a 3.3-V power supply (i.e., VCC =3 . 3V ) . VPPSEL (7) – 14 17 Input Mode select for VPP. VPPSEL must be connected to ground if VPP uses a 5.0-V power supply (i.e., VPP= 5.0 V). VPPSEL must be connected to VCC if VPP uses a 3.3-V power supply (i.e, VPP = 3.3 V). VPP (7) – 18 23 Power Programming power pin. For the EPC2 device, this pin is normally tied to VCC . If the EPC2 VCC is 3.3 V, VPP can be tied to 5.0 V to improve in-system programming times. For EPC1 and EPC1441 devices, VPP must be tied to VCC . PDIP (3) 20-Pin PLCC 32-Pin TQFP (4)
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Configuration Devices for SRAM-based LUT Devices Data Sheet Notes to Table 3: (1) Do not use EPC2 devices to configure FLEX 6000 devices. (2) Pin-out information for EPC8 and EPC16 configuration devices, please refer to each respective data sheet. (3) This package is available for EPC1 and EPC1441 devices only. (4) This package is available for EPC2 and EPC1441 devices only. (5) The OE, nCS, and nINIT_CONF pins on EPC2 devices have internal, user-configurable 1-k Ω pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. (6) The EPC1441 device does not support data cascading. EPC2 and EPC1 devices support data cascading. (7) This pin applies to the EPC2 device only. APEX II, APEX 20K, Merucry, ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration with Multiple EPC2 or EPC1 Configuration Devices When configuration data for APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX devices exceeds the capacity of a single EPC2 or EPC1 configuration device, multiple EPC2 or EPC1 devices can be cascaded together. If multiple EPC2 or EPC1 devices are required, the nCASC and nCS pins provide handshaking between the devices.
1 EPC8 and EPC16 configuration devices cannot be cascaded
together. The EPC1441 device does not support data cascading. VCC 7, 8 20 27 Power Power pin. GND 5 10 12 Ground Ground pin. A 0.2- µF decoupling capacitor must be placed between the VCC and GND pins. PDIP (3) 20-Pin PLCC 32-Pin TQFP (4)
Configuration Devices for SRAM-Based LUT Devices Data Sheet When configuring APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX 10K devices with cascaded EPC2 or EPC1 devices, the position of the EPC2 or EPC1 device in the chain determines its operation. Similarly, when configuring FLEX 6000 devices with cascaded EPC1 devices, the position of the EPC1 device in the chain determines its operation. When the first or master device in a configuration device chain is powered-up or reset and the nCS pin is driven low, the master device controls configuration. The master device supplies all clock pulses to one or more LUT-based PLDs and to any subsequent slave devices during configuration. The master EPC2 or EPC1 device also provides the first stream of data to the LUT-based PLD during multi-device configuration. After the master EPC2 or EPC1 device finishes sending configuration data, the master EPC2 or EPC1 device drives its nCASC pin low, which drives the nCS pin of the first slave EPC2 or EPC1 device low. This action causes the slave EPC2 or EPC1 device to send configuration data to the LUT-based PLDs. The master EPC2 or EPC1 device clocks all subsequent slave devices until configuration is complete. Once all configuration data is transferred and the nCS pin on the master EPC2 or EPC1 device is driven high by the LUT- based PLD’s CONF_DONE pin, the master EPC2 or EPC1 device clocks 16 additional cycles to initialize the LUT-based PLD(s). The master EPC2 or EPC1 device then goes into zero-power (idle) state. If nCS on the master EPC2 or EPC1 device is driven high before all configuration data is transferred, or if nCS is not driven high after all configuration data is transferred, the master EPC2 or EPC1 device drives the APEX 20K, Mercury, ACEX 1K, and FLEX device’s nSTATUS pin low, indicating a configuration error. Configuration automatically restarts if the project is compiled with the Auto-Restart Configuration on Frame Error option turned on in the MAX+PLUS II software’s Global Project Device Options dialog box (Assign menu). Figure 5 shows an APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device configured with two EPC2 or EPC1 devices. Additional EPC2 or EPC1 devices can be added by connecting nCASC to nCS of the subsequent slave EPC2 or EPC1 device in the chain and connecting DCLK, DATA, and OE in parallel.
1 A mixture of APEX 20K, Mercury, ACEX 1K, FLEX 10K, and
FLEX 6000 devices can be configured in the same chain. A mixture of FLEX 10K, FLEX 10KA, FLEX 10KE, and 5.0-V and 3.3-V FLEX 6000 devices can be configured in the same chain. See “Configuration Chain with Multiple Voltage Levels” on page 25.
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Figure 5. APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 Device Configured with Two EPC2 (1) Do not use EPC2 devices to configure FLEX 6000 devices. (2) The pull-up resistor should be connected to the same supply voltage as the configuration device. should not be used on these pins. resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files. (5) EPC4, EPC8, and EPC16 devices cannot be cascaded. CC either directly or through a 1-kΩ resistor. sequences, pull up nCONFIG to VCCINT. only be able to drive low or tri-state. (9) The nCEO pin is left unconnected.
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(1) Do not use EPC2 devices to configure FLEX 6000 devices. used with FLEX 6000 devices. All other connections are the same for FLEX 6000 devices. (4) EPC4, EPC8, and EPC16 devices cannot be cascaded. CC either directly or through a 1-kΩ resistor. sequences, pull up nCONFIG to VCCINT. (7) This diagram is for APEX 20KE devices only. only be able to drive low or tri-state. APEX 20K, FLEX 10K & FLEX 6000 Devices). Figure 7 shows the timing waveform for the configuration device scheme. Figure 7. Configuration Device Scheme Timing Waveform (1) The configuration devivce will drive DATA low after configuration.
parameters when using EPC2 devices at 3.3 V. parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data Sheet. voltage supply to stabilize. Subsequent reconfigurations do not incur this delay. Table 4. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC2
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parameters when using EPC1 and EPC1441 devices at 3.3 V. parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data Sheet. voltage supply to stabilize. Subsequent reconfigurations do not incur this delay. Table 5. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC1 &
parameters when using EPC2, EPC1, and EPC1441 devices at 5.0 V. (1) Do not use EPC16, EPC8, EPC4, or EPC2 devices to configure FLEX 6000 devices. parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data Sheet. voltage supply to stabilize. Subsequent reconfigurations do not incur this delay. configuration devices support this type of configuration. Table 6. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC2,
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configure any FLEX 8000 device. EPC1064V configuration device. Figure 8. FLEX 8000 Device Configured with an EPC1, EPC1441, EPC1213, (2) All pull-up resistors are 1 k Ω . EPC1213 configuration devices.
Figure 9. FLEX 8000 Multi-Device Configuration with Two EPC1 or EPC1213 Configuration Devices (1) The pull-resistor should be connected to the same supply voltage as the confiuration device. (2) All pull-up resistors are 1 k Ω .
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Configuration Devices for SRAM-based LUT Devices Data Sheet Table 7 describes the pin functions of all configuration devices during FLEX 8000 device configuration. Notes: to Table 7 (1) This package is available for EPC1, EPC1441, EPC1213, EPC1064, and EPC1064V devices only. (2) This package is available for EPC1441, EPC1064, and EPC1064V devices only. (3) The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC1 and EPC1213 devices support data cascading for FLEX 8000 devices. f For more information on FLEX 8000 device configuration, see the following documents: ■ Application Note 33 (Configuring FLEX 8000 Devices) ■ Application Note 38 (Configuring Multiple FLEX 8000 Devices) Table 7. Configuration Device Pin Functions During FLEX 8000 Device Configuration PDIP (1) 20-Pin PLCC 32-Pin TQFP (2) DATA 12 31 Output Serial data output. The DATA pin is tri-stated before configuration when the nCS pin is high and after the configuration device finishes sending its configuration data. This operation is independent of the device’s position in the cascade chain. DCLK 24 2 Input DCLK is a clock input when using EPC1, EPC1213, EPC1064, and EPC1064V configuration devices. Rising edges on DCLK increment the internal address counter and present the next bit of data to the DATA pin. The counter is incremented only if the OE input is held high, the nCS input is held low, and all configuration data has not been transferred to the target device. OE 38 7 Open- Drain I/O Output enable (active high) and reset (active low). A low logic level resets the address counter. A high logic level enables DATA and permits the address counter to count. nCS (3) 4 9 10 Input Chip-select input (active low). A low input allows DCLK to increment the address counter and enables DATA. nCASC6 12 15 Output Cascade-select output (active low). This output goes low when the address counter has reached its maximum value. The nCASC output is usually connected to the nCS input of the next device in a configuration chain, so the next DCLK clocks data out of the next device. VCC 7, 8 20 27 Power Power pin. GND 5 10 12 Ground Ground pin. A 0.2- µF decoupling capacitor must be placed between the VCC and GND pins.
Configuration Devices for SRAM-Based LUT Devices Data Sheet Power & Operation This section describes Power-On Reset (POR) delay, error detection, and 3.3-V and 5.0-V operation of Altera configuration devices. Power-On Reset During initial power-up, a POR delay occurs to permit voltage levels to stabilize. When configuring an APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device with an EPC4, EPC8, EPC16, EPC2, EPC1, or EPC1441 device, the POR delay occurs inside the configuration device, and the POR delay is a maximum of 200 ms. When configuring a FLEX 8000 device with an EPC1213, EPC1064, or EPC1064V device, the POR delay occurs inside the FLEX 8000 device, and the POR delay is typically 100 ms, with a maximum of 200 ms. Error Detection Circuitry The EPC4, EPC8, EPC16, EPC2, EPC1, and EPC1441 configuration devices have built-in error detection circuitry for configuring APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 devices only. Built-in error-detection circuitry uses the nCS pin of the configuration device, which monitors the CONF_DONE pin on the APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device. An error condition occurs if the CONF_DONE pin does not go high after all the configuration data has been sent, or if the CONF_DONE pin goes high before the configuration device has completed sending configuration data. When an error condition occurs, the configuration device drives its OE pin low, which drives the APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device’s nSTATUS pin low, indicating an error. After an error, configuration automatically restarts if the Auto-Restart Configuration on Frame Error option is turned on in the Global Project Device Options dialog box (Assign menu) in the MAX+PLUS II software. For APEX 20K, APEX II, and Mercury devices, the Quartus II software provides a similar option. In addition, if the APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device detects a cyclic redundancy code (CRC) error in the received data, it may also flag the error by driving nSTATUS low. This low signal on nSTATUS resets the configuration device, allowing reconfiguration. CRC checking is performed when configuring all APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 devices.
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VPPSEL pin, to adjust the programming voltage to 5.0 V or 3.3 V. The functions of the VCCSEL and VPPSEL pins are described below. device functions in 3.3-V mode when VCCSEL is connected to VCC. 3.3-V power supply, VPPSEL must be connected to VCC. Table 8. VCCSEL & VPPSEL Pin Functions on the EPC2
Configuration Devices for SRAM-Based LUT Devices Data Sheet For EPC1 and EPC1441 configuration devices, 3.3-V or 5.0-V operation is controlled by a programming bit in the POF. The programming bit value is determined by the core supply voltage of the targeted device during design compilation with the MAX+PLUS II software. For example, EPC1 devices are programmed automatically to operate in 3.3-V mode when configuring FLEX 10KA devices, which have a V CC voltage of 3.3 V. In this example, the EPC1 device’s VCC pin is connected to a 3.3-V power supply. Designers may choose to set the configuration device for low voltage when using the MultiVoltTM feature, which allows an ACEX, APEX, APEX II, FLEX, or Mercury device to bridge between systems operating with different voltages. When compiling for 3.3-V FLEX 6000 devices, set the configuration device for low-voltage operation. To set the EPC1 and EPC1441 configuration devices for low-voltage operation, turn on the Low-Voltage I/O option in the Global Project Device Options dialog box (Assign menu) in the MAX+PLUS II software. Configuration Chain with Multiple Voltage Levels An EPC2 or EPC1 device can configure a device chain with multiple voltage levels. All 3.3-V and 2.5-V ACEX, APEX, APEX II, FLEX, and Mercury devices can be driven by higher-voltage signals. When configuring a mixed-voltage device chain, the APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX devices’ VCCINT and VCCIO pins may be connected to 2.5 V, 3.3 V, or 5.0 V, depending upon the device. The configuration device may be powered at 3.3 V or 5.0 V. If an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V configuration device is powered at 3.3 V, the nSTATUS and CONF_DONE pull-up resistors must be connected to 3.3 V. If these configuration devices are powered at 5.0 V, the nSTATUS and CONF_DONE pull-up resistors must be connected to 3.3 V or 5.0 V.
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tolerances of all EPC2 pins at 5.0 V and 3.3 V are listed in Table 9. Table 9. EPC2 Input & Bidirectional Pin Voltage Tolerance
Configuration Devices for SRAM-Based LUT Devices Data Sheet Programming & Configuration File Support The Quartus II and MAX+PLUS II development systems provide programming support for Altera configuration devices. The Quartus II and MAX+PLUS II software automatically generates a POF to program each configuration device in a project. In a multi-device project, the software can combine the programming files for multiple ACEX, APEX, APEX II, FLEX, or Mercury devices into one or more configuration devices. The software allows you to select the appropriate configuration device to most efficiently store the data for each APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX device. Moreover, when compiling for ACEX 1K, FLEX 10KA, FLEX 10KE, or Mercury devices, the MAX+PLUS II software automatically defaults to generate the EPC1 or EPC1441 POF with the programming bit set for 3.3-V operation. All Altera configuration devices are programmable using Altera programming hardware in conjunction with the Quartus II or MAX+PLUS II software. In addition, many manufacturers offer programming hardware that supports other Altera configuration devices. EPC4, EPC8, EPC16, and EPC2 configuration devices can be programmed in-system through its industry-standard 4-pin JTAG interface. ISP capability in the EPC2, EPC4, EPC8, and EPC16 devices provides ease in prototyping and updating APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX device functionality. The EPC8 and EPC16 devices can be programmed in-system via test equipment using SVF Files, Jam STAPL Files (.jam), or Jam STAPL Byte-Code Files (.jbc), embedded processors using the Jam programming and test language, and the MAX+PLUS II or Quartus II software via the MasterBlaster or ByteBlasterMV download cables. When programming multiple EPC2 devices in a JTAG chain, the Quartus II and MAX+PLUS II software and other programming methods employ concurrent programming to simultaneously program multiple devices and reduce programming time. EPC2, EPC4, EPC8, and EPC16 devices can be programmed and erased up to 100 times. After programming an EPC2, EPC4, EPC8, or EPC16 device in-system, APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX device configuration can be initiated by including the EPC2 JTAG configuration instruction. See Table 10 on page 28. f For more information on programming and configuration support, see the following documents: ■ Altera Programming Hardware Data Sheet ■ Programming Hardware Manufacturers ■ MasterBlaster Serial/USB Communications Cable Data Sheet ■ ByteBlasterMV Parallel Port Download Cable Data Sheet ■ ByteBlaster Parallel Port Download Cable Data Sheet ■ BitBlaster Serial Download Cable Data Sheet
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The EPC2 provides JTAG BST circuitry that complies with the IEEE Std. device supports the JTAG instructions shown in Table 10. developed to allow concurrent ISP between multiple PLD vendors. Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet. Boundary-Scan Testing in Altera Devices). Figure 10 shows the timing requirements for the JTAG signals. Table 10. EPC2 JTAG Instructions normal device operation, and permits an initial data pattern output at the device pins. test pattern at the output pins and capturing results at the input pins. programmable user-defined pattern. Jam STAPL Files, and JBC Files.
Figure 10. EPC2 JTAG Waveforms capacitance for configuration devices. Table 11. JTAG Timing Parameters & Values
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Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet. Table 12. Absolute Maximum Ratings Note (1) Table 13. Recommended Operating Conditions Table 14. DC Operating Conditions
(1) See the Operating Requirements for Altera Devices Data Sheet . input currents less than 100 mA and periods shorter than 20 ns under no-load conditions. (3) Numbers in parentheses are for industrial-temperature-range devices. (5) Certain EPC2 pins may be driven to 5.75 V when operated with a 3.3-V V CC. See Table 9 on page 26. (7) Capacitance is sample-tested only. Table 15. EPC1213, EPC1064 & EPC1064V Device ICC Supply Current Values Table 16. EPC2 Device ICC Supply Current Values Table 17. EPC1 Device ICC Supply Current Values Table 18. EPC1441 Device ICC Supply Current Values Table 19. Capacitance Note (7)
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APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX devices. Table 20. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC2 Devices at 5.0-V Table 21. ACEX 1K, APEX 20K, APEX II, FLEX 10K & Mercury Device Configuration Parameters Using EPC2
Table 22. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 & Table 23. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 &
34 Altera Corporation
■ Corrected the APEX 20KE voltate in Table 2 to 1.8 V. ■ Updated notes to Figures 4, 5, and 6. ■ Added APEX 20KE device diagrams to Figures 4 and 6. Table 24. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1441, EPC1213, EPC1064 &
Configuration Devices for SRAM-Based LUT Devices Data Sheet Altera Corporation 35 Notes:
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