EP1810 ALTERA | Alldatasheet
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Table 1. Classic Device Features
Classic EPLD Family Data Sheet General The Altera Classic™ device family offers a solution to high-speed, low- sat power logic integration. Fabricated on advanced CMOS technology, Description Classic devices also have a Turbo-only version, which is described in this data sheet. Classic devices support 100% TTL emulation and can easily integrate multiple PAL- and GAL-type devices with densities ranging from 300 to 900 usable gates. The Classic family provides pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz. Classic devices are available in a wide range of packages, including CerDIP, PDIP, PLCC, PGA, and SOIC packages. EPROM-based Classic devices can reduce active power consumption without sacrificing performance. This reduced power consumption makes the Classic family well suited for a wide range of low-power applications. Classic devices are 100% generically tested and can be erased with ultra-violet (UV) light, allowing design changes to be implemented quickly. Classic devices use sum-of-products logic and a programmable register. The sum-of-products logic provides a programmable-AND/fixed-OR structure that can implement logic with up to eight product terms. The programmable register can be individually programmed for D, T, SR, or IK flipflop operation or can be bypassed for combinatorial operation. In addition, macrocell registers can be individually clocked either by a global clock or by any input or feedback path to the AND array. Altera’s proprietary programmable I/O architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. These features make it possible to implement a variety of logic functions simultaneously. Classic devices are supported by Altera‘s MAX+PLUS II development system, a single, integrated package that offers schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry; compilation and logic synthesis; simulation and timing analysis; and device programming, The MAX+PLUS II software provides EDIF 200 and 3.0.0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and workstation- based EDA tools. The MAX+PLUS II software runs on 486- and Pentium- based PCs, and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System /6000 workstations. These devices also contain on-board logic test circuitry to allow verification of function and AC specifications during standard production flow. . bal ww = ‘For more information, go to the MAX+PLUS Ti Progmmmabie Logic Development System & Software Data Sheet in this data book.
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implements either an output enable or a logic-array-generated clock. information on feedback select configurations, see Figure 3 on page 423. Figure 1. Classic Device Macrocell
Classic EPLD Family Data Sheet The eight product terms of the programmable-AND array feed the 8-input oR gate, which then feeds one input to an XOR gate. The other input to the XOR gate is connected to a programmable bit that allows the array output to be inverted. Altera’s MAX+PLUS II software uses the XOR gate to implement either active-high or active-low logic, or De Morgan's inversion to reduce the number of product terms needed to implement a function. Programmable Registers To implement registered functions, each macrocell register can be individually programmed for D, T, JK, or SR operation. If necessary, the register can be bypassed for combinatorial operation. During design compilation, the MAX+PLUS II software selects the most efficient register operation for each registered function to minimize the logic resources needed by the design. Registers have an individual asynchronous clear function that is controlled by a dedicated product term. These registers are cleared automatically during power-up. In addition, macrocell registers can be individually clocked by either a global clock or any input or feedback path to the AND array. Altera’s proprietary programmable I/O architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. These features make it possible to simultaneously implement a variety of logic functions. Output Enable/Clock Select Figure 2 shows the two operating modes (Modes 0 and 1) provided by the output enable/clock (OE/CLK) select. The O£/CLK select, which is controlled by a single programmable bit, can be individually configured for each macrocell. In Mode 0, the tri-state output buffer is controlled by a single product term. If the output enable is high, the output buffer is enabled. If the output enable is low, the output has a high-impedance value. In Mode 0, the macrocell flipflop is clocked by its global clock input signal. In Mode 1, the output enable buffer is always enabled, and the macrocell register can be triggered by an array clock signal generated by a product term. This mode allows registers to be individually clocked by any signal on the AND array. With both true and complement signals in the AND array, the register can be configured to trigger on a rising or falling edge. This product-term-controlled clock configuration also supports gated clock structures.
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level performance evaluation. Figure 4. Classic Timing Model
424 Altera Corporation
Classic EPLD Family Data Sheet Timing information can be derived from the timing model and parameters for a particular device. External timing parameters represent pin-to-pin timing delays, and can be calculated from the sum of internal parameters. Figure 5 shows the internal timing relationship for internal and external delay parameters. <@ a _ Formore information on device timing, refer to Application Note 78 (Understanding MAX 5000 & Classic Tinting) in this data book. Altera Corporation 425
Figure 5. Classic Switching Waveforms
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Classic device that supports the Turbo mode. elements before and after packaging ensures 100% programming yield. AC specifications during standard production flow. Figure 6. AC Test Conditions Progra mming Master Programming Unit (MPU), and the appropriate device adapter. contact between the adapter and the device.
Notes:
— Pipelined data rates of up to 125 MHz. Figure 7. EP610 Package Pin-Out Diagrams Package outlines not drawn to scale. Windows in ceramic packages only.
Figure 8. EP610 Block Diagram Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages. Figure 9. Icc vs. Frequency of EP610 Devices
2 Ta =25°C
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Figure 10 shows the typical output drive characteristics of EP610 devices. Figure 10. Output Drive Characteristics of EP610 Devices Drive characteristics may exceed shown curves.
3 Ta = 25°C
Classic EPLD Family Data Sheet Operating The following tables provide information on absolute maximum ratings, was recommended operating conditions, operating conditions, and Conditions capacitance for EP610 and EP6101 devices. EP610 & EP610! Device Absolute Maximum Ratings —_ Notes (7), (2) ee ae [Symbol] Perens [Coons [wn [wor [win | ox | Unt] [ec | Smo vonage With especto gourd, leur [DG cut curentporpin [| as fas | | [Tere [Storage temperate [Nobis | os | 190 | 6s | 60 | -o | [Tae [Ambient temperature _[Underbias | 05 [va a5) 10 | es | = | bias [Peste packages under bas | | was | | ws | = | EP610 & EP610! Device Recommended Operating Conditions —_ Note (2) a [vos |Supeiywotage —‘(tews) ——~S~=*da Ta sas @H)] a7 | sas | Vv [vi [rmputvotage | id | Yoo | 0 | Ves | [No oupatvotago sf es | 0 os | | [Forindustiaivse | 40 | a5 | 40 | as | = | [ta [inputrisotime oto) Tos | 500s [i [imputtatime vio) Eto) J 500 Ys | EP610 & EP610I Device DC Operating Conditions Note (4} [var | Riheverinputvonage SSCS 80g | V_| [ve [Lowsevelinputvotage | ——SS~dt 0] oe vd [Ha ievel OOS ouput votage —[lgv=—96MADC, Sows 7) | ser | | v_| Low-level output voltage [iq=4maDdc,note7) | Tots fv | "| VO pin leakage current of dedicated input | V| = Veg or ground Pepe fe | pins [ie [Tistteoupatesiags omen [Vo=Vocorgomd | 0 | | a |
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Classic EPLD Family Data Sheet EP610 & EP610! Device Capacitance Note (9) [cio 0 pin capactance Vour=0V,1=10wHz |__| ve | | 8 _| oF | [Geiss | o:k% pincapactance |Vu-ovit=tomne |__| #0 | | 10 _| oF | VweoVistomHz [Tao | Te | oF | EP610 Device I¢¢ Supply Current —_ Notes (2), (10) Parameter Speed Typ Grade lect Voc supply current V\\ = Voc oF ground, no load, nA (non-Turbo, standby) Notes {11}, (12) lcce | Vcc Supply current V, = Voc oF ground, no load, 10 (15) (non-Turbo, active) f= 1.0 MHz, Notes (11), 112) EP610! Device Ic Supply Current Note (70) lect Voc supply current V, = Voc oF ground, no load, 150 nA (non-Turbo, standby) Notes (11), (12) lcc2 | Voo supply current V\\ = Voc oF ground, no load, (non-Turbo, active) f= 1.0 MHz, Notes (11), (12) Iccs [Voc supply current V\\ = Voc oF ground, no load, (Turbo, active) {= 1.0 MHz, Note (12) Altera Corporation 433
Classic EPLD Family Data Sheet Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet in this data book. (2) Numbers in parentheses are for industrial-temperature-range devices. (3) Theminimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions. (4) These values are specified under the “fP610 & EP610I Device Recommended Operating Conditions” on page 432. (5) For EP610 devices, maximum Vc rise time is 50 ms. For EP6101 devices, Vc rise time is unlimited with monotonic rise. (6) For EP610-15 and EP610-20 devices: tp and tp = 40 ns. For EP610-15 and EP610-20 clocks: tg and tp = 20 ns. (7) The Igy; parameter refers to high-level TTL or CMOS output current; the Igy, parameter refers to low-level TTL. output current. (8) This parameter does not apply to EP610I devices. (9) The device capacitance is measured at 25° C and is sample-tested only. The clock-pin capacitance is for dedicated clock inputs only. For EP610-25, EP610-30, and EP610-35 devices: pin 13 has a maximum capacitance of 50 pF; Cyy, Cio, and Cer = 20 pe. (10) Typical values are for T, = 25° C and Voc = 5 V. (11) When the Turbo Bit option is not set (non-Turbo mode), EP610 devices enter standby mode if no logic transitions occur for 100 ns after the last transition. When the Turbo Bit option is not set, EP610I devices enter standby mode if no logic transitions occur for 75 ns after the last transition. (12) Measured with a device programmed as a 16-bit counter.
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Classic EPLD Family Data Sheet EP610-15 & EP610-20 Device AC Operating Conditions Notes (1), (2) [ena rinngraameee esis | ee Ma] [Symes] Parameter | Contin | win [wx] min | wa] vets) | i [tor _[inputtonon-egistered output cr=a5pF | ts | [20 [20 Ts | [teoz [VO inputtonon-registered ouput cr=a5pF || 7 || 22 [20 Ts | [trex [inputtooutputenablo i= aopr TT ts | [ao [20 Ts | line [Mnuttoouputdsatie _|o1=spR. nos | | 15 |} 0 | 20 | ww | [ean —[Aeyncvonous ouput deartineor-espr____| | 16 | [0 | 20 | ww _| [tax _[Maximumclockirequency |notos) saa] [east | oo | Miz | |tsu___[Globalcockinputsetptime | Tl TT 20 Ts | |tu___[Giobalciockinputhostime | Po Plo TT oT rs [ton __[Globalcockhightime | Po | Ul oh TUT oT os | |tcr___[Globalcocktowtime | Pl | Ul oh TUT oT os | [tcor__[Giobalcockto output delay | TP Te To Ts [tenr _[Globalcockminimumperiod | TP te | ie [oT os | [cr [Mex inna gobel cock requoney |e) _[esa| |ees| | 0 | wie | |tasu __[Arayclockinputsotuptime | Po | UT oh TT eo Ts | [tan [Arayclockinputholdtime | Po | UT oh TU oT os | [tacn [Array clockhigntime Pe Tl TU oT os [tace [Anayctockiowtime fw Tl TT os | [toon [Ouputdata holdtime atterctock cr=a5pr, nove) | 1 | [+ [| [4 Tas | [tacor [Arayclocktooutputdolay | ts | eo Tao Ts | [tour [Array clockminimumperiod | TT tv Te oT os | [tacur [Array clock internal maximum tequency [Nowe 6) [7a [ose [ [ome | [aerinvnnas i [| [Symbot] Parameter | Conctions | win] Wax | win] Max] Unit [tw [inputpad and butterdelay | Pa Ts | [io ___[WOinputpadandbuttordelay || Pc Tf eT os | [iso [togicaraydoay PT Tl os | [too [Ouputbuterandpaddelay cr=a5pr | TT 8 | ns | [tex [Outputbutferenabledelay cr=a5pr | | ns | [tz [Outputbutterdisabledelay ci=spF | | | ns | [isu __[Registerseuptime PC TT Ts | [i [Registerhotdtime Pe Ts | [ic [Anayctockdotay PT TT os | [tics __[Globalciockdoly | Te os | [to | Feedbackdelay PT os | [tun __[Registorcleartime | Tl Ys | Altera Corporation 435
Classic EPLD Family Data Sheet EP610-25, EP610-30 & EP610-35 AC Operating Conditions Notes (1), (2) [cor tigmanee [ees [eww [eons PEM] [Srmbot] Parameter Conations | win | ax] Win waxy win] mex] ie) | Unt] [teor _[Inputto non-registered output [cr=a5eF | [a | | ao | | a5 [30 | ns | [teo2 __[WOinputtononegistered ouput | || a7 | [se ff a7 [| ns | [trex _[Imputtoouputenadle | Tf es TT oT fa [a0 is | fre_[rrtvewwene fc | Let Let [Pd Note (4) [tan [Aayrcivorous oop cearine [or =a5eF | [| [| || 0 [ws | [tune [Maximum teuensy [Nowe fare | far] | a | | 0 [| [tsu___[Global clock inputsetuptime [21 | [ae | ev | [a0 rs | [tu [Global ciockinputtoidtime [fo | fof fof fo [as | [tou __[Globalciookhightime Tf to | Pv | Pe To | ns | [tr__[Globalciocktowtime ff tof PT fet To | ns | [tor __[Globalciock to outputdelay | | Ts | wz | foo is | [tewr [Global ciock minimum period [| Tas || ao | fs [oT ns | [torr __[Max. internal globalciock requency| oreo) | 40 | [sas{ [eas] [| o [ wre] [tasu [Array clockinputsotuptime [| 8 | fe Tf 8 TT a0 | os | [tax [Array clockinputholdtime | f 2 |e | Pe] To | ns | [tacn __[Arayctocktigh time fT to | PT fet To [ns | [tace [Arrayctockiowtime TP to TPT Pe To | ns | feor_[Prnceretimeteos Soom TT Tt ttt tt Note (7} [tacor [Array clocktooutputdolay ||P a | se | 7 [0s | [tac [Array clock minimumperiod [| fas | fo | fs To os | [tacwr _[Max.internal global ctock requency| oie) | 40 | [sas] [ass] | o | wnz|
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Classic EPLD Family Data Sheet Internal Timing Parameters EP610-25 EP610-30 ] woes | | Srmba Parameter | Concition | in | wax | win | wax | win | wax | unt | Input pad and bulfer delay eS [tio [VO input pad and butter delay a [ts [Registerseupime it SS |] eo [te [ray lok ly ee [tes | tbat ook delay SO Feedback dy De fe oe | Notes to tables: (1) These values are specified under the “EP610 & EP610! Device Recommended Operating Conditions” on page 432. (2) See Application Note 78 (Linderstanding MAX 5000 & Classic Timing) in this data book for information on internal timing parameters. (3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (5) The fyyax Values represent the highest frequency for pipelined data. (6) Measured with a device programmed as a 16-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking, Altera Corporation 437
Classic EPLD Family Data Sheet EP610 Device AC Operating Conditions —_ Notes {1}, (2) a Fsman[ —___Paamnter | onttne [win [wer [Jo | ot [ieor _|iputononvegiteedouput _———*(Si=aspr_[ [vo | a | me | [te VO mputtononregisteredoupat =| S| 10 | as | [tx |inputtooupitenabie i ts as | a (re Note (4) fan [Aeron oupatcearine ————fer-asar [| me [| oe | [tune [Maximum tequency ids) “asi | feu tbat cockinputseupine Sd sd [i [Gebel ockinputnolgtime =i Si Pt i a | [tea |Glbalcockrighime ——SCS*SCSSCSCSCSC~C Pid a [tr ___—[Globalciocktowtime TT Ts | [tor [Globalciocktooutputdetay | Ts Ts | ler | tba cockrnimumpenod |_| | 19 | 2s] we | leer | Maxim rioma global dock Fequoney [oie | 700) | 0 | wr | [isu |Avay cocking sotptime | | ts | |e | EN ee SN A [sau [Arey docktowtine SSS dP | = peeeees ee TT Noite {7) [iscor [Arey docktoouipadoay YS | | [sar [Atay dock minimum parid | | P10 | as | [ren [Max iternal aay doc requeney [rowers | soo | 0 [ww |
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Classic EPLD Family Data Sheet Internal Timing Parameters EP6101-10 | | [to | V0 input pad and butter delay ee ee [1c | lobt cok ely ee [iio [Feedback dly ee ee Notes to tables: (1) These values are specified under the “HP610 & EPS10I Device Recommended Operating Conditions” on page 452. Q) See Application Note 78 (Linderstanding MAX 5000 & Classic Timing }in this data book for more information on Classic timing parameters. (3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (5) The fyyqx values represent the highest frequency for pipelined data. (6) Measured with a device programmed as a 16-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking. Altera Corporation 439
Notes:
— Pipelined data rates of up to 125 MHz. Figure 11. EP910 Package Pin-Out Diagrams Package ouilines are not drawn to scale. Windows in ceramic packages only.
we integration (SSI) and medium-scale integration (MSI) logic functions. and 1 through 12, respectively. Figure 12. EP910 Block Diagram Numbers without parentheses are for DIP packages. Numbers in parentheses are for J-lead packages.
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Classic EPLD Family Data Sheet Operati ng The following tables provide information on absolute maximum ratings, sae recommended operating conditions, operating conditions, and Conditions capacitance for EP910 and EP910I devices. EP910 & EP910I Device Absolute Maximum Ratings —_ Note (1) [svmbot| Parameter |__ conditions| win | max | win | max [Unit Supply voltage [woesi2i@) | 20 | zo | 20 [ zo | v | [lr | OC opt curonporgin | as [as P| [Tere —|Siorgp tempore [Nobis | 5 | 150 | es | 50] -o | [Taye [Ambientonperate [Nowe sy | 05 | vas 10 [as [=o | Ty Junction temperature Ceramic packages, under °c bias Plastic packages, under 135 °C bias EP910 & EP910I Device Recommended Operating Conditions —_Noie (5) Po eo | | Sa] Per Coane [win | ox | win | or [Un [v[iourvonage | Sd oo | 0 oe | | [vo JOuutvonage | SS*d | Yoo | 0 Yoo |v | Ta | Operating temperature [Forcommercialuse | 0 | 70 | o | 7 [-c| [Forinustiiuse | ~0 [es [| [=| [im iain ses | | [t= [Input fall time [woe | toot | 500s | EP910 & EP910! Device DC Operating Conditions —_ Noes (8), (9) Symbol Parameter Conditions [min | max [unit] [ver _|Wariovernpatvomage dS 8 gga] [vi [Lowevetinputvotage [SSS or fo |v | [Hot iover OS oupuvotage [Iga =08mADC, Hoi (OI see _| Pv | [Wor [Lowievelouputvotage [lu =4mADG, Howl Yom] lice [Terstate ouput leakage curent___[Vo=Vogergrand | 10 | 10 | wa]
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Classic EPLD Family Data Sheet EP910 & EP910I Device Capacitance —_ Noles (8), (12) [symbol] Parameter |__ Conditions| win_| max | win | Max [ unit Viv = OV. t= 1.0 MHz ee Viv = OV, t= 1.0 MHz Le EP910 & EP9101 Device Ic Supply Current Notes (5), (8), (8) ee [Symbcr] Parameter | _Condions_—__| win | Typ | wax| win | Typ | wax] unit Ice: [Veo Supply current V) = Voc or ground, no load, 150 nA (non-Turbo, standby) Notes (13), (14) lco2 [Veo Supply current V, = Veo oF ground, no load, mA (non-Turbo, active) f= 1.0 MHz, Notes (13), (14) Ices [Veo Supply current V) = Voc oF ground, no load, 45 | 80 mA (Turbo, active) f= 1.0 Mz, Note (14) (100) Notes to tables: (1) See the Operating Requirements for Aliera Devices Data Sheet in this data book. (2) Voltage with respect to ground. (3) For EP910 devices, the minimum DC input is -0.3 V; for EP9101 devices, the minimum DC input is -0.5 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions. (4) Under bias. Extended temperature versions are also available. (5) Numbers in parentheses are for industrial-temperature-range devices. (6) Maximum V¢c rise time for EP910 devices = 50 ms; for EP9101 devices, maximum V¢c rise time is unlimited with monotonic rise. (7) Forall clocks: tp and tp = 100 ns (50 ns for the industrial-temperature-range version). (8) These values are specified under the “fP910 & EPSi0 Device Recommended Operating Conditions” on page 444. (9) Typical values are T, = 25° C and Vec =5 V. (10) The Ip} parameter refers to high-level TTL or CMOS output current; the Ip, parameter refers to low-level TTL, output current. (11) This parameter does not apply to EP9101 devices. (12) For EP910 devices: capacitance measured at 25°C; sample-tested devices only; clock-pin capacitance for dedicated clock inputs only; pin 21 (high-voltage pin during programming) has a maximum capacitance of 60 pF. Values for EP910I devices are evaluated during initial characterization and design modifications. (13) When the Turbo Bit option is not set (non-Turbo mode), an EP910 device will enter standby mode if no logic transitions occur for 100 ns after the last transition, and an EP910I device will enter standby mode if no logic transitions occur for 75 ns after the last transition. (14) Measured with a device programmed as a 24-bit counter. Altera Corporation 445
Classic EPLD Family Data Sheet EP910 Device AC Operating Conditions Notes (1), (2) [erating Pramews | ear | eoras | mow [| | [Symbol] Parameter Conctons | win | Max] Win [wax] Win] Max] rove | unt [tor _[Inputtonon-registered output [cr=aspF [| so | [a5 | | 4 | 30 ns | [teo2 [VO inputtononvedistered ouput _[cr=sspF | | 33 | | ae [| 43 | 30 as | [trex _[Inputto ourputenabie fcr=a5pF [| ao | [as | [4 | 30 as | fre [irteowies feo | TT Ly Let Le Note (4) [ean |vnsivonons oopatcearime —[ot-o5pF | [| [= | |e] [m=] [twax [Maximum trequency Notes) [an [ [a7 | foes[ [owe | [tsu___[Globalciockinputsetuptime | [2a | [a7 | fv [30 os | [t __[Globalctockinputhoidtime | fo | fo | fo fT fo} [as | [tou __[Globalciockhigh ime | Pe |e TPs] To os | [tx___[Globalciocktowtime | Pe |e | fs | To os | [tcor [Global ciockto ouputdelay fci=a5pr [| ie | [aif [a [oT ns | [ter [Global clock minimum clockperiod [oie | | 30 | [as | [ao | oT os | Maximum internal global clock Note (6) 33.3 frequency [tasu [Array cock inputsetptime || wo | fo | fof 30 os | [tan [Array cook inputhowdime | Fs | fs | fs | To as | [tacn [Array ctockhightime | Pts |e | Pz To [os | [tac [Array ctockiowtime | ts |e | Pz] To [os | feor_[Prmrseretinewmrers Pees TT TT Tt Te] Note (7) [tacor [Array clock to outputdelay _—fci=aspF [| a3 [| ae [| a3 | 30 ns | [tac [Array clock minimum clockperiod | | [| go [| a5 | [ao [oT os | [tac _[Max. internal array clock trequency [oie (s) [saa] [ese] [as [| o [Mke|
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Classic EPLD Family Data Sheet Internal Timing Parameters EP910-30 EP910-35 EP910-40 | | [Symbol | __ Parameter Conction | win | wax | win | wax] win | wax [unt] Input pad and buffer delay Po TP to TT 9 Ps | YOinputpadandbutierdolay [| TT 8 TT oT [os | Logic array delay Po Pe Pe Ts | Output bulfer disable delay [or-ser TT TT 8 TT 10 [os | [isu | Registersetuptime | te | Tt | ns | Rgister hold time On Array clock delay Po Tt TT 20 [os | Giobal clock delay Po ee fs | Feedback delay Po Po Pe [ios | [tun _[Registercteartime PE Tt | 20 | is | Notes to tables: (1) These values are specified under the “£2910 & EP910i Device Recommended Operating Conditions” on page 444, (2) See Application Note 78 (Linderstanding MAX 5000 & Classic Timing) for more information on Classic timing parameters. (3) Thenon-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (5) The fax Values represent the highest frequency for pipelined data. (6) Measured with a device programmed as a 24-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both global and array clocking. Altera Corporation 447
Classic EPLD Family Data Sheet EP910I Device AC Operating Conditions —_ Noes (1), (2) Non- seovmnme ——_[osfemsfome] | [Symbo| —__Pranetr [os win] a] in] waa [Ua [teor _Inputtononregistered output [Ct=a5pF | [2] [is | [a5 [40 | ns | [tro _|VOinputto non-registered output [ct=s5pF | [2 | [is | [as [40 | ns | [trex _Inputtooutputenabio [ct =5pk | [ts | [ie | [ee [40 | ns | a Note (4) [torn [Asynchronous output cleartime _—[ci=a5pF | [1s | [ie | [28 [ 40 | ns | [tax _[iobalclockmaximum frequency [Noto s) | es [roo | [ozs[ [0 | whe [teu [Giobalclockinputsewptime | Pe | PT [te TT 40 | ns | [tu [Globatciockinpurhortime Po | fof fot fo Ts | [ten [iobalclockhightime | dE TP oe TP to To | is | [tr [Siobalclockiowtime | TU oT to To | os | |tcor [Global clockto ouiputdelay | | CP oh [le [ff oo [as | [tewr | Stobal clock minimum clock period —[cr=s5pF | [3] [is [ [25 [40 | ns | [text [Maximum internal global clock trequency [Note @) [769] Joss] | ao | [0 | wbe| [tasu [Array ctockinputsetuptime | Po Tf eT Pe TT 40 | os | [tan [Array ctockinputhoidtime | Pe TP | Pe TT | ns | [tacu _[Anayctockhigntime To [fst fest [as | [tacn [Arrayctockiowtme | Po Ts] rest | ns | foo [Pwracnrevommatroes fecee t | Tt tit | [| lote (7) [tacor [Array ctocktoouputdelay [ct=a5pF | | ie] [we] [2] 40 | ns | [tact [Array ctock minimum cockpeiod |_| Ts | fs | [25 [40 | ns | [tact [Maximum internal array ciock frequency [Note @ [769] Joss] [ao | [| wne|
448 Altera Corporation
Classic EPLD Family Data Sheet Internal Timing Parameters EP9101-12 EP9i0l-15 | EP910I-25 | | Symbol Parameter Coneition | win | mex] win] wax | win] wax] unt | [tw [Input pad and buffer delay poe Pe Ts [to [VOinputpad andbutterdelay | | | of oT oT os | Logie array delay ee ee [ao ___[ Output butter and pad dolay [or-sspr_ [| | 2 Tf 3 TT 6 [os | Output butfer enable delay [or-s5pr_— TT oe TP oe TT 9 I os | Ouiput buller disable delay C1=5pF {of sf fet fT 37 ns | Register setup time Po Ps TT os | Register hold time po Pe Pa Ts Array clock delay Poe Pe Ps Ps Global clock delay Po Ps Ts Ts | Feedback delay Po a Ts Ts Register clear time Po ee TT 0 Ts | Notes to tables: (1) These values are specified under the “EP910 & EP9101 Device Recommended Operating Conditions” on page 444. 2) See Application Note 78 (Linderstanding MAX 5000 & Classic Timing) in this data book for information on internal timing parameters. (3) Thenon-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (5) The fyyqx values represent the highest frequency for pipelined data. (6) Measured with the device programmed as a 24-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both global and array clocking. Altera Corporation 449
Notes:
Figure 15. EP1810 Package Pin-Out Diagrams Package outlines not drawn to scale. See Taie 2 on page 459 of this data sheet for PGA package pin-out information. Windows in ceramic packages only.
Classic EPLD Family Data Sheet General Altera EP1810 devices offer large-scale integration (LSI) density, TTL- we equivalent speed, and low-power consumption. EP1810 devices have 48 Description macrocells, 16 dedicated input pins, and 48 I/O pins (see Figure 16). EP1810 devices are divided into four quadrants, each containing 12 macrocells. Of the 12 macrocells in each quadrant, 8 have quadrant feedback and are “local” macrocells (see “Feedback Select” on page 423 of this data sheet for more information). The remaining 4 macrocells in the quadrant are “global” macrocells. Both local and global macrocells can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of the feedbacks from the global macrocells. EP1810 devices also have four dedicated inputs (one in each quadrant) that can be used as quadrant clock inputs. If the dedicated input is used as a clock pin, the input feeds the clock input of all registers in that particular quadrant.
452 Altera Corporation
Figure 16. EP1810 Block Diagram Numbers without parentheses are for J-lead packages. Numbers with parentheses are for PGA packages.
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1 Local Macrocells
Figure 17. Ic vs. Frequency of EP1810 Devices Figure 18 shows the output drive characteristics of EP1810 devices. Figure 18. Output Drive Characteristics of EP1810 Devices Drive characteristics may exceed shown curves.
5 Ta =25°C 3 Ta =25°C
454 Altera Corporation
Classic EPLD Family Data Sheet Ope rati ng The following tables provide information on absolute maximum ratings, was recommended operating conditions, operating conditions, and Conditions capacitance for EP1810 devices. EP1810 Device Absolute Maximum Ratings —_ Notes (1), (2) Srobol]___Pamsor | _Corions [win [wax [oil Supply voltage With respect to ground, Note (3) DC input voltage With respect to ground, Note 3) [1 [sunoton temperature _[Underbias SSS Ss) | EP1810 Device Recommended Operating Conditions —_ Note (2) [Symbol] ___Paommor [condos [win [wax [un Supply voltage 475(45) | 5.25(6.5) [iz Jptisetine dein Sd | EP1810 Device DC Operating Conditions —_Noies (6), (7) [Sr] Pernow Cone [win War [Ua Vou [High-level TTL output voltage lou = —4 mA DC, Note (6) [24 | High-level CMOS output voltage _| lox, = 0.6 mA DG, Note (3) ee ee Low-level output voltage lo. =4 mA DG, Note (8) ee ee VO pin leakage current of dedicated | V, = Voc or ground HA input pins [loz __| Tri-state output leakage current _[ Vg = Voc or ground [| -0 =| to Altera Corporation 455
Classic EPLD Family Data Sheet EP1810 Device Capacitance —_ Note (9) Simba Pome __Conow ‘| wn | war [un EP1810 Device Igc Supply Current Notes (2), (6), (7) Parameter Conditions Speed Typ Grade lect Veo supply current Vi=Voc or ground, noload,|-20,-25] | 50 | 150 | uA | loos Voo Supply current (Turbo, active) [V\\=Voo or ground, no load |-20,-25| | 180 _| 225 (250) | ma | Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet in this data book. (2) Numbers in parentheses are for industrial-temperature-range devices. (3) The minimum DC inputis -0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions. (4) Maximum Vec rise time is 50 ms. (5) For EP1810 clocks: tr and ty = 100 ns (50 ns for industrial-temperature-range versions). (6) Typical values are for T, = 25°C and Vec = 5 V. (2) These values are specified under the “f:P 1810 Device Recommended Operating Conditions” on page 435. (8) The Ioyy parameter refers to high-level TTL or CMOS output current; the Ioy, parameter refers to low-level TTL output current. (9) Capacitance measured at 25° C. Sample-tested only. Clock-pin capacitance for dedicated clock inputs only. Pin 19 has a maximum capacitance of 160 pF. (10) Measured with a device programmed as four 12-bit counters.
456 Altera Corporation
Classic EPLD Family Data Sheet EP1810-20 & EP1810-25 AC Device Operating Conditions Note (1) scene rinng ramets | rez fence | MR | rm] ermaor | Coane [win |e] wae] -_[U [teor _[inputtonon-egistered output |ci=a5pr_ || eo | [as | as | ns | [tro [VO inputtonon-registered ouput [ci=a5pF || 22 || 28 | as ns | [teu [Globalcocksouptime | Pt Ta Ts ns | [tu ___[Giobalcocknoigtime TP TPO TT ns | [ton __[Globalcockhightime ff TP oT To ns | [tcx___[Gtobalcockiowtime [Pe | fof To ts | [tor [Global cockto output delay ci=a5pF | Ts | fe | os | [texr [Minimum global clockperiod fois) | To | as | os | [fewr [Maximum intemal frequency foots) | 80 | ao || oe |tasu __[Arayclocksetwptime | TTP to | Ts is | [tan [Arayclockhotime | TTP oT To | ns | [tacor [Array lock to outputdelay [ci=aspr || 20 | fas [25 | os | [toon [Output dataholdtime aterciock [Cr=aspr.voio | 1 | [1 [ [oo | ns | [tecrer [Array clock maximum ciockperiod _[rovee) | 20 | [as [oo | ns | i = Gl Da frequency [twax _[Maximumclock iroquency [Noto is) ees | [so [| [Mie] mera ring Peace | rez ras | MR | [mo] Prmsor [Coane [wn wo] win wae] he -_[U [tw __[imputpad and utterdelay | | PT | UT 7] os | [ic [WOinputpadandbutterdelay | | dT 2 | To | | Jiao [bovicaraydolay | Tl Te Ts ns | [too [Ouputbutterandpad delay [ci=aspr_ | fo | [6 [oI ns | [ix __[Outputbutterenabiedelay [ci=aspr_ | fe | of 6 {lo | ns | [iz __[Outputbutterdisabiedelay [ci=sprinow | [ie | [ef io | rs | [isu __[Registorsouptime [Pe | fof To os | [iv [Registorhodtime J TP oT To | lic [Anayclockdotay fT Te Ts | lies [Globalciockdoy | TT To [ns | [to [Foodbackdelay | TT Tes | [tun _[Registercteartime TE Cl Te Ts os | Altera Corporation 457
Classic EPLD Family Data Sheet EP1810-35 & EP1810-45 Device AC Operating Conditions Note (1) scene rinngrarmewrs | ers [eas | Re | [rm] ermaor | Coane [win own wae] _[U [teor _[inputtonon-egistered output |ci=a5pF || a5 | [as | a0 ns | [tro [VO inputtonon-registered output [ci=a5pF || ao || so | a0 ns | [teu [Globalcocksouptime | PTT co | To ns | [tu ___[Giobalcocknoigtime TP TPO TT ns | [ton __[Globalcockhightime | Pe Ts TT ons | [tcx__[Gobalciockiowtime [Pe Ts [To ns | [tor [Global cockto output delay i= a5pF | | 2 | as | os | [ext [Minus goal cock parade | Rote | a5 | | «6 | 0 | we | [fewr [Maximum intoral frequency [ois age | [ez2t | o [Me |tasu __[Arayclocksetwptime | to TP TT 0 ns | [tan [Arayclockhotime | tT | To ns | [tacor [Array clock to outputdelay [ci=a5er_ | as | [as [30s | [toon [Output dataholdtime aterciock [cr=aspr.voio) | 1 | [1 [ [| ns | [tecrr [Array clock maximum ciockperiod _[rovee) | [a5 | [as [0 | ns | fr [ico es fe ey frequency [twax _[Maximumclock irequency | Noios) | ao | [oasf To [Me mera ring Pears | rts [eas | Re | [Symper] Parameter | conations | win [ax] win| wax] sH(2) [unt] [tw __[imputpad and butterdelay | | dT 7] UT oh To [ns | [ic |[WOinputpadandbutterdelay | | | TT To | ns | [iso [bovicaraydolay | | | os Tc ns | [too [Ouputbutterandpad delay [ci=aspr || a | Pv To ns | [ix __[Outputbutterenabiedelay fci=aspr_ || @ | fv fo ns | [iz __[Outputbutterdisabiedelay [ct=sprinow | [ef [ufo | ns | [isu __[Registorseuptime [Po | fof To os | [iv [Registerholdtime J Tt TT on | [ic [Anayclockdoay fT Te Ts | [tics [Globalciockdoy | TT TU To ns | [to [Foodbackdelay | TE TT os | [tun _[Registorcteartime TT Tf 2 To os |
458 Altera Corporation
(2) Thenon-Turbo adder must be added to this parameter when the Turbo Bit option is off. (3) Measured with a device programmed as four 12-bit counters. applies for both global and array clocking. (5) The fy4x values represent the highest frequency for pipelined data. (6) Sample-tested only for an output change of 500 mV. Table 2. EP1810 PGA Pin-Outs