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Technical content

Features

  • Integrated Inductor Technology
  • 3mm x 3mm x 1.1mm QFN package
  • Total Solution Footprint ~ 21mm2
  • Low VOUT ripple for IO compatibility
  • High efficiency, up to 94%
  • 1000mA continuous output current
  • Less than 1µA standby current
  • 5 MHz switching frequency
  • 3 pin VID for glitch free voltage scaling
  • VOUT Range 0.6V to VIN – 0.5V
  • Short circuit and over current protection
  • UVLO and thermal protection
  • IC level reliability in a PowerSoC solution

Applications

  • Portable wireless and RF applications
  • Wireless broad band data cards
  • Solid state storage applications
  • Noise and space sensitive applications EP53A8xQI 4.7uF 10uF 6mm 3.5mm

100 Ohm

10µF 08054.7µF 0603 VOUT VOUT AGND ENABLE VFB PGND AVIN 100 ohm Figure 1. Total Solution Footprint Figure 2. Typical Application Circuit.

03651 September 17, 2013 Rev D

Ordering Information

Part Number Comment Package EP53A8LQI LOW VID Range 16-pin QFN T&R EP53A8HQI HIGH VID Range 16-pin QFN T&R EVB-EP53A8LQI E P53A8LQI Evaluation Board EVB-EP53A8HQI E P53A8HQI Evaluation Board Packing and Marking Information : www.altera.com/support/reliability/packing/rel-packing-and-marking.html Pin Assignments (Top View) Figure 1: EP53A8LQI Pin Out Diagram (Top View) F igure 4: EP53A8HQI Pin Out Diagram (Top View) Pin

Description

1, 15,

16 NC(SW)

NO CONNECT – These pins are internally connected to the common switching node of the internal MOSFETs. NC (SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage to the device. 2,3 PGND Power ground. Connect this pin to the ground electrode of the Input and output filter capacitors. 4 VFB EP53A8LQI: Feed back pin for external divider option. EP53A8HQI: No Connect 5 VSENSE Sense pin for preset output voltages. Refer to application section for proper configuration. 6 AGND Analog ground. This is the quiet ground for the internal control circuitry, and the ground return for external feedback voltage divider 7, 8 VOUT Regulated Output Voltage. Refer to application section for proper layout and decoupling. 9, 10, VS2, VS1, VS0 Output voltage select. VS2 = pin 9, VS1 = pin 10, VS0 = pin 11. EP53A8LQI: Selects one of seven preset output voltages or an external resistor divider. EP53A8HQI: Selects one of eight preset output voltages. (Refer to section on output voltage select for more details.) 12 ENABLE Output Enable. Enable = logic high; Disable = logic low 13 AVIN Input power supply for the controller circuitry. Connect to PVIN through a 100 Ohm resistor. 14 PVIN Input Voltage for the MOSFET switches. w ww.altera.com/enpirion, Page 2

CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER SYMBOL MIN M AX UNITS Input Supply Voltage VIN -0.3 6.0 V Voltages on: ENABLE, VSENSE, VSO – VS2 -0.3 VIN+ 0.3 V Voltages on: VFB (EP53A8LQI) -0.3 2.7 V Maximum Operating Junction Temperature TJ-ABS 150 °C Storage Temperature Range TSTG -65 150 °C Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020C 260 °C ESD Rating (based on Human Body Mode) 2000 V Recommended Operating Conditions PARAMETER SYMBOL MIN M AX UNITS Input Voltage Range VIN 2.4 5.5 V Operating Ambient Temperature TA - 40 +85 °C Operating Junction Temperature TJ - 40 +125 °C Thermal Characteristics PARAMETER SYMBOL TYP UNITS Thermal Resistance: Junction to Ambient –0 LFM (Note 1) θJA 80 °C/W Thermal Overload Trip Point TJ-TP +155 °C Thermal Overload Trip Point Hysteresis 25 °C Note 1: Based on a four layer copper board and proper thermal design per JEDEC EIJ/JESD51 standards. www.altera.com/enpirion, Page 3

Electrical Characteristics

NOTE: TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.6V. CIN = -4.7µF 0603 MLCC, COUT = 10µF 0805 MLCC. PARAMETER SYMBOL TEST CONDITIONS MIN TYP M AX UNITS Operating Input Voltage VIN 2.4 5.5 V Under Voltage Lock-out – VIN Rising VUVLO_R 2.0 V Under Voltage Lock-out – VIN Falling VUVLO_F 1.9 V Drop Out Resistance RDO Input to Output Resistance 350 500 mΩ Output Voltage Range VOUT EP53A8LQI (VDO = ILOAD X RDO) EP53A8HQI 0.6

1.8 VIN-VDO

3.3 V Dynamic Voltage Slew Rate VSLEW EP53A8HQI EP53A8LQI 8

4 V/mS

Accuracy ∆VOUT TA = 25°C, VIN = 3.6V; ILOAD = 100mA ; 0.8V ≤ VOUT ≤ 3.3V -2 +2 % Feedback Pin Voltage Initial Accuracy VFB TA = 25°C, VIN = 3.6V; ILOAD = 100mA ; 0.8V ≤ VOUT ≤ 3.3V .588 0.6 0.612 V Line Regulation ∆VOUT_LINE 2.4V ≤ VIN ≤ 5.5V 0.03 %/V Load Regulation ∆VOUT_LOAD 0A ≤ ILOAD ≤ 1000mA 0.6 %/A Temperature Variation ∆VOUT_TEMPL -40°C ≤ TA ≤ +85°C 30 ppm/°C Output Current IOUT 1000 mA Shut-down Current ISD Enable = Low 0.75 µA OCP Threshold ILIM 2.4V ≤ VIN ≤ 5.5V 0.6V ≤ VOUT ≤ 3.3V 1.25 1.4 A VS0-VS2, Pin Logic Low VVSLO 0.0 0.3 V VS0-VS2, Pin Logic High VVSHI 1.4 VIN V VS0-VS2, Pin Input Current IVSX Note 1 <100 nA Enable Pin Logic Low VENLO 0.3 V Enable Pin Logic High VENHI 1.4 V Enable Pin Current IENABLE Note 1 <100 nA Feedback Pin Input Current IFB Note 1 <100 nA Operating Frequency FOSC 5 MHz Soft Start Operation Soft Start Slew Rate ∆VSS EP53A8HQI (VID only) EP53A8LQI (VID only) 8 Soft Start Rise Time ∆TSS EP53A8LQI (VFB mode); Note 2 170 225 280 µS Note 1: Parameter guaranteed by design and characterization. Note 2: Measured from when VIN ≥ VUVLO_R & ENABLE pin crosses its logic High threshold. www.altera.com/enpirion, Page 4

Typical Performance Characteristics Efficiency vs. Load Current: VIN = 5.0V, V OUT Efficiency vs. Load Current: VIN = 3.3V, V OUT (from top to bottom) = 2.5, 1.8V,1.2V Start Up Waveform: VIN = 5.0V, V OUT = 3.3V; ILOAD = 1000mA Shut-down Waveform: VIN = 5.0V, V OUT = 3.3V; ILOAD = 1000mA Output Ripple: VIN = 5.0V, V OUT = 1.2V, Load = 1A Output Ripple: VIN = 5.0V, VOUT = 3.3V, Load = 1A 0 100 200 300 400 500 600 700 800 900 1000 Load Current (A) Efficiency (%) 0 100 200 300 400 500 600 700 800 900 1000 Load Current (A) Efficiency (%) www.altera.com/enpirion, Page 5

Typical Performance Characteristics (continued) Output Ripple: VIN = 3.3V, VOUT = 1.8V, Load = 1A Output Ripple: VIN = 3.3V, VOUT = 1.2V, Load = 1A Load Transient: V IN = 5.0V, V OUT = 3.3V Load stepped from 0mA to 1000mA Load Transient: V IN = 5.0V, V OUT = 1.2V Load stepped from 0mA to 1000mA Load Transient: V IN = 3.7V, V OUT = 1.2V Load stepped from 0mA to 1000mA Load Transient: V IN = 3.3V, V OUT = 1.8V Load stepped from 0mA to 1000mA 5mV/Div www.altera.com/enpirion, Page 6

(+) (-) Error Amp VSENSE VFB VOUT Package Boundry P-Drive N-Drive UVLO Thermal Limit Current Limit Soft Start Sawtooth Generator (+) (-) PWM Comp PVIN ENABLE PGND Logic Compensation Network NC(SW) Voltage Select VS0 VS1AVIN VS2AGND Figure 5: Functional Block Diagram www.altera.com/enpirion, Page 7

The EP53A8xQI requires only 2 small MLCC capacitors and an 0201MLC resistor for a complete DC -DC converter solution. The device integrates MOSFET switches, PWM controller, Gate-drive, compensation, and inductor into a tiny 3mm x 3mm x 1.1mm QFN package. Advanced package design, along with the high level of integration, provides very low output ripple and noise. The EP53A8xQI uses voltage mode control for high noise immunity and load matching to advanced ≤90nm loads. A 3-pin VID allows the user to choose from one of 8 output voltage settings. The EP53A8xQI comes with two VID output voltage ranges. The EP53A8HQI provides V OUT settings from 1.8V to 3.3V, the EP53A8LQI provides VID settings from 0.8V to 1.5V, and also has an external resistor divider option to program output setting over the 0.6V to V IN-0.5V range. The EP53A8xQI provides the industry’s highest power density of any 1A DCDC converter solution. The key enabler of this revolutionary integration is Altera’s proprietary power MOSFET technology. The advanced MOSFET switches are implemented in deep-submicron CMOS to supply very low switching loss at high switching frequencies and to allow a high level of integration. The semiconductor process allows seamless integration of all switching, control, and compensation circuitry. The proprietary magnetics design provides high-density/high-value magnetics in a very small footprint. Altera Enpirion magnetics are carefully matched to the control and compensation circuitry yielding an optimal solution with assured performance over the entire operating range. Protection features include under -voltage lock- out (UVLO), over -current protection (OCP), short circuit protection, and thermal overload protection. Integrated Inductor: Low -Noise Low-EMI The EP53A8xQI utilizes a proprietary low loss integrated inductor. The integration of the inductor greatly simplifies the power supply design process. The inherent shielding and compact construction of the integrated inductor reduces the conducted and radiated noise that can couple into the traces of the printed circuit board. Further, the package layout is optimized to reduce the electrical path length for the high di/dT input AC ripple currents that are a major source of radiated emissions from DC-DC converters. The integrated inductor provides the optimal solution to the complexity, output ripple, and noise that plague low power DCDC converter design. Voltage Mode Control, High Bandwidth The EP53A8xQI utilizes an integrated type III compensation network. Voltage mode control is inherently impedance matched to the sub 90nm process technology that is used in today’s advanced ICs. Voltage mode control also provides a high degree of noise immunity at light load currents so that low ripple and high accuracy are maintained over the entire load range. The very high switching frequency allows for a very wide control loop bandwidth and hence excellent transient performance. Soft Start Internal soft start circuits limit in-rush current when the device starts up from a power down condition or when the “ENABLE” pin is asserted “high”. Digital control circuitry limits the V OUT ramp rate to levels that are safe for the Power MOSFETS and the integrated inductor. The EP53A8HQI has a soft -start slew rate that is twice that of the EP53A8LQI. When the EP53A8LQI is configured in external resistor divider mode, the device has a fixed VOUT ramp time. Therefore, the ramp rate will vary with the output voltage setting. Output voltage ramp time is given in the Electrical Characteristics Table. Excess bulk capacitance on the output of the device can cause an over -current condition at startup. Assuming no-load at startup, the maximum total capacitance on the output, including the output filter capacitor and bulk www.altera.com/enpirion, Page 8

and decoupling capacitance, at the load, is given as: EP53A8LQI: COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 250uF EP53A8HQI: COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 125uF EP53A8LQI (in external divider mode): COUT_TOTAL_MAX = 2.25x10-4/VOUT Farads The nominal value for C OUT is 10uF. See the applications section for more details. Over Current/Short Circuit Protection The current limit function is achieved by sensing the current flowing through a sense P - MOSFET which is compared to a reference current. When this level is exceeded the P - FET is turned off and the N -FET is turned on, pulling V OUT low. This condition is maintained for approximately 0.5mS and then a normal soft start is initiated. If the over current condition still persists, this cycle will repeat. Under Voltage Lockout During initial power up, an under voltage lockout circuit will hold -off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. If the lockout circuitry will again disable the switching. Hysteresis is inclu ded to prevent chattering between states. Enable The ENABLE pin provides a means to shut down the converter or enable normal operation. A logic low will disable the converter and cause it to shut down. A logic high will enable the converter into normal operation. NOTE: The ENABLE pin must not be left floating. Thermal Shutdown When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature exceeds the thermal shutdown temperature, the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. When the junction temperature decreases by 25C°, the device will go through the normal startup process.

Application Information

10µF 08054.7µF 0603 VOUT VOUT AGND ENABLE PGND AVIN 100 ohm Figure 2: Application Circuit, EP53A8HQI. VIN VSENSE PVIN VS1 VS2 VS0 10µF 08054.7µF 0603 VOUT VOUT AGND ENABLE VFB PGND AVIN 100 ohm Figure 3: Application Circuit, EP53A8LQI showing the VFB function. www.altera.com/enpirion, Page 9

Output Voltage Programming The EP53A8xQI utilizes a 3-pin VID to program the output voltage value. The VID is available in two sets of output VID programming ranges. The VID pins should be connected either to an external control signal, AVIN or to AGND to avoid noise coupling into the device. The “Low” range is optimized for low voltage applications. It comes with preset VID settings ranging from 0.80V and 1.5V. This VID set also has an external divider option. To specify this VID range, order part number EP53A8LQI. The “High” VID set provides output voltage settings ranging from 1.8V to 3.3V. This version does not have an external divider option. To specify this VID range, order part number EP53A8HQI. Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. NOTE: The VID pins must not be left floating. Table 1: EP53A8LQI VID Voltage Select Settings EP53A8L Low VID Range Programming The EP53A8LQI is designed to provide a high degree of flexibility in powering applications that require low V OUT settings and dynamic voltage scaling (DVS). The device employs a 3-pin VID architecture that allows the user to choose one of seven (7) preset output voltage settings, or the user can select an external voltage divider option. The VID pin settings can be changed on the fly to implement glitch- free voltage scaling. Table 1 shows the VS2-VS0 pin logic states for the EP53A8LQI and the associated output voltage levels. A logic “1” indicates a connection to AVIN or to a “high” logic voltage level. A logic “0” indicates a connection to AGND or to a “low” logic voltage level. These pins can be either hardwired to AVIN or AGND or alternatively can be driven by standard logic levels. Logic levels are defined in the electrical characteristics table. Any level between the logic high and logic low is indeterminate. EP53A8LQI External Voltage Divider The external divider option is chosen by connecting VID pins VS2-VS0 to VIN or a logic “1” or “high”. The EP53A8LQI uses a separate feedback pin, V FB, when using the external divider. VSENSE must be connected to V OUT as indicated in Figure 8. The output voltage is selected by the following formula: ( ) Rb Ra OUT V V+ =1 6 . 0 VIN VSense VS0 VS2 EP53A8L 10µF 0805 4.7uF 0603 VOUT VOUT AGND ENABLE Ra Rb VFB VS1 PGND AVIN PVIN

100 Ohms

Figure 4: EP53A8LQI using external divider Ra must be chosen as 237KΩ to maintain loop gain. Then Rb is given as: Ω−= 6 . 0 10 2 . 1423 OUT b V x R VOUT can be programmed over the range of 0.6V to (VIN – 0.5V). NOTE: Dynamic Voltage Scaling is not allowed between internal preset voltages and external divider. VS2 VS1 VS0 VOUT 0 0 0 1.50 0 0 1 1.45 0 1 0 1.20 0 1 1 1.15 1 0 0 1.10 1 0 1 1.05 1 1 0 0.8 1 1 1 EXT www.altera.com/enpirion, Page 10

The EP53A8HQI V OUT settings are optimized for higher nominal voltages such as those required to power IO, RF, or IC memory. The preset voltages range from 1.8V to 3.3V. There are eight (8) preset output voltage settings. The EP53A8HQI does not have an external divider option. As with the EP53A8LQI, the VID pin settings can be changed while the device is enabled. Table 2 shows the VS0-VS2 pin logic states for the EP53A8HQI and the associated output voltage levels. A logic “1” indicates a connection to AVIN or to a “high” logic voltage level. A logic “0” indicates a connection to AGND or to a “low” logic voltage level. These pins can be either hardwired to AVIN or AGND or alternatively can be driven by standard logic levels. Logic levels are defined in the electrical characteristics table. Any level between the logic high and logic low is indeterminate. These pins must not be left floating. Table 2: EP53A8HQI VID Voltage Select Settings Power-Up/Down Sequencing During power -up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before AVIN. The PVIN should never be powered when AVIN is off. During power down, the AVIN should not be powered down before the PVIN. Tying PVIN and AVIN or all three pins (AVIN, PVIN, ENABLE) together during power up or power down meets these requirements Pre-Bias Start-up The EP53A8xQI does not support startup into a pre-biased condition. Be sure the output capacitors are not charged or the output of the EP53A8xQI is not pre-biased when the EP53A8xQI is first enabled. Input Filter Capacitor The input filter capacitor requirement is a 4.7µF 0603 low ESR MLCC capacitor. The input capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and with temperature, and are not suitable for switch- mode DC-DC converter input filter applications. Output Filter Capacitor The output filter capacitor requirement is a minimum of 10µF 0805 MLCC. Ripple performance can be improved by using 2x10µF 0603 or 2x10µF 0805 MLCC capacitors. The maximum output filter capacitance next to the output pins of the device is 60µF low ESR MLCC capacitance. V OUT has to be sensed at the last output filter capacitor next to the EP53A8xQI. Additional bulk capacitance for decoupling and bypass can be placed at the load as long as there is sufficient separation between the V OUT Sense point and the bulk capacitance. The separation provides an inductance that isolates the control loop from the bulk capacitance. Excess total capacitance on the output (Output Filter + Bulk) can cause an over -current condition at startup. Refer to the section on Soft-Start for the maximum total capacitance on the output. The output capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch-mode DC-DC converter output filter applications. VS2 VS1 VS0 VOUT 0 0 0 3.3 0 0 1 3.0 0 1 0 2.9 0 1 1 2.6 1 0 0 2.5 1 0 1 2.2 1 1 0 2.1 1 1 1 1.8 www.altera.com/enpirion, Page 11

Figure 9 shows critical components and layer 1 traces of a recommended minimum footprint EP53A8LQI/EP53A8HQI layout with ENABLE tied to V IN. Alternate ENABLE configurations, and other small signal pins need to be connected and routed according to specific customer application. Please see the Gerber files on the Altera website www.altera.com/enpirion for exact dimensions and other layers. Please refer to Figure 9 while reading the layout recommendations in this section. Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the E P53A8QI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the E P53A8QI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. Recommendation 2: Input and output grounds are separated until they connect at the PGND pins. The separation shown on Figure 9 between the input and output GND circuits helps minimize noise coupling between the converter input and output switching loops. Recommendation 3: The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. Please see the Gerber files on the Altera website www.altera.com/enpirion Figure 9: Top PCB Layer Critical Components and Copper for Minimum Footprint Recommendation 4: Multiple small vias should be used to connect the ground traces under the device to the system ground plane on another layer for heat dissipation. The drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm . Do not use thermal reliefs or spokes to connect the vias to the ground plane. It is preferred to put these vias under the capacitors along the edge of the GND copper closest to the +V copper. Please see Figure 9. These vias connect the input/output filter capacitors to the GND plane and help reduce parasitic inductances in the input and output current loops. If the vias cannot be placed under C IN and COUT, then put them just outsi de the capacitors along the GND. Do not use thermal reliefs or spokes to connect these vias to the ground plane. Recommendation 5: AVIN is the power supply for the internal small -signal control circuits. It should be connected to the input voltage at a quiet point. In Figure 9 this connection is made with RAVIN at the input capacitor close to the VIN connection. www.altera.com/enpirion, Page 12

Figure 10: EP53A8xQI Package PCB Footprint www.altera.com/enpirion, Page 13

Figure 51: EP53A8xQI Package Dimensions Packing and Marking Information : www.altera.com/support/reliability/packing/rel-packing-and-marking.html Contact Information Altera Corporation

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San Jose, CA 95134 Phone: 408-544-7000 www.altera.com © 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com/enpirion, Page 14