EP4001 EOREX | Alldatasheet

Document overview

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Technical content

Features

  • Low Start-up Voltage: 1.0V
  • 35μA Quiescent Supply Current in Switch-off mode
  • <1μA Shutdown Current
  • 90% Efficiency
  • Excellent Load and Line Regulation Characteristics
  • 350mΩ Internal MOSFET
  • 450KHz Fixed Switching Frequency
  • Small 6-Lead SOT-23 Package

Applications

  • PDA
  • DSC
  • LCD Panel
  • RF-Tags
  • MP3
  • Portable Equipment
  • Wireless key board and mouse

Description

The EP4001 is a micropower, high efficiency, and low voltage step-up DC/DC converter intended for use in battery powered wireless applications. With the low start-up input voltage below 1V, the device is suitable for applications with 1 or 2 AA cells, providing up to 300mA output current at 3.3V output. The 35µA low quiescent current, zero shutdown current and high efficiency maintains long battery lifetime. A switching frequency of 450KHz minimizes solution footprint by allowing the use of small inductors and ceramic capacitors. The device is offered in a low profile (1mm) small 6-lead SOT-23 package. The current mode PWM design is optimized for stable and high efficiency operations over a wide range of load currents. With low resistance internal MOSFET switches, the EP4001 maintains high efficiency over a wide range of load current. In addition to its high efficiency at moderate and heavy loads, the EP4001 includes automatic PFM operation that improves efficiency of the power converter at light loads. Typical Application VOUT= FB × ⎟⎠ ⎞⎜⎝ ⎛ + R11 Where FB=1.22V Figure 1-Basic application circuit with EP4001

Aug. 2006 www.eorex.com Pin Assignment

Ordering Information

1 EN Chip enable EP4001 gets into shutdown mode when EN pin set to low

2 EXT Output pin for driving external NMOS. 3 GND Ground. 4 SW Pin for switching. 5 V IN Supply Input Pin. Must be closely decoupled to GND, Pin 2, with a 2.2µF or greater ceramic capacitor.

6 FB Feedback input pin Internal reference voltage for the error amplifier is

1.25V

Aug. 2006 www.eorex.com Thermal Resistance (Note 1) Package θJA θJC TSOT23-6 220°C/W 110°C/W Absolute Maximum Rating (Note 2) Symbol Item Rating Units VIN Input Supply Voltage -0.3 ~ +6 V VSW SW Pin Switch Voltage -0.3 ~ +6 V Other I/O Pin Voltage -0.3 ~ V IN+0.3 V ISW SW Pin Switch Current 2.5 A IEXT EXT Pin Driver Current 150 mA TJ Junction Temperature (Note 3) +125 °C TSTG Storage Temperature Range -65 ~ +150 °C Note 1:Thermal Resistance is specified with approximately 1 square of 1 oz cooper. Note 2:Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. Moreover, such values for any two items must not be reached simultaneously. Operation above these absolute maximum ratings may cause degradation or permanent damage to the device. These ar e stress ratings only and do not necessarily imply functional operation below these limits. Note 3:T J is calculated from the ambient temperature T A and power dissipation P D according to the following formula: TJ = TA + (PD) × (220°C/W)

Aug. 2006 www.eorex.com

Electrical Characteristics

(VIN = 1.5V, VOUT=3.3V, IL = 0mA, TA=25°C, Test Circuit Figure 2, unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Units VS Start-up Voltage I L=1mA 0.85 1.05 V Operating V OUT Range V IN pin voltage 2 4.2 V IQ Quiescent Current (Shutdown Current) EN pin = 0V, VIN=4.5V 0.01 1 µA IQ Quiescent Current (Switch-off Current) VIN=6V 35 50 µA IQ Quiescent Current (Continuous Switching Current) VIN=EN=3.3V, VFB=GND 0.4 0.6 mA IQ Quiescent Current (No Load Current) 110 µA TA =+25°C 1.195 1.220 1.245 V 0°C≤TA ≤ 85°C 1.190 1.220 1.250 V VFB Feedback Reference Voltage -40°C≤TA ≤ 85°C 1.183 1.220 1.257 V FS Switching Frequency 380 450 520 KHz DMAX Maximum Duty 85 90 % SW ON Resistance 0.03 1.1 Ω ILIMIT Current Limit Setting 2 A EXT ON Resistance to V IN 16 Ω EXT ON Resistance to GND 18 Ω VOUT Output Voltage VIN=1.5V, IL=100mA -40°C≤TA ≤ 85°C 3.200 3.300 3.400 V VOUT Output Voltage VIN=3.0V, IL=300mA -40°C≤TA ≤ 85°C 3.200 3.300 3.400 V ∆VLINE Line Regulation V IN=1V to 3V, IL=1mA 0.3 mV/V ∆VLOAD Load Regulation VIN=1.5V, IL=1mA to 100mA 0.4 mV/mA ∆VLOAD Load Regulation VIN=3.0V, IL=1mA to 300mA 0.4 mV/mA EN Pin Trip Level 0.4 0.8 1.2 V TS Temperature Stability for V OUT 110 ppm/°C Thermal Shutdown 165 °C Thermal Shutdown Hysteresis 10 °C

Aug. 2006 www.eorex.com Typical Performance Characteristics (Test Figure 2 above unless otherwise specified) Efficiency (%) Efficiency (%) Output Voltage (V) Start Up Voltage (V) Switching Frequency (KHz) Supply Current (uA)

Aug. 2006 www.eorex.com Functional Block Diagram Figure 3-EP4001 Functional Block Diagram Operation The EP4001 is a current mode PWM boost converter wi th a fixed switching frequency at 450KHz. It is able to operate from an input voltage below 1V. With its low RDS(ON) internal MOSFET switch, this device maintains the high efficiency over a wide range of load current. Low Voltage Start-Up The EP4001 will start up with a typical V IN voltage at 1V. The low voltage start-up circuitry controls the internal NMOS switch allowing the devices to start up into an output load. Once V OUT exceeds 1.8V, the start-up circuitry is disabled and normal fixed frequenc y PWM operation is initiated. In this mode, the EP4001 operates independent of V IN. The limiting factor for the app lication becomes t he ability of the battery to supply sufficient energy to the output. Low Noise Fixed Frequency Operation Oscillator: The frequency of operation is internally set to 450KHz.

Aug. 2006 www.eorex.com Low Noise Fixed Frequency Operation Oscillator The frequency of operation is internally set to 450KHz. Error Amp: The internal 1.22V reference voltage is compared to the voltage at the FB pin to generate an error signal at the output of the error amplifier. A voltage divider from VOUT to ground programs the output according to the equation: VOUT= FB × ⎟⎠ ⎞⎜⎝ ⎛ + R11 Where FB=1.22V Due to device performance limitation, the EP4001 is limited to applications with output voltage less than 4.2V, until the problem is corrected at later date. PWM Mode Refer to Figure 3, functional block diagram. The main gain block is a comparator that sums four signals: feedback voltage, reference, current-sensing and slope compensation ramp. This direct-summing method approaches the ideal of cycl e-by-cycle control of output voltage. Under heavy loads, the controller operates in full PWM mode. Every pulse from the oscillator sets the output latch and turns on the NMOS switch for a period determined by the duty factor and current limit. PFM Mode Operation Portable devices frequently spend extended time in low power or standby mode, only switching to high power mode when specific function s are enabled. Maintain high effici ency over a wide range of load current is critical for prolong battery life. In additi on to its high efficiency at moderate and heavy loads, the EP4001 includes automatic PFM operation that impr oves efficiency of the converter at light load. PFM operation is initiated if the output load current falls below an internally programmed threshold. Once initiated, the PFM operation circuitry shuts down mo st of the device, only keeping alive the circuitry required to monitor the output voltage.

Aug. 2006 www.eorex.com Inductor Selection The EP4001 can utilize small surface mount and chip inductors operating at 450KHz switching frequency. The inductor current ripple is typically set for 20% to 40% of the maximum inductor current. The inductor should have low ESR (series resistance of the winding s) to reduce the I2R power losses, and must be able to handle the peak inductor current without saturating. Output and Input Capacitor Selection Low ESR (equivalent series resistance) capacitors should be used to minimize the output voltage ripple. Low ESR input capacitors reduce input switching noise and reduce the peak current drawn from the battery. The input decoupling capacitor should be located as close as possible to the device. Output Voltage Setting The output voltage of the switching regulator (VOUT) is determined by (Eq.1) Feedback Loop Design The value selection for R1 and R2 is based on the trade-off between quiescent current consumption and interference immunity. Higher values for R1 and R2 will reduce the quiescent current, while Lower values for R1 and R2 has the advantage of a better noise immunity, and is less sensitive to other interferences. However, a resistor having a value higher than 5m Ω is not recommended. The noise immunity of the feedback loops can be improved by using a proper val ue of feed forward capacitor in parallel with R1. The value for this capacitor is between 0 to 33pF for feedback resistors of m Ω, and 10nF to 0.1 μF for feedback resistors of tens to hundreds kΩ. Be aware that such kind of “high impedance feedback Loops” is sensitive to any interference, which require careful layout and avoid any interference. Layout Guide 1. The power traces, which are consisted of GND trace, the SW trace and the V IN trace should be kept short, direct and wide. 2. Keep the switching node, SW, away from the sensitive FB node. 3. Keep the distance between pin SW and L1 as close as possible, and no more than 3-4mm. 4. Keep the distance between capacitor C3 and L1 as close as possible, no more than 3-4mm. 5. Connect the (+) plate of C IN to VIN as closely as possible. This capacitor provides the AC current to the internal power MOSFETs. 6. Connect pin FB directly to t he feedback resistors. T he resistive divider R1/ R2 must be connected between the (+) plate of COUT and ground. 7. Keep the (-) plates of CIN and COUT as close as possible.

Aug. 2006 www.eorex.com Package Description 6pin TSOT-23 MILLIMETERS INCHES DIM A 0.90 − 1.10 0.035 − 0.043 A1 0.01 − 0.13 0.0004 − 0.005 B 0.30 − 0.50 0.012 − 0.020 C 0.09 − 0.20 0.004 − 0.008 D 2.80 − 3.00 0.110 − 0.118 H 2.50 − 3.10 0.098 − 0.122 E 1.50 − 1.70 0.059 − 0.067 e 0.95 REF. 0.037 REF. e1 1.90 REF. 0.075 REF. L1 0.20 − 0.55 0.008 − 0.022 L 0.35 − 0.80 0.014 − 0.031