EP3003

EP3003_15 EOREX | Alldatasheet

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Technical content

Rev.03 EP3003

Revision History

Revision 0.1 (Apr. 2006) - First release. Revision 0.2 (Feb. 2008).. - Modify ordering infomation.(page 2) Revision 0.3 (Apr. 2008).. - Update currently version “not supported burst mode＂ information. - Modify Typical Performance Characteristics without burst mode (page 5)

Rev.03 EP3003 2-CH, 600mA Synchronous Step-down Converter

DESCRIPTION

The EP3003 is a dual channel, 1.5MHz constant frequency, slope compensated current mode PWM step-down converter. The EP3003 can supply 600mA of load current from a 2.5V to 5.5V input voltage. Each output voltage is adjustable from 0.6V to 5V. It is ideal for powering portable equipment that runs from a single cell lithium-Ion (Li+) battery. Internal synchronous 0.35Ω, 1A power switches provide high efficiency without the need for external Schottky diodes. The EP3003 can also run at 100% duty cycle for low dropout operation, extending battery life in portable system. Pulse Skipping Mode operation at light loads provides very low output ripple voltage for noise sensitive applications.

APPLICATIONS

‧ Cellular and Smart Phones ‧ Microprocessors and DSP Core Supplies ‧ Wireless and DSL Modems ‧ PDAs ‧ Portable Instruments / Media Players ‧ Digital Cameras ‧ PC Cards

FEATURES

‧ High Efficiency: Up to 96% ‧ 1.5MHz Constant Switching Frequency ‧ 600mA Output Current ‧ Integrated Main Switch and Synchronous Rectifier ‧ High Switch Current: 1A on Each Channel ‧ 2.5V to 5.5V Input Voltage Range ‧ Output Voltage as Low as 0.6V ‧ 100% Duty Cycle in Dropout ‧ Low Quiescent Current: 50µA Slope Compensated Current Mode Co‧ ntrol for Excellent Line and Load Transient Response ‧ Can be synchronized to an external oscillator Short Circuit Protection‧ ‧ Power-on Reset Output Thermal Fault Protection‧ ‧ <1uA Shutdown Current ‧ Small Thermally Enhanced 10-Pin MSOP and 3mm × 3mm DFN Packages Typical Application Figure 1. Basic Application Circuit for 2.5V and 1.8V Output Voltages

Rev.03 EP3003 Package/Order Information MSOP: D FN:

Ordering Information

Absolute Maximum Rating (Note1) Storage Temperature Range (MSOP) -65°C to +150°C Storage Temperature Range (DFN) .. -65°C to +125°C Note 1. Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.

Rev.03 EP3003 Electrical Characteristics (Note 2) : (VIN =VRUN= 3.6V, TA = 25°C, unless otherwise noted.) Parameter Conditions MIN TYP MAX unit Input Voltage Range 2.5 5.5 V Input DC Supply Current Active Mode Shutdown Mode VFB=0.5V RUN=0V, VIN=5.5V, MODE/SYNC=0V 600 0.1 800 1.0 µA µA TA = +25°C 0.588 0.600 0.612 V TA= 0°C ≦ T A ≦ 85°C 0.586 0.600 0.613 V Regulated Feedback Voltage TA= -40°C ≦ T A ≦ 85°C 0.582 0.600 0.618 V VFB Input Bias Current 30 nA Reference Voltage Line Regulation VIN = 2.5V to 5.5V 0.3 0.5 %/V Threshold: VFBX Ramping Up, MODE/SYNC = 0V VFBX Ramping Down, MODE/SYNC = 8.5 -8.5 Power-On Reset On-Resistance 100 200 Ω Power-On Reset (POR) Power-On Reset Delay 270K Cycles Output Voltage Load Regulation 0.5 % Peak Inductor Current VIN=3V, VFB=0.5V Duty Cycle < 35% 0.75 1.00 1.25 A Oscillator Frequency VFBX =0.6V 1.2 1.5 1.8 MHz Synchronization Frequency

1.5 MHz

RDS(ON) Top Switch On-Resistance Bottom Switch On-Resistance 0.35 0.30 0.45 0.45 Ω Ω SW Leakage VRUN = 0V, VFBX= 0V, VIN = 5V 0.01 1 µA RUN Threshold -40°C ≦ T A ≦ 85°C 0.3 1.0 1.50 V RUN Leakage Current ±0.01 ±1 µA Note 2. 100% production test at +25°C. Specifications over the temperature range are guaranteed by design and characterization.

Rev.03 EP3003 Typical Performance Characteristics (TBD)

Rev.03 EP3003 Functional Block Diagram

Rev.03 Pin Description PIN NAME FUNCTION 1 VFB1 Output Voltag e F eedback Pin. An internal resistive div ider divides the o utput voltag e down for comp arison to the i nternal reference voltage. No minal voltage for this pin is 0.6V. 2 RUN1 Regulator 1 E nable contro l input. F orcing this pin to VIN enabl es regu lator 1, while forcing it to GND ca uses re gulator 1 to shut do wn. In shutdown, a ll functions are disabled drawing <1µA supply current. Do not leave RUN floating. 3 VIN Main Power Supply. Must be closely decoupled to GND with a ceramic capacitor. 4 SW1 Regulator 1 Power Switch Output. Switch Node Connection to the Inductor. This pin swings from VIN to GND.

5 GND Ground

6 Mode/Sync Combination o f Mode Sel ection a nd Oscill ator S ynchronization. T his pin controls th e operation of the d evice. W hen tie d to V IN or GND, Bur st Mode o peration or p ulse skipping mode is sel ected, respectively. Do not float this pin. The oscillation frequency can be synchronized to an external oscillator applied to this pin and pulse skipping mode is automatically selected. ( Current version “Burst Mode” is not supported ) 7 SW2 Regulator 2 P ower S witch O utput. S witch No de Con nection to the Indu ctor. This pin swings from VIN to GND. /POR Power-On R eset. This common-dr ain l ogic out put is p ulled to GND when the outp ut voltage is not within ±8.5% of regulation and goes high after 175ms when both channels are within regulation. 9 RUN2 Regulator 2 E nable co ntrol input. F orcing this pi n to V IN ena bles r egulator 2, while forcing it to GND causes regulator 2 to shut down. VFB2 Output Voltage Feedback Pin for Regulator 2. See VFB1 section.

11 Power

Connect to the (–) terminal of COUT , and (–) terminal o f C IN. Must be soldere d to electrical ground on PCB.

The EP3003 uses current mode architecture with frequency set at 1.5MHz and can be synchronized to an e xternal os cillator. Both c hannels s hare the same clo ck and run i n-phase. T o suit a variet y of applications, the selectable Mode pin allows the user to trade-off noise for efficiency. Output voltage is set by an external divider returned to the VF B pins. An error amplifier compares the divided output voltage with a reference voltage of 0.6V and adjusts the peak inductor current accordingly. Over voltage a nd under voltage comparators will pull the POR output lo w if the output voltage is not within ±8.5%. The POR output will go high after 270K clock cycles of achieving regulation. During normal operation, the top power switch (P-channel MOSFET) is turned on at the beginning of a clock cycle when the VFB voltage is below the reference voltage. The current into the inductor and the load increases until the current limit is reached. The switch turns off and energy stored in the in ductor flows through the bottom s witch (N-channel MOSFET) into the load until the next clock cycle. The peak inductor current is controlled by the internally compensated ITH voltage, which is the output of the error am plifier. This amplifier compares the VF B pin to the 0.6V refer ence. When the load c urrent increases, the V FB voltage decre ases sli ghtly b elow t he refe rence. T his decre ase causes the err or amplifier to increase the IT H voltage until th e average inductor current matches the ne w load current. The main control loop is shut down by pulling the RUN pin to ground. Low Current Control Pulse skipping mode is available to control the operation of the EP3003 at low currents. For lower ripple noise at low currents, the pulse skipping mode can be used. In this mode, the EP30 03 continues to switch at a constant frequency down to very low currents, where it will begin skipping pulses. Rev.03 8

The EP3003 al lows the mai n switch to remai n on for more than o ne switching cycle and increases the duty cycle until it reaches 100%. The output voltage then is the in put voltage minus the voltage drop across the main s witch and the induct or. At lo w in put su pply volta ge, the R DS(ON) of the P Chan nel MOSFET increases, and the efficiency of the converter decreases. Caution must be exercised to ensure the heat dissipated not to exceed the maximum junction temperature of the IC. Note 3. The duty cycle D of a step-down converter is defined as: D = TON x fOSC x 100% ≈ VOUT/VIN x 100% where TON is the main switch on time, and fOSC is the oscillator frequency (1.5MHz). Maximum Load Current The EP3003 will operate with input supply voltage as low as 2.5V, however, the maximum load current decreases at l ower input due to large IR drop on t he main switch and s ynchronous rectifier. The slope compensation sign al red uces the peak ind uctor cu rrent as a function of t he dut y c ycle to preve nt sub-harmonic oscillations at duty cycles greater than 50%. Conversely the current limit increases as the duty cycle decreases. APPLICATIONS INFORMATION A general application circuit for EP3003 is shown in Figure 1, which is the baseline for some calculation mentioned below. All external component selection for EP3003 application design will be illustrated as the following. Setting the Output Voltage The external resistor sets the output voltage according to the following equation: ⎞⎜⎝ ⎛ += 1 216.0 R RVVout R1 = 150KΩ; R2 = 300KΩ for VOUT = 1.8V; R3 = 100KΩ; R4 = 330KΩ for VOUT = 2.5V. Rev.03 9

For most desi gns, the EP3 003 op erates with ind uctors o f 1 µH to 4.7 µH. Lo w i nductance va lues a re physically sm aller but re quire faster s witching, which re sults in s ome efficienc y loss. Large val ue inductors lower ripple current and small value inductors result in high ripple currents. The inductor value can be derived from the following equation: OSCLIN OUTINOUT fIV VVVL ×∆× −×= where is indu ctor Rippl e C urrent. Cho ose induct or ripple curre nt ap proximately 35% of the maximum load current 600mA, or 210mA. LI∆ For output voltages ab ove 2.0V, when lig ht-load efficienc y is important, the minimum recommended inductor is 2.2 µH. For optimum voltage-positioning load transients, choose an inductor with DC s eries resistance in the 50mΩ to 150mΩ range. For higher efficiency at heavy loads (above 200mA), or minimal load regulation (but some tra nsient overshoot), the resista nce should be kept be low 100mΩ. The DC current rating of the ind uctor should be at least eq ual to t he maximum load current plus half the ri pple current to prevent core saturation (600mA+105mA). Table 1 lists some t ypical surface mount inductors that meet target applications for the EP3003. Part # L (µH) Max DCR (m.) Rated D.C. Current (A) Size WxLxH (mm) Sumida CR43 1.4 2.2 3.3 4.7 56.2 71.2 86.2 108.7 2.52 1.75 1.44 1.15 4.5x4.0x3.5 Sumida CDRH4D18 1.5 2.2 3.3 4.7 110 162 1.32 1.04 0.84 4.7x4.7x2.0 Toko D312C 1.5 2.2 3.3 4.7 120 140 180 240 1.29 1.14 0.98 0.79 3.6x3.6x1.2 Rev.03 10

The input capacitor reduces the surge current drawn from the input and switching noise from the device. The input capacitor impedance at the switching frequency shall be less than input source impedance to prevent high frequ ency s witching current passin g to the i nput. A lo w E SR input cap acitor sized for maximum RM S current must be used. Ceramic capac itors with X5R o r X7R di electrics are highl y recommended because of their lo w ESR and small temperature coefficients. A 10µF ceramic capacitor for most applications is sufficient. Output Capacitor Selection The output ca pacitor is r equired to kee p the output voltage ripple small and to ensure regulation loop stability. The output capacitor must have low impedance at the switching frequency. Ceramic capacitors with X5R or X7R d ielectrics are rec ommended due to their l ow ES R an d mi nimization of lar ge temperature and voltage coefficients. The output ripple OUTV∆ is determined by: −×≤∆ 38 CfESRLfV VVVV OSCOSCIN OUTINOUT OUT Rev.03 11

DFN: Rev.03 12

MSOP: Rev.03 13