EP2A15

EP2A15 ALTERA | Alldatasheet

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August 2002, ver. 3.0 Data Sheet DS-APEXII-3.0 Features... ■ Programmable logic device (PLD) manufactured using a 0.15-µm all- layer copper-metal fabrication process (up to eight layers of metal) – 1-gigabit per second (Gbps) True-LVDS TM, LVPECL, pseudo current mode logic (PCML), and HyperTransportTM interface – Clock-data synchronization (CDS) in True-LVDS interface to correct any fixed clock-to-data skew – Enables common networking and communications bus I/O standards such as RapidIOTM, CSIX, Utopia IV, and POS-PHY Level 4 – Support for high-speed external memory interfaces, including zero bus turnaround (ZBT), quad data rate (QDR), and double data rate (DDR) static RAM (SRAM), and single data rate (SDR) and DDR synchronous dynamic RAM (SDRAM) –3 0 % to 40% faster design performance than APEX TM 20KE devices on average – Enhanced 4,096-bit embedded system blocks (ESBs) implementing first-in first-out (FIFO) buffers, Dual-Port+ RAM (bidirectional dual-port RAM), and content-addressable memory (CAM) – High-performance, low-power copper interconnect – Fast parallel byte-wide synchronous device configuration – Look-up table (LUT) logic available for register-intensive functions ■ High-density architecture – 1,900,000 to 5,250,000 maximum system gates (see Table 1) – Up to 67,200 logic elements (LEs) – Up to 1,146,880 RAM bits that can be used without reducing available logic ■ Low-power operation design – 1.5-V supply voltage – Copper interconnect reduces power consumption – MultiVolt TM I/O support for 1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces – ESBs offer programmable power-saving mode

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APEX II Programmable Logic Device Family Data Sheet Notes to Table 1: (1) Each device has 36 input channels and 36 output channels. (2) EP2A15 and EP2A25 devices have 56 input and 56 output channels; EP2A40 and EP2A70 devices have 88 input and 88 output channels. (3) PLL: phase-locked loop. True-LVDS PLLs are dedicated to implement True-LVDS functionality. (4) Two internal outputs per PLL are available. Additionally, the device has one external output per PLL pair (two external outputs per device). ...and More

Features

■ I/O features – Up to 380 Gbps of I/O capability – 1-Gbps True-LVDS, LVPECL, PCML, and HyperTransport support on 36 input and 36 output channels that feature clock synchronization circuitry and independent clock multiplication and serialization/deserialization factors – Common networking and communications bus I/O standards such as RapidIO, CSIX, Utopia IV, and POS-PHY Level 4 enabled – 400-megabits per second (Mbps) Flexible-LVDS and HyperTransport support on up to 88 input and 88 output channels (input channels also support LVPECL) – Support for high-speed external memories, including ZBT, QDR, and DDR SRAM, and SDR and DDR SDRAM – Compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits – Compliant with 133-MHz PCI-X specifications – Support for other advanced I/O standards, including AGP, CTT, SSTL-3 and SSTL-2 Class I and II, GTL+, and HSTL Class I and II – Six dedicated registers in each I/O element (IOE): two input registers, two output registers, and two output-enable registers – Programmable bus hold feature – Programmable pull-up resistor on I/O pins available during user mode Table 1. APEX II Device Features

APEX II Programmable Logic Device Family Data Sheet – Programmable output drive for 3.3-V LVTTL at 4 mA, 12 mA, 24 mA, or I/O standard levels – Programmable output slew-rate control reduces switching noise – Hot-socketing operation supported – Pull-up resistor on I/O pins before and during configuration ■ Enhanced internal memory structure – High-density 4,096-bit ESBs – Dual-Port+ RAM with bidirectional read and write ports – Support for many other memory functions, including CAM, FIFO, and ROM – ESB packing mode partitions one ESB into two 2,048-bit blocks ■ Device configuration – Fast byte-wide synchronous configuration minimizes in-circuit reconfiguration time – Device configuration supports multiple voltages (either 3.3 V and 2.5 V or 1.8 V) ■ Flexible clock management circuitry with eight general-purpose PLL outputs – Four general-purpose PLLs with two outputs per PLL – Built-in low-skew clock tree – Eight global clock signals – ClockLock TM feature reducing clock delay and skew – ClockBoost TM feature providing clock multiplication (by 1 to 160) and division (by 1 to 256) – ClockShift TM feature providing programmable clock phase and delay shifting with coarse (90°, 180°, or 270°) and fine (0.5 to 1.0 ns) resolution ■ Advanced interconnect structure – All-layer copper interconnect for high performance – Four-level hierarchical FastTrack ® interconnect structure for fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) – Interleaved local interconnect allowing one LE to drive 29 other LEs through the fast local interconnect ■ Advanced software support – Software design support and automatic place-and-route provided by the Altera® QuartusTM II development system for Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations –A l t e r a M e g a C o r e® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions optimized for APEX II architecture

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TM device package sizes, options, and I/O pin counts. package type to identify which I/O pins are migratable. (2) I/O pin counts include dedicated clock and fast I/O pins. Table 2. APEX II Package Sizes Table 3. APEX II Package Options & I/O Pin Count Notes (1), (2)

APEX II Programmable Logic Device Family Data Sheet General

Description

APEX II devices integrate high-speed differential I/O support using the True-LVDS interface. The dedicated serializer, deserializer, and CDS circuitry in the True-LVDS interface support the LVDS, LVPECL, HyperTransport, and PCML I/O standards. Flexible-LVDS pins located in regular user I/O banks offer additional differential support, increasing the total device bandwidth. This circuitry, together with enhanced IOEs and support for numerous I/O standards, allows APEX II devices to meet high-speed interface requirements. APEX II devices also include other high-performance features such as bidirectional dual-port RAM, CAM, general-purpose PLLs, and numerous global clocks. Configuration The logic, circuitry, and interconnects in the APEX II architecture are configured with CMOS SRAM elements. APEX II devices are reconfigurable and are 100% tested prior to shipment. As a result, test vectors do not have to be generated for fault coverage. Instead, the designer can focus on simulation and design verification. In addition, the designer does not need to manage inventories of different ASIC designs; APEX II devices can be configured on the board for the specific functionality required. APEX II devices are configured at system power-up with data either stored in an Altera configuration device or provided by a system controller. Altera offers in-system programmability (ISP)-capable configuration devices, which configure APEX II devices via a serial data stream. The enhanced configuration devices can configure any APEX II device in under 100 ms. Moreover, APEX II devices contain an optimized interface that permits microprocessors to configure APEX II devices serially or in parallel, synchronously or asynchronously. This interface also enables microprocessors to treat APEX II devices as memory and to configure the device by writing to a virtual memory location, simplifying reconfiguration. APEX II devices also support a new byte-wide, synchronous configuration scheme at speeds of up to 66 MHz using EPC16 configuration devices or a microprocessor. This parallel configuration reduces configuration time by using eight data lines to send configuration data versus one data line in serial configuration. APEX II devices support multi-voltage configuration; device configuration can be performed at 3.3 V and 2.5 V or 1.8 V.

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APEX II Programmable Logic Device Family Data Sheet After an APEX II device has been configured, it can be reconfigured in- circuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications. Software APEX II devices are supported by the Altera Quartus II development system: a single, integrated package that offers hardware description language (HDL) and schematic design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, SignalTap logic analysis, and device configuration. The Quartus II software runs on Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations. The Quartus II software includes the LogicLock incremental design feature. The LogicLock feature allows the designer to make pin and timing assignments, verify functionality and performance, and then set constraints to lock down the placement and performance of a specific block of logic using LogicLock constraints. Constraints set by the LogicLock function guarantee repeatable placement when implementing a block of logic in a current project or exporting the block to another project. The constraints set by the LogicLock feature can lock down logic to a fixed location in the device. The LogicLock feature can also lock the logic down to a floating location, and the Quartus II software determines the best relative placement of the block to meet design requirements. Adding additional logic to a project will not affect the performance of blocks locked down with LogicLock constraints. The Quartus II software provides NativeLink interfaces to other industry- standard PC- and UNIX workstation-based EDA tools. For example, designers can open the Quartus II software from within third-party design tools. The Quartus II software also contains built-in optimized synthesis libraries; synthesis tools can use these libraries to optimize designs for APEX II devices. For example, the Synopsys Design Compiler library, supplied with the Quartus II development system, includes DesignWare functions optimized for the APEX II architecture. Functional APEX II devices incorporate LUT-based logic, product-term-based logic, memory, and high-speed I/O standards into one device. Signal interconnections within APEX II devices (as well as to and from device pins) are provided by the FastTrack interconnect—a series of fast, continuous row and column channels that run the entire length and width of the device.

APEX II Programmable Logic Device Family Data Sheet Each I/O pin is fed by an IOE located at the end of each row and column of the FastTrack interconnect. Each IOE contains a bidirectional I/O buffer and six registers that can be used for registering input, output, and output-enable signals. When used with a dedicated clock pin, these registers provide exceptional performance and interface support with external memory devices such as DDR SDRAM and ZBT and QDR SRAM devices. IOEs provide a variety of features such as: 3.3-V, 64-bit, 66-MHz PCI compliance, 3.3-V, 64-bit, 133-MHz PCI-X compliance, Joint Test Action Group (JTAG) boundary-scan test (BST) support, output drive strength control, slew-rate control, tri-state buffers, bus-hold circuitry, programmable pull-up resistors, programmable input and output delays, and open-drain outputs. APEX II devices offer enhanced I/O support, including support for 1.5 V, 1.8 V, 2.5 V, 3.3 V, LVCMOS, LVTTL, HSTL, LVDS, LVPECL, HyperTransport, PCML, 3.3-V PCI, PCI-X, GTL+, SSTL-2, SSTL-3, CTT, and 3.3-V AGP I/O standards. High-speed (up to 1.0 Gbps) differential transfers are supported with True-LVDS circuitry for LVDS, LVPECL, HyperTransport, and PCML I/O standards. The optional CDS feature corrects any clock-to-data skew at the True-LVDS receiver channels, allowing for flexible board topologies. Up to 88 Flexible-LVDS channels support differential transfer at up to 400 Mbps (DDR) for LVDS and HyperTransport I/O standards. An ESB can implement many types of memory, including Dual-Port+ RAM, CAM, ROM, and FIFO functions. Embedding the memory directly into the die improves performance and reduces die area compared to distributed-RAM implementations. The abundance of cascadable ESBs ensures that the APEX II device can implement multiple wide memory blocks for high-density designs. The ESB’s high speed ensures it can implement small memory blocks without any speed penalty. The abundance of ESBs, in conjunction with the ability for one ESB to implement two separate memory blocks, ensures that designers can create as many different-sized memory blocks as the system requires. Figure 1 shows an overview of the APEX II device.

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Figure 1. APEX II Device Block Diagram Table 4 lists the resources available in APEX II devices. purpose PLLs for clock management. Table 4. APEX II Device Resources

APEX II devices are constructed from a series of MegaLABTM structures. interconnect. Figure 2 shows the MegaLAB structure. Figure 2. MegaLAB Structure transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs. LABs, allowing the use of a fast local interconnect for high performance.

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Figure 3 shows the APEX II LAB. Figure 3. APEX II LAB Structure when implementing counters, they can also be used with other functions. in an LAB, both LAB-wide clock signals are used. can drive two local interconnect areas.

distribution. Figure 4 shows the LAB control signal generation circuit. Figure 4. LAB Control Signal Generation (2) The SYNCCLR signal can be generated by the local interconnect or global signals. routing structures. See Figure 5.

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Figure 5. APEX II Logic Element LUT drives the outputs of the LE.

APEX II Programmable Logic Device Family Data Sheet Each LE has two outputs that drive the local, MegaLAB, or FastTrack interconnect routing structure. Each output can be driven independently by the LUT’s or register’s output. For example, the LUT can drive one output while the register drives the other output. This feature, called register packing, improves device utilization because the register and the LUT can be used for unrelated functions. The LE can also drive out registered and unregistered versions of the LUT output. The APEX II architecture provides two types of dedicated high-speed data paths that connect adjacent LEs without using local interconnect paths: carry chains and cascade chains. A carry chain supports high-speed arithmetic functions such as counters and adders, while a cascade chain implements wide-input functions such as equality comparators with minimum delay. Carry and cascade chains connect LEs 1 through 10 in an LAB and all LABs in the same MegaLAB structure. Carry Chain The carry chain provides a fast carry-forward function between LEs. The carry-in signal from a lower-order bit drives forward into the higher- order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature allows the APEX II architecture to implement high-speed counters, adders, and comparators of arbitrary width. The Quartus II Compiler can create carry chain logic automatically during the design process, or the designer can create it manually during design entry. Parameterized functions such as DesignWare functions from Synopsys and library of parameterized modules (LPM) functions automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 10 LEs by linking LABs together automatically. For enhanced fitting, a long carry chain skips alternate LABs in a MegaLAB structure. A carry chain longer than one LAB skips either from an even-numbered LAB to the next even- numbered LAB, or from an odd-numbered LAB to the next odd- numbered LAB. For example, the last LE of the first LAB in the upper-left MegaLAB structure carries to the first LE of the third LAB in the MegaLAB structure. Figure 6 shows how an n-bit full adder can be implemented in n + 1 LEs with the carry chain. One portion of the LUT generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the LE. The register can be bypassed for simple adders or used for accumulator functions. Another portion of the LUT and the carry chain logic generates the carry-out signal, which is routed directly to the carry- in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is driven onto the local, MegaLAB, or FastTrack interconnect routing structures.

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Figure 6. APEX II Carry Chain

designer can create it manually during design entry. functions with a wide fan-in. Figure 7. APEX II Cascade Chain

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APEX II Programmable Logic Device Family Data Sheet LE Operating Modes The APEX II LE can operate in one of the following three modes: ■ Normal mode ■ Arithmetic mode ■ Counter mode Each mode uses LE resources differently. In each mode, seven available inputs to the LE—the four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous LE—are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all LE modes. The Quartus II software, in conjunction with parameterized functions such as LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers. If required, the designer can also create special-purpose functions that specify which LE operating mode to use for optimal performance. Figure 8 shows the LE operating modes.

Figure 8. APEX II LE Operating Modes (1) LEs in normal mode support register packing. (2) There are two LAB-wide clock enables per LAB. (3) When using the carry-in in normal mode, the packed register feature is unavailable. (4) A register feedback multiplexer is available on LE1 of each LAB. LEs other than the second LE in a LAB. (6) The LAB-wide synchronous clear and LAB-wide synchronous load affect all registers in a LAB.

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APEX II Programmable Logic Device Family Data Sheet Normal Mode The normal mode is suitable for general logic applications, combinatorial functions, or wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in are inputs to a four-input LUT. The Quartus II Compiler automatically selects the carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal. LEs in normal mode support packed registers. Arithmetic Mode The arithmetic mode is ideal for implementing adders, accumulators, and comparators. An LE in arithmetic mode uses two 3-input LUTs. One LUT computes a three-input function; the other generates a carry output. As shown in Figure 8, the first LUT uses the carry-in signal and two data inputs from the LAB local interconnect to generate a combinatorial or registered output. For example, when implementing an adder, this output is the sum of three signals: DATA1, DATA2, and carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports simultaneous use of the cascade chain. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. The Quartus II software implements parameterized functions that use the arithmetic mode automatically where appropriate; the designer does not need to specify how the carry chain will be used. Counter Mode The counter mode offers clock enable, counter enable, synchronous up/down control, synchronous clear, and synchronous load options. The counter enable and synchronous up/down control signals are generated from the data inputs of the LAB local interconnect. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. Consequently, if any of the LEs in an LAB use the counter mode, other LEs in that LAB must be used as part of the same counter or be used for a combinatorial function. The Quartus II software automatically places any registers that are not used by the counter into other LABs.

APEX II Programmable Logic Device Family Data Sheet The counter mode uses two three-input LUTs: one generates the counter data, and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading, and another AND gate provides synchronous clearing. If the cascade function is used by an LE in counter mode, the synchronous clear or load overrides any signal carried on the cascade chain. The synchronous clear overrides the synchronous load. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. Clear & Preset Logic Control Logic for the register’s clear and preset signals is controlled by LAB-wide signals. The LE directly supports an asynchronous clear function. The Quartus II Compiler can use a NOT-gate push-back technique to emulate an asynchronous preset. Moreover, the Quartus II Compiler can use a programmable NOT-gate push-back technique to emulate simultaneous preset and clear or asynchronous load. However, this technique uses three additional LEs per register. All emulation is performed automatically when the design is compiled. Registers that emulate simultaneous preset and load will enter an unknown state upon power-up or when the chip- wide reset is asserted. In addition to the two clear and preset modes, APEX II devices provide a chip-wide reset pin (DEV_CLRn) that resets all registers in the device. Use of this pin is controlled through an option in the Quartus II software that is set before compilation. The chip-wide reset overrides all other control signals. Registers using an asynchronous preset are preset when the chip- wide reset is asserted; this effect results from the inversion technique used to implement the asynchronous preset. FastTrack Interconnect In the APEX II architecture, connections between LEs, ESBs, and I/O pins are provided by the FastTrack interconnect. The FastTrack interconnect is a series of continuous horizontal and vertical routing channels that traverse the device. This global routing structure provides predictable performance, even in complex designs. In contrast, the segmented routing in FPGAs requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance.

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or ESB in a device. See Figure 9. Figure 9. APEX II Interconnect Structure A row line can be driven directly by LEs, IOEs, or ESBs in that row. drive elements in a different row via the column and row interconnect. IOEs, or ESBs in a particular MegaLAB structure.

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Figure 11. Driving the FastTrack Interconnect

Figure 12. APEX II FastRow Interconnect

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shows the ESB in product-term mode. Table 5. APEX II Routing Scheme

Figure 13. Product-Term Logic in ESB (1) PLL outputs cannot drive data input ports. asynchronous preset. Figure 14 shows the APEX II macrocell.

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Figure 14. APEX II Macrocell clock control. The register can be bypassed for combinatorial operation. operation automatically when synthesizing HDL designs. using a clock also uses the associated clock enable. ESB-wide clock signals are used.

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The programmable register also supports an asynchronous clear function. between the two asynchronous clear signals or choose to not be cleared. shows the ESB control logic when implementing product-terms. Figure 15. ESB Product-Term Mode Control Logic neighboring macrocell to implement fast, complex logic functions. 30 parallel expanders provided by the neighboring macrocells in the ESB.

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Figure 16. APEX II Parallel Expanders two writes, or one read and one write at two different clock frequencies. Figure 17 shows the ESB block diagram.

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be written in 1× mode at port A while being read in 16× mode from port B. signals meet setup and hold time specifications relative to the WE signal. or for fast feedback product-term logic. not need to merge the functions manually. Table 6. Variable Width Configurations for Dual-Port RAM

APEX II Programmable Logic Device Family Data Sheet By combining multiple ESBs, the Quartus II software implements larger memory blocks automatically. For example, two 256 × 16 RAM blocks can be combined to form a 256 x 32 RAM block, and two 512 × 8 RAM blocks can be combined to form a 512 × 16 RAM block. Memory performance does not degrade for memory blocks up to 4,096 words deep. Each ESB can implement a 4,096-word-deep memory; the ESBs are used in parallel, eliminating the need for any external control logic that would increase delays. To create a high-speed memory block more than 4,096-words deep, the Quartus II software automatically combines ESBs with LE control logic. Input/Output Clock Mode The ESB implements input/output clock mode for both dual-port and bidirectional dual-port memory. An ESB using input/output clock mode can use up to two clocks. On each of the two ports, A or B, one clock controls all registers for inputs into the ESB: data input, WREN, read address, and write address. The other clock controls the ESB data output registers. Each ESB port, A or B, also supports independent read clock enable, write clock enable, and asynchronous clear signals. Input/output clock mode is commonly used for applications where the reads and writes occur at the same system frequency, but require different clock enable signals for the input and output registers. Figure 19 shows the ESB in input/output clock mode.

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Figure 19. ESB in Input/Output Clock Mode Note (1) (1) All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset. (2) This configuration is not supported for bidirectional dual-port configuration.

ESB can support up to two single-port mode RAMs. Figure 20. ESB in Single-Port Mode Note (1) (1) All registers can be asynchronously cleared by ESB local interconnect signals, global signals, or chip-wide reset.

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in address 14, the CAM outputs 14 when FA12 is driven into it. filtering. Figure 21 shows the CAM block diagram. Figure 21. CAM Block Diagram combines ESBs and LEs to create larger CAM blocks. don’t-care has no effect on matches.

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APEX II Programmable Logic Device Family Data Sheet If the same data is written into multiple locations in the memory, a CAM block can be used in multiple-match or fast multiple-match modes. The ESB outputs the matched data’s locations as an encoded or unencoded address. In multiple-match mode, it takes two clock cycles to write into a CAM block. For reading, there are 16 outputs from each ESB at each clock cycle. Therefore, it takes two clock cycles to represent the 32 words from a single ESB port. In this mode, encoded and unencoded outputs are available. To implement the encoded version, the Quartus II software adds a priority encoder with LEs. Fast multiple-match is identical to the multiple match mode, however, it only takes one clock cycle to read from a CAM block and generate valid outputs. To do this, the entire ESB is used to represent 16 outputs. In fast multiple-match mode, the ESB can implement a maximum CAM block size of 16 words. A CAM block can be pre-loaded with data during configuration, or it can be written during system operation. In most cases, two clock cycles are required to write each word into CAM. When don’t-care bits are used, a third clock cycle is required. f For more information on CAM, see Application Note 119 (Implementing High-Speed Search Applications with APEX CAM). Driving Signals to the ESB ESBs provide flexible options for driving control signals. Different clocks can be used for the ESB inputs and outputs. Registers can be inserted independently on the data input, data output, read address, write address, WE, and RE signals. The global signals and the local interconnect can drive the WE and RE signals. The global signals, dedicated clock pins, and local interconnects can drive the ESB clock signals. Because the LEs drive the local interconnect, the LEs can control the WE and RE signals and the ESB clock, clock enable, and synchronous clear signals. Figure 24 shows the ESB control signal generation logic.

Figure 24. ESB Control Signal Generation

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APEX II Programmable Logic Device Family Data Sheet Programmable Speed/Power Control APEX II ESBs offer a high-speed mode that supports fast operation on an ESB-by-ESB basis. When high speed is not required, this feature can be turned off to reduce the ESB’s power dissipation by up to 50% . ESBs that run at low power incur a nominal timing delay adder. This Turbo Bit TM option is available for ESBs that implement product-term logic or memory functions. An ESB that is not used will be powered down so that it does not consume DC current. Designers can program each ESB in the APEX II device for either high- speed or low-power operation. As a result, speed-critical paths in the design can run at high speed, while the remaining paths operate at reduced power. I/O Structure The IOE in APEX II devices contains a bidirectional I/O buffer, six registers, and a latch for a complete embedded bidirectional single data rate or DDR IOE. Figure 25 shows the structure of the APEX II IOE. The IOE contains two input registers (plus a latch), two output registers, and two output enable registers. Both input registers and the latch can be used for capturing DDR input. Both output registers can be used to drive DDR outputs. The output enable (OE) register can be used for fast clock-to- output enable timing. The negative edge-clocked OE register is used for DDR SDRAM interfacing. The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins.

Figure 25. APEX II IOE Structure

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Figure 26. Row IOE Connection to the Interconnect Figure 27 shows how a column IOE connects to the interconnect.

Figure 27. Column IOE Connection to the Interconnect routing can improve setup times and OE timing. signals can be driven from internal logic or from the Fast I/O signals. Table 7 lists the peripheral control signal destinations. OE signal is driven by local interconnect.

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bidirectional configuration. Table 7. Peripheral Control Bus Destinations

Figure 28. APEX II IOE in Bidirectional I/O Configuration

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shows the programmable delays for APEX II devices. (1) This delay has four settings: off and three levels of delay. all registers in the IOE must use that preset or clear signal. Table 8. APEX II Programmable Delay Chain

shows an IOE configured for DDR input. Figure 29. APEX II IOE in DDR Input I/O Configuration time. Figure 30 shows the IOE configured for DDR output.

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Figure 30. APEX II IOE in DDR Output I/O Configuration DDR input and DDR output configurations.

APEX II Programmable Logic Device Family Data Sheet Zero Bus Turnaround SRAM Interface Support In addition to DDR SDRAM support, APEX II device I/O pins also support interfacing with ZBT SRAM devices at up to 200 MHz. ZBT SRAM blocks are designed to eliminate dead bus cycles when turning a bidirectional bus around between reads and writes, or writes and reads. ZBT allows for 100% bus utilization because ZBT SRAM can be read or written on every clock cycle. To avoid bus contention, the output clock-to-low-impedance time (t ZX) delay ensures that the tZX is greater than the clock-to-high-impedance time (tXZ). Phase delay control of clocks to the OE/output and input registers using two general-purpose PLLs enable the APEX II device to meet ZBT tCO and tSU times. Programmable Drive Strength The output buffer for each APEX II device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL standard has several levels of drive strength that the user can control. SSTL-3 class I and II, SSTL-2 class I and II, HSTL class I and II, 3.3-V GTL+, PCI, and PCI-X support a minimum setting. The minimum setting is the lowest drive strength that guarantees the I OH/IOL of the standard. Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot. Table 9 shows the possible settings for the I/O standards with drive strength control.

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enable signals) that can be asserted by any of several devices. Table 9. Programmable Drive Strength

APEX II Programmable Logic Device Family Data Sheet Bus Hold Each APEX II device I/O pin provides an optional bus-hold feature. When this feature is enabled for an I/O pin, the bus-hold circuitry weakly holds the signal at its last driven state. By holding the last driven state of the pin until the next input signal is present, the bus-hold feature eliminates the need to add external pull-up or pull-down resistors to hold a signal level when the bus is tri-stated. The bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. This feature can be selected individually for each I/O pin. The bus-hold output will drive no higher than V CCIO to prevent overdriving signals. If the bus-hold feature is enabled, the programmable pull-up option cannot be used. The bus-hold feature should also be disabled if open-drain outputs are used with the GTL+ I/O standard. The bus-hold circuitry weakly pulls the signal level to the last driven state through a resistor with a nominal resistance (R BH) of approximately 7 kΩ . Table 41 on page 74 gives specific sustaining current that will be driven through this resistor and overdrive current that will identify the next driven input level. This information is provided for each VCCIO voltage level. The bus-hold circuitry is active only after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. Programmable Pull-Up Resistor Each APEX II device I/O pin provides an optional programmable pull-up resistor during user mode. When this feature is enabled for an I/O pin, the pull-up resistor (typically 25 kΩ ) weakly holds the output to the VCCIO level of the bank that the output pin resides in. Dedicated Fast I/O Pins APEX II devices incorporate dedicated bidirectional pins for signals with high internal fanout, such as PCI control signals. These pins are called dedicated fast I/O pins (FAST1, FAST2, FAST3, and FAST4) and can drive the four global fast lines throughout the device, ideal for fast clock, clock enable, preset, clear, or high fanout logic signal distribution. The dedicated fast I/O pins have one output register and one OE register, but they do not have input registers. The dedicated fast lines can also be driven by a LE local interconnect to generate internal global signals.

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APEX II Programmable Logic Device Family Data Sheet Advanced I/O Standard Support APEX II device IOEs support the following I/O standards: ■ LVTTL ■ LVCMOS ■ 1.5-V ■ 1.8-V ■ 2.5-V ■ 3.3-V PCI ■ 3.3-V PCI-X ■ LVDS ■ LVPECL ■ PCML ■ HyperTransport ■ GTL+ ■ HSTL class I and II ■ SSTL-3 class I and II ■ SSTL-2 class I and II ■ CTT ■ Differential HSTL

Table 10 describes the I/O standards supported by APEX II devices. see Application Note 117 (Using Selectable I/O Standards in Altera Devices). Table 10. APEX II Supported I/O Standards

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Figure 31. APEX II I/O Banks section in Application Note 166 (Using High-Speed I/O Standards in APEX II Devices) . 1.8 V, or 1.5 V. However, True-LVDS pins do not support the HSTL Class II output. HyperTransport outputs and regular I/O pin standards.

APEX II Programmable Logic Device Family Data Sheet Each bank can support multiple standards with the same VCCIO for input and output pins. Each bank can support one voltage-referenced I/O standard, but it can support multiple I/O standards with the same V CCIO voltage level. For example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs. When the True-LVDS banks are not used for LVDS I/O pins, they support all of the other I/O standards except HSTL Class II output. True-LVDS Interface APEX II devices contain dedicated circuitry for supporting differential standards at speeds up to 1.0 Gbps. APEX II devices have dedicated differential buffers and circuitry to support LVDS, LVPECL, HyperTransport, and PCML I/O standards. Four dedicated high-speed PLLs (separate from the general-purpose PLLs) multiply reference clocks and drive high-speed differential serializer/deserializer channels. In addition, CDS circuitry at each receiver channel corrects any fixed clock- to-data skew. All APEX II devices support 36 input channels, 36 output channels, two dedicated receiver PLLs, and two dedicated transmitter PLLs. The True-LVDS circuitry supports the following standards and applications: ■ RapidIO ■ POS-PHY Level 4 ■ Utopia IV ■ HyperTransport APEX II devices support source-synchronous interfacing with LVDS, LVPECL,PCML, or HyperTransport signaling at up to 1 Gbps. Serial channels are transmitted and received along with a low-speed clock. The receiving device then multiplies the clock by a factor of 1, 2, or 4 to 10. The serialization/deserialization rate can be any number from 1, 2, or 4 to 10 and does not have to equal the clock multiplication value. For example, an 840-Mbps LVDS channel can be received along with an 84-MHz clock. The 84-MHz clock is multiplied by 10 to drive the serial shift register, but the register can be clocked out in parallel at 8- or 10-bits wide at 84 or 105 MHz. See Figures 32 and 33.

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Figure 32. True-LVDS Receiver Diagram Notes (1), (2) (1) Two sets of 18 receiver channels are located in each APEX II device. Each set of 18 channels has one receiver PLL. W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, DDR I/O registers are used. can drive the logic array via a global clock line.

Figure 33. True-LVDS Transmitter Diagram Notes (1), (2) W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, DDR I/O registers are used. feature can be turned on or off independently for each receiver channel. and multi-bit mode, which corrects any fixed clock-to-data skew.

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patterns automatically determine byte alignment (see Table 11). inherent with these topologies, making them possible to use. Table 11. Single-Bit CDS Training Patterns

Figure 34. Multi-Bit CDS Supports N:1 Topology logic. Table 12 shows the possible training patterns for multi-bit CDS. Table 12. Multi-Bit CDS Patterns

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to implement the byte alignment circuitry for this operation. perform serialization/deserialization functions. Table 13. APEX II Flexible-LVDS Timing Specification

3.3 V and is compatible with 3.3-V or 5.0-V systems. Table 14 summarizes APEX II MultiVolt I/O support. inputs are powered by V CCIO. As a result, input levels below the V CCIO setting cannot drive these standards. (3) When V CCIO = 1.8 V, an APEX II device can drive a 1.5-V device with 1.8-V tolerant inputs. (5) APEX II devices can be 5.0-V tolerant with the use of an external series resistor and enabling the PCI clamping diode. considered when selecting a pull-up resistor. they have been designed specifically for any possible power-up sequence. Table 14. APEX II MultiVolt I/O Support Note (1)

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device is configured, APEX II devices operate as specified by the user. The PLLs in APEX II devices are enabled through the Quartus II software. APEX II general-purpose PLL. Figure 35. APEX II General-Purpose PLL Note (1) Table 15. APEX II General-Purpose PLL Features

APEX II Programmable Logic Device Family Data Sheet Note to Figure 35: (1) n represents the prescale divider for the PLL input. m represents the multiplier. k and v represent the different post scale dividers for the two possible PLL outputs. m and k are integers that range from 1 to 160. n and v are integers that range from 1 to 16. Advanced ClockBoost Multiplication & Division APEX II PLLs include circuitry that provides clock synthesis for eight internal outputs and two external outputs using m/(n × output divider) scaling. When a PLL is locked, the locked output clock aligns to the rising edge of the input clock. The closed loop equation for Figure 35 gives an output frequency fclock0 = (m/(n × k))fIN and fclock1 = (m/(n × v))fIN. These equations allow the multiplication or division of clocks by a programmable number. The Quartus II software automatically chooses the appropriate scaling factors according to the frequency, multiplication, and division values entered. A single PLL in an APEX II device allows for multiple user-defined multiplication and division ratios that are not possible even with multiple delay-locked loops (DLLs). For example, if a frequency scaling factor of 3.75 is needed for a given input clock, a multiplication factor of 15 and a division factor of 4 can be entered. This advanced multiplication scaling can be performed with a single PLL, making it unnecessary to cascade PLL outputs. External Clock Outputs APEX II devices have two low-jitter external clocks available for external clock sources. Other devices on the board can use these outputs as clock sources. There are three modes for external clock outputs. ■ Zero Delay Buffer: The external clock output pin is phase aligned with the clock input pin for zero delay. Multiplication, programmable phase shift, and time delay shift are not allowed in this configuration. The MegaWizard interface for altclklock should be used to verify possible clock settings. ■ External Feedback: The external feedback input pin is phase aligned with clock input pin. By aligning these clocks, you can actively remove clock delay and skew between devices. This mode has the same restrictions as zero delay buffer mode. ■ Normal Mode: The external clock output pin will have phase delay relative to the clock input pin. If an internal clock is used in this mode, the IOE register clock will be phase aligned to the input clock pin. Multiplication is allowed with the normal mode.

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APEX II Programmable Logic Device Family Data Sheet ClockShift Circuitry General-purpose PLLs in APEX II devices have ClockShift circuitry that provides programmable phase shift. Users can enter a phase shift (in degrees or time units) that affects all PLL outputs. Phase shifts of 90°, 180°, and 270° can be implemented exactly. Other values of phase shifting, or delay shifting in time units, are allowed with a resolution range of 0.5 ns to 1.0 ns. This resolution varies with frequency input and the user-entered multiplication and division factors. The phase shift ability is only possible on a multiplied or divided clock if the input and output frequency have an integer multiple relationship (i.e., f IN/fOUT or fOUT/fIN must be an integer). Clock Enable Signal APEX II PLLs have a CLKLK_ENA pin for enabling/disabling all device PLLs. When the CLKLK_ENA pin is high, the PLL drives a clock to all its output ports. When the CLKLK_ENA pin is low, the clock0, clock1, and extclock ports are driven by GND and all of the PLLs go out of lock. When the CLKLK_ENA pin goes high again, the PLL relocks. The individual enable port for each PLL is programmable. If more than one PLL is instantiated, each one does not have to use the clock enable. To enable/disable the device PLLs with the CLKLK_ENA pin, the inclocken port on the altclklock instance must be connected to the CLKLK_ENA input pin. Lock Signals The APEX II device PLL circuits support individual LOCK signals. The LOCK signal drives high when the PLL has locked onto the input clock. LOCK remains high as long as the input remains within specification. It will go low if the input is out of specification. A LOCK pin is optional for each PLL used in the APEX II devices; when not used, they are I/O pins. This signal is not available internally; if it is used in the logic array, it must be fed back in with an input pin. SignalTap Embedded Logic Analyzer APEX II devices include device enhancements to support the SignalTap embedded logic analyzer. By including this circuitry, the APEX II device provides the ability to monitor design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry; a designer can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is particularly important for advanced packages such as FineLine BGA packages because adding a connection to a pin during the debugging process can be difficult after a board is designed and manufactured.

performed before or after configuration, but not during configuration. operation of the device with the SignalTap embedded logic analyzer. APEX II devices support the JTAG instructions shown in Table 16. (1) Bus hold and weak pull-up features override the high-impedance state of HIGHZ, CLAMP, and EXTEST. Table 16. APEX II JTAG Instructions normal device operation, and permits an initial data pattern to be output at the device pins. Also used by the SignalTap embedded logic analyzer. pattern at the output pins and capturing test results at the input pins. allowing the USERCODE to be serially shifted out of TDO. to be serially shifted out of TDO. operation, while tri-stating all of the I/O pins. Monitors internal device operation with the SignalTap embedded logic analyzer.

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(1) The most significant bit (MSB) is on the left. (2) The IDCODE’s least significant bit (LSB) is always 1. Figure 36 shows the timing requirements for the JTAG signals. Table 17. APEX II JTAG Boundary-Scan Register Length Table 18. 32-Bit APEX II Device IDCODE

Figure 36. APEX II JTAG Waveforms Table 19. APEX II JTAG Timing Parameters & Values

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Figure 37. Multiple test patterns can be used to configure devices during ■ Power supply transients can affect AC measurements. ■ Threshold tests must not be performed under AC conditions. observable noise immunity can result. Figure 37. APEX II AC Test Conditions APEX II devices are offered in both commercial and industrial grades.

Table 20. APEX II Device Absolute Maximum Ratings Notes (1), (2) Table 21. APEX II Device Recommended Operating Conditions

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Table 22. APEX II Device DC Operating Conditions Note (7) Table 23. LVTTL Specifications Table 24. LVCMOS Specifications

Table 25. 2.5-V I/O Specifications Note (10) Table 26. 1.8-V I/O Specifications Table 27. 1.5-V I/O Specifications

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Table 28. 3.3-V PCI Specifications Table 29. PCI-X Specifications Table 30. GTL+ I/O Specifications

Table 31. SSTL-2 Class I Specifications Table 32. SSTL-2 Class II Specifications Table 33. SSTL-3 Class I Specifications

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Table 34. SSTL-3 Class II Specifications Table 35. 3.3-V AGP 2× Specifications Table 36. 3.3-V AGP 1× Specifications

Table 37. 1.5-V HSTL Class I Specifications Table 38. 1.5-V HSTL Class II Specifications Table 39. 1.5-V Differential HSTL Specifications

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(1) See the Operating Requirements for Altera Devices Data Sheet . operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. currents less than 100 mA and periods shorter than 20 ns. (4) Maximum V CC rise time is 100 ms, and V CC must rise monotonically. (5) V CCIO maximum and minimum conditions for LVPECL, LVDS, RapidIO, and PCML are shown in parentheses. (8) This value is specified for normal device operation. The value may vary during power-up. (10) Drive strength is programmable according to values in Table 9 on page 48. (11) V REF specifies the center point of the switching range. Table 40. CTT I/O Specifications Table 41. Bus Hold Parameters

0 V < VIN <

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Table 42. 3.3-V LVDS I/O Specifications Table 43. 3.3-V PCML Specifications

(1) Maximum V OD is measured under static conditions. Table 44. LVPECL Specifications Note (2) Table 45. HyperTransport Specifications

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Figure 40. APEX II Maximum Input & Output Pin Capacitance Table 46. APEX II Device Capacitance

APEX II Programmable Logic Device Family Data Sheet Timing Model The high-performance FastTrack and MegaLAB interconnect routing structures ensure predictable performance, and accurate simulation and timing analysis. In contrast, the unpredictable performance of FPGAs is caused by their segmented connection scheme. All specifications are always representative of worst-case supply voltage and junction temperature conditions. All output-pin-timing specifications are reported for maximum drive strength. Figure 41 shows the f MAX timing model for APEX II devices. These parameters can be used to estimate fMAX for multiple levels of logic. However, the Quartus II software timing analysis provides more accurate timing information because the Quartus II software usually has more up- to-date timing information than the data sheet until the timing model is final. Also, the Quartus II software can model delays caused by loading and distance effects more accurately than by using the numbers in this data sheet.

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Figure 41. fMAX Timing Model

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Figure shows the dual-port RAM timing microparameter waveform. Table 48. APEX II fMAX ESB Timing Parameters

Figure 43. Dual-Port RAM Timing Microparameter Waveform Table 49. APEX II fMAX Routing Delays

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Table 50. APEX II Minimum Pulse Width Timing Parameters Table 51. APEX II External Timing Parameters Note (1)

Table 52. EP2A15 fMAX LE Timing Parameters Table 53. EP2A15 fMAX ESB Timing Parameters

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Table 54. EP2A15 fMAX Routing Delays Table 55. EP2A15 Minimum Pulse Width Timing Parameters Table 56. EP2A25 fMAX LE Timing Parameters

Table 57. EP2A25 fMAX ESB Timing Parameters Table 58. EP2A25 fMAX Routing Delays

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Table 59. EP2A25 Minimum Pulse Width Timing Parameters Table 60. EP2A40 fMAX LE Timing Parameters

Table 61. EP2A40 fMAX ESB Timing Parameters Table 62. EP2A40 fMAX Routing Delays

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Table 63. EP2A40 Minimum Pulse Width Timing Parameters Table 64. EP2A70 fMAX LE Timing Parameters

Table 65. EP2A70 fMAX ESB Timing Parameters Table 66. EP2A70 fMAX Routing Delays

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Table 67. EP2A70 Minimum Pulse Width Timing Parameters Table 68. EP2A15 External Timing Parameters for Row I/O Pins

Table 69. EP2A15 External Timing Parameters for Column I/O Pins Table 70. EP2A25 External Timing Parameters for Row I/O Pins

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Table 71. EP2A25 External Timing Parameters for Column I/O Pins Table 72. EP2A40 External Timing Parameters for Row I/O Pins

Table 73. EP2A40 External Timing Parameters for Column I/O Pins Table 74. EP2A70 External Timing Parameters for Row I/O Pins

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Table 75. EP2A70 External Timing Parameters for Column I/O Pins

Table 76. APEX II Selectable I/O Standards Input Adder Delays

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released via a future interactive power estimator on the Altera web site. Library for pin-out information. Table 77. APEX II Selectable I/O Standards Output Adder Delays

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San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified a s trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Alte ra Corporation in the U.S. and other countries. All other product or service names are the property of the ir respective holders. Altera products are protected under numerous U.S. and foreign patents and pendin g applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services APEX II Programmable Logic Device Family Data Sheet

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The information contained in the APEX II Programmable Logic Device Family Data Sheet version 3.0 supersedes information published in previous versions. The following changes were made to the APEX II Programmable Logic Device Family Data Sheet version 3.0: ■ Changed the value from 624 to 400 Mbps throughout the document. ■ Deleted the pin count (612) for the EP2A25 device in the 1,020-pin FineLine BGA package (see Table 3). ■ Added Table 13. ■ Changed the maximum value of 3.6 to 2.4 in Table 20. ■ Updated Tables 60 through 67 and Tables 72 through 75. ■ Updated Figures 25, 28, and 30. ■ Added Note (1) to Figure 13. ■ Added Figure 43.