EP220

EP220 ALTERA | Alldatasheet

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Technical content

Features

n High-performance, low-power Erasable Programmable Logic Devices (EPLDs) with 8 macrocells – Combinatorial speeds as low as 7.5 ns – Counter frequencies of up to 100 MHz – Pipelined data rates of up to 115 MHz – Maximum 5.5-ns Clock-to-output time; minimum 4.5-ns setup time n Replacement or upgrade for 16V8/20V8 PAL and GAL devices n Up to 18 inputs (10 dedicated inputs) in EP220, 22 inputs (14 dedicated inputs) in EP224; up to 8 outputs in both EP220 and EP224 n Macrocells independently programmable for both registered and combinatorial logic n Programmable inversion control supporting active-high or active- low outputs n Low power consumption – Typical I CC = 90 mA at 25 MHz (for -7A speed grades) – Quarter-power mode (I CC = 40 mA) – Programmable zero-power mode with typical I CC = 50 m A (for -10A and -12 speed grades) n Programmable Security Bit for total protection of proprietary designs n Low output skew for Clock driver applications n 100 generically tested to provide 100 programming yield n Software and programming support from Altera and a wide range of third-party tools n Available in windowed ceramic and one-time-programmable (OTP) plastic packages – 20-pin plastic J-lead package (PLCC) – 20-pin ceramic and plastic dual in-line packages (CerDIP and PDIP) – 24-pin PDIP – 28-pin PLCC General

Description

The EPROM-based EP220 and EP224 devices feature a flexible I/O architecture and implement 150 usable (300 available) gates of custom user logic functions. EP220 and EP224 devices can be used as upgrades for high-speed bipolar programmable logic devices (PLDs) or for 74-series LS and CMOS (SSI and MSI) logic devices in high-performance microcomputer systems.

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EP220 & EP224 Classic EPLDs Compared to bipolar devices of equivalent speed, the EP220 and EP224 offer lower power consumption, faster input-to-non- registered-output delay ( t PD ) in combinatorial mode, and higher counter frequencies in registered applications. This added performance supports faster state machine designs compared to bipolar devices, and provides additional timing margin for existing designs. The EP220 and EP224 are ideal for high-volume manufacturing of high-performance systems. These devices improve performance and decrease system noise, power consumption, and heat generation. Functional Figure 1 shows block diagrams of the EP220 and EP224 device architectures. The EP220 has 10 dedicated inputs and 8 I/O pins; the EP224 has 14 dedicated inputs and 8 I/O pins.

Figure 1. EP220 & EP224 Block Diagram Numbers in parentheses refer to the pin-out number. input, output, or bidirectional pin.

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inputs for the EP220, 44 inputs for the EP224—and I/O feedback signal. Figure 2. EP220 & EP224 Macrocell combinatorial feedback signal from the I/O pin to feed the logic array.

product terms can be programmed accordingly. compatible devices can be programmed into EP220 or EP224 devices. with EP220 and EP224 devices. Table 1. EP220- and EP224-Compatible Devices (Part 1 of 4)

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Table 1. EP220- and EP224-Compatible Devices (Part 2 of 4)

Table 1. EP220- and EP224-Compatible Devices (Part 3 of 4)

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EP220 and EP224 devices are fully functionally tested and guaranteed. Table 1. EP220- and EP224-Compatible Devices (Part 4 of 4)

Figure 3. EP220 & EP224 AC Test Circuits

1995 Data Book

Altera and third-party programming hardware support. parentheses are for the EP224 device.

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Figure 4. EP220 & EP224 I Figure 5. EP220 & EP224 Output Drive Characteristics

EP220 & EP224 Classic EPLDs Absolute Maximum Ratings Note (1) Recommended Operating Conditions DC Operating Conditions Note (5) Capacitance Notes (5), (8) Symbol Parameter Conditions Min Max Unit V CC Supply voltage Note (2) –2.0 7.0 V V I DC input voltage Notes (2) (3) –0.5 V CC + 0.5 V T STG Storage temperature –65 150 C T AMB Ambient temperature Note (4) –10 85 C Symbol Parameter Conditions Min Max Unit V CC Supply voltage 5.0-V operation 4.75 5.25 V V IN Input voltage 0V CC V V O Output voltage 0V CC V T A Operating temperature For commercial use 0 70 C T A Operating temperature For industrial use –40 85 C t R Input rise time 500 ns t F Input fall time 500 ns Symbol Parameter Conditions Min Max Unit V IH High-level input voltage Note (6) 2.0 V CC + 0.3 V V IL Low-level input voltage Note (6) –0.3 0.8 V VOH High-level TTL output voltage I OH = –4.0 mA DC, VCC = Min. 2.4 V VOL Low-level output voltage -7A, -7, -10: I OL = 24 mA DC, VCC = Min. -10A, -12: IOL = 12 mA DC, VCC = Min. 0.45 V II Input leakage current V CC = Max., GND < VIN < VCC –10 10 mA IOZ Tri-state output leakage current V CC = Max., GND < VOUT < VCC –10 10 mA ISC Output short-circuit current V CC = Max., VOUT = 0.5 V, Note (7) –30 120 mA Symbol Parameter Conditions Min Max Unit C IN Input capacitance V IN = 0 V, f = 1.0 MHz 6 pF C OUT I/O capacitance V OUT = 0 V, f = 1.0 MHz 8 pF C CLK Clock pin capacitance V OUT = 0 V, f = 1.0 MHz 8 pF C VPP VPP pin capacitance V PP on pin 11 (EP220) and pin 13 (EP224), f = 1.0 MHz 10 pF

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EP220 & EP224 Classic EPLDs ICC Supply Current: EP220-7A & EP224-7A Note (5) ICC Supply Current: EP220-10A, EP224-10A, EP220-12 & EP224-12 Note (5) ICC Supply Current: EP220-7, EP224-7, EP220-10 & EP224-10 Note (5) Notes to tables: (1) See Operating Requirements for Altera Devices in the Altera 1995 Data Book. (2) Voltage with respect to ground. (3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions. (4) Under bias. Extended temperature versions are also available. (5) Operating conditions: T A = 0° C to 70° C, VCC = 5.0 V – 5% for commercial use. TA = –40° C to 85° C, VCC = 5.0 V – 10% for industrial use. (6) Absolute values with respect to device GND; all over- and undershoots due to system or tester noise are included. (7) For -7A, -10A, -12 speed grades for EP220 and EP224 devices: maximum DC I OL (all 8 outputs) = 64 mA. For -7, -10 speed grades for EP220 and EP224 devices: test 1 output at a time; test duration should not exceed 1 s. (8) These values are measured during initial characterization. V CC = Max., VIN = VCC or GND. (9) Measured with a device programmed as an 8-bit counter. (10) When the Turbo Bit is not set (non-turbo mode), an EP220 or EP224 device enters standby mode if no logic transitions occur for approximately 75 ns after the last transition. Symbol Parameter Conditions Min Max Unit ICC3 VCC supply current f IN = 25 MHz, Note (9) 90 mA fIN = 100 MHz, Note (9) 115 mA Symbol Parameter Conditions Min Max Unit ICC1 VCC supply current (non-turbo) Standby mode, Note (9) 500 mA ICC2 VCC supply current (non-turbo) V CC = Max., VIN = VCC or GND, no load, fIN = 1 MHz, Notes (9), (10) 5m A ICC3 VCC supply current (turbo, active) fIN = 15 MHz, Note (9) 50 mA fIN = 80 MHz, Note (9) 60 mA Symbol Parameter Conditions Min Max Unit ICC1 VCC supply current (standby) f IN = 25 MHz, Note (9) 90 mA fIN = 74 MHz, Note (9) 105 mA ICC3 VCC supply current (active) f IN = 25 MHz, Note (9) 115 mA fIN = 74 MHz, Note (9) 135 mA

EP220 & EP224 Classic EPLDs AC Operating Conditions: -7A, -10A, & -12 Speed Grades Note (1) Notes to tables: (1) Operating conditions: V CC = 5 V – 5% , TA = 0° C to 70° C for commercial use. VCC = 5 V – 5% , TA = –40° C to 85° C for industrial use. (2) If the device enters standby mode and remains inactive for approximately 75 ns, increase the time by the amount shown. For EP220-10A, EP220-12, and EP224-10A, EP224-12 devices only. (3) Measured with all outputs switching. (4) The t PZX and tPXZ parameters are measured at – 0.5 V from steady-state voltage that is driven by the specified output load. The tPXZ parameter is measured with CL = 5 pF and with all eight outputs switching. Combinatorial Mode EP220-7A EP224-7A EP220-10A EP224-10A EP220-12 EP224-12 Non-Turbo Adder Symbol Parameter Min Max Min Max Min Max Note (2) Units tPD1 Input to non-registered output, Note (3) 7.5 10 12 20 ns tPD2 I/O to non-registered output, Note (3) 7.5 10 12 20 ns tPZX Input or I/O to output enable, Note (4) 91 2 1 2 2 0 n s tPXZ Input or I/O to output disable, Note (4) 91 0 1 2 2 0 n s tOSR Register-mode output to output skew 300 - - - ps tOSC Combinatorial-mode output to output skew 400 - - - ps Synchronous Clock Mode EP220-7A EP224-7A EP220-10A EP224-10A EP220-12 EP224-12 Non-Turbo Adder Symbol Parameter Min Max Min Max Min Max Note (2) Units fMAX Maximum frequency (pipelined), no feedback, Note (3) 115 111 90.9 - MHz fCNT1 Maximum counter frequency, external feedback, Note (3) 100 80 66 - MHz fCNT2 Maximum counter frequency, internal feedback, Note (3) 115 100 83.3 - MHz tSU1 Input or I/O setup time to global clock 4.5 7 9 20 ns tH Input or I/O hold time from global clock 0 0 0 0 ns tCO1 Global clock to output delay, Note (3) 5.5 5.5 6 0 ns tCO2 Global clock to output delay through combinatorial macrocell 10 13 15 20 ns tCNT Minimum global clock period, Note (3) 10 10 12 20 ns tCL Clock low time 4 4 5 0 ns tCH Clock high time 4 4 5 0 ns tCP Clock period 10 9 11 0 ns

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EP220 & EP224 Classic EPLDs AC Operating Conditions: -7 & -10 Speed Grades Note (1) Notes to tables: (1) Operating conditions: V CC = 5 V – 5% , TA = 0° C to 70° C for commercial use. (2) Measured with three I/O outputs switching. (3) The t PZX and tPXZ parameters are measured at – 0.5 V from steady-state voltage that is driven by the specified output load. The tPXZ parameter is measured with CL = 5 pF and with all eight outputs switching. Combinatorial Mode EP220-7 EP224-7 EP220-10 EP224-10 Symbol Parameter Min Max Min Max Units tPD1 Input or I/O to non-registered output, inversion on, Note (2) 7.5 10 ns tPD2 Input or I/O to non-registered output, inversion off, Note (2) 8.5 10 ns tPZX Input or I/O to output enable, Note (3) 91 0 n s tPXZ Input or I/O to output disable, Note (3) 91 0 n s tOSR Register mode output-to-output skew 300 300 ps tOSC Combinatorial mode output-to-output skew 400 400 ps Synchronous Clock Mode EP220-7 EP224-7 EP220-10 EP224-10 Symbol Parameter Min Max Min Max Units fMAX Maximum frequency (pipelined), no feedback, Note (2) 100 62.5 MHz fCNT1 Maximum counter frequency, external feedback, Note (2) 74 58.8 MHz fCNT2 Maximum counter frequency, internal feedback, Note (2) 100 60.6 MHz tSU1 Input or I/O setup time to global clock 7 10 ns tH Input or I/O hold time from global clock 0 0 ns tCO1 Global clock to output delay, Note (2) 6.5 7 ns tCO2 Global clock to output delay through combinatorial macrocell 11 13 ns tCNT Minimum global clock period, Note (2) 10 16.5 ns tCL Clock low time 4 7 ns tCH Clock high time 4 7 ns tCP Clock period 10 16 ns

orders for products or services. Copyright Ó 1996 Altera Corporation. All rights reserved.

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that date, only Altera ordering codes will be accepted. Table 2. EP220 & EP224 Availability