EP20K1000EFI672-2X ALTERA | Alldatasheet
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Table 1. APEX 20K Device Features Note (1)
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APEX 20K Programmable Logic Device Family Data Sheet Note to Tables 1 and 2: (1) The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to 57,000 additional gates. Additional
Features
■ Designed for low-power operation – 1.8-V and 2.5-V supply voltage (see Table 3) –M u l t i V o l tTM I/O interface support to interface with 1.8-V, 2.5-V, 3.3-V, and 5.0-V devices (see Table 3) – ESB offering programmable power-saving mode Note to Table 3: (1) APEX 20KE devices can be 5.0-V tole rant by using an external resistor. Table 2. Additional APEX 20K Device Features Note (1) Table 3. APEX 20K Supply Voltages
APEX 20K Programmable Logic Device Family Data Sheet ■ Flexible clock management circuitry with up to four phase-locked loops (PLLs) – Built-in low-skew clock tree – Up to eight global clock signals – ClockLock ® feature reducing clock delay and skew – ClockBoost ® feature providing clock multiplication and division – ClockShift TM programmable clock phase and delay shifting ■ Powerful I/O features – Compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits – Support for high-speed external memories, including DDR SDRAM and ZBT SRAM (ZBT is a trademark of Integrated Device Technology, Inc.) – Bidirectional I/O performance ( t CO + tSU) up to 250 MHz – LVDS performance up to 840 Mbits per channel – Direct connection from I/O pins to local interconnect providing fast t CO and tSU times for complex logic – MultiVolt I/O interface support to interface with 1.8-V, 2.5-V, 3.3-V, and 5.0-V devices (see Table 3) – Programmable clamp to V CCIO – Individual tri-state output enable control for each pin – Programmable output slew-rate control to reduce switching noise – Support for advanced I/O stan dards, including low-voltage differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stub- series terminated logic (SSTL-3 and SSTL-2), Gunning transceiver logic plus (GTL+), and high-speed terminated logic (HSTL Class I) – Pull-up on I/O pins before and during configuration ■ Advanced interconnect structure – Four-level hierarchical FastTrack ® Interconnect structure providing fast, predictable interconnect delays – Dedicated carry chain that implem ents arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – Dedicated cascade chain th at implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) – Interleaved local interconnect allows one LE to drive 29 other LEs through the fast local interconnect ■ Advanced packaging options – Available in a variety of packages with 144 to 1,020 pins (see Tables 4 through 7) – FineLine BGA ® packages maximize board space efficiency ■ Advanced software support – Software design support and automatic place-and-route provided by the Altera® Quartus® II development system for
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Table 4. APEX 20K QFP, BGA & PGA Package Options & I/O Count Notes (1), (2)
(1) I/O counts include dedicated input and clock pins. Package Information Data Sheet for detailed package size information. Table 5. APEX 20K FineLine BGA Package Options & I/O Count Notes (1), (2) Table 6. APEX 20K QFP, BGA & PGA Package Sizes Table 7. APEX 20K FineLine BGA Package Sizes
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APEX 20K Programmable Logic Device Family Data Sheet General
Description
APEXTM 20K devices are the first PLDs designed with the MultiCore architecture, which combines the strengths of LUT-based and product- term-based devices with an enhanced memory structure. LUT-based logic provides optimized performance and efficiency for data-path, register- intensive, mathematical, or digital signal processing (DSP) designs. Product-term-based logic is optimized for complex combinatorial paths, such as complex state machines. LUT- and product-term-based logic combined with memory functions and a wide variety of MegaCore and AMPP functions make the APEX 20K device architecture uniquely suited for system-on-a-programmable-chip designs. Applications historically requiring a combination of LUT-, product-term-, and memory-based devices can now be integrated into one APEX 20K device. APEX 20KE devices are a superset of APEX 20K devices and include additional features such as advanced I/O standard support, CAM, additional global clocks, and enhanced ClockLock clock circuitry. In addition, APEX 20KE devices extend the APEX 20K family to 1.5 million gates. APEX 20KE devices are denoted with an “E” suffix in the device name (e.g., the EP20K1000E device is an APEX 20KE device). Table 8 compares the features included in APEX 20K and APEX 20KE devices.
Table 8. Comparison of APEX 20K & APEX 20KE Features
156 Mbps (in -1 speed grade devices)
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APEX 20K Programmable Logic Device Family Data Sheet All APEX 20K devices are reconfigurable and are 100% tested prior to shipment. As a result, test vectors do not have to be generated for fault coverage purposes. Instead, the designer can focus on simulation and design verification. In addition, the designer does not need to manage inventories of different application-specific integrated circuit (ASIC) designs; APEX 20K devices can be configured on the board for the specific functionality required. APEX 20K devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers in-system programmability (ISP)-capable EPC1, EPC2, and EPC16 configuration devices, which configure APEX 20K devices via a serial data stream. Moreover, APEX 20K devices contain an optimized interface that permits microprocessors to configure APEX 20K devices serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat APEX 20K devices as memory and configure the device by writing to a virtual memory location, making reconfiguration easy. After an APEX 20K device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications. APEX 20K devices are supported by the Altera Quartus II development system, a single, integrated package that offers HDL and schematic design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, SignalTap logic analysis, and device configuration. The Quartus II software runs on Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations. The Quartus II software provides NativeLink interfaces to other industry- standard PC- and UNIX workstation-based EDA tools. For example, designers can invoke the Quartus II software from within third-party design tools. Further, the Quartus II software contains built-in optimized synthesis libraries; synthesis tools can use these libraries to optimize designs for APEX 20K devices. For example, the Synopsys Design Compiler library, supplied with the Quartus II development system, includes DesignWare functions optimized for the APEX 20K architecture.
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dedicated clock pins, for a total of four dedicated clock pins. the local interconnect. Figure 2 shows the MegaLAB structure. Figure 2. MegaLAB Structure
transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs. performance. Figure 3 shows the APEX 20K LAB. Figure 3. LAB Structure can drive two local interconnect areas.
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when implementing counters, they can also be used with other functions. wide clock signals are used. distribution. Figure 4 shows the LAB control signal generation circuit. Figure 4. LAB Control Signal Generation (1) APEX 20KE devices have four dedicated clocks. (3) The SYNCCLR signal can be generated by the local interconnect or global signals.
interconnect, and FastTrack Interconnect routing structures. See Figure 5. Figure 5. APEX 20K Logic Element LUT drives the outputs of the LE.
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APEX 20K Programmable Logic Device Family Data Sheet Each LE has two outputs that drive the local, MegaLAB, or FastTrack Interconnect routing structure. Each output can be driven independently by the LUT’s or register’s output. For example, the LUT can drive one output while the register drives the other output. This feature, called register packing, improves device utilization because the register and the LUT can be used for unrelated functions. The LE can also drive out registered and unregistered versions of the LUT output. The APEX 20K architecture provides two types of dedicated high-speed data paths that connect adjacent LEs without using local interconnect paths: carry chains and cascade chains. A carry chain supports high-speed arithmetic functions such as counters and adders, while a cascade chain implements wide-input functions such as equality comparators with minimum delay. Carry and cascade chains connect LEs 1 through 10 in an LAB and all LABs in the same MegaLAB structure. Carry Chain The carry chain provides a very fast carry-forward function between LEs. The carry-in signal from a lower-order bit drives forward into the higher- order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature allows the APEX 20K architecture to implement high-speed counters, adders, and comparators of arbitrary width. Carry chain logic can be created automatically by the Quartus II software Compiler during design processing, or manually by the designer during design entry. Parameterized functions such as library of parameterized modules (LPM) and DesignWare functions automatically take advantage of carry chains for the appropriate functions. The Quartus II software Compiler creates carry chains longer than ten LEs by linking LABs together automatically. For enhanced fitting, a long carry chain skips alternate LABs in a MegaLAB ™ structure. A carry chain longer than one LAB skips either from an even-numbered LAB to the next even- numbered LAB, or from an odd-numbered LAB to the next odd- numbered LAB. For example, the last LE of the first LAB in the upper-left MegaLAB structure carries to the first LE of the third LAB in the MegaLAB structure. Figure 6 shows how an n-bit full adder can be implemented in n + 1 LEs with the carry chain. One portion of the LUT generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the LE. The register can be bypassed for simple adders or used for accumulator functions. Another portion of the LUT and the carry chain logic generates the carry-out signal, which is routed directly to the carry- in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is driven onto the local, MegaLAB, or FastTrack Interconnect routing structures.
Figure 6. APEX 20K Carry Chain
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processing, or manually by the designer during design entry. functions with a wide fan-in. Figure 7. APEX 20K Cascade Chain
APEX 20K Programmable Logic Device Family Data Sheet LE Operating Modes The APEX 20K LE can operate in one of the following three modes: ■ Normal mode ■ Arithmetic mode ■ Counter mode Each mode uses LE resources differently. In each mode, seven available inputs to the LE—the four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous LE—are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all LE modes. The Quartus II software, in conjunction with parameterized functions such as LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers. If required, the designer can also create special-purpose functions that specify which LE operating mode to use for optimal performance. Figure 8 shows the LE operating modes.
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Figure 8. APEX 20K LE Operating Modes (1) LEs in normal mode support register packing. (2) There are two LAB-wide clock enables per LAB. (3) When using the carry-in in normal mode, the packed register feature is unavailable. (4) A register feedback multiplexer is available on LE1 of each LAB. LEs other than the second LE in an LAB. (6) The LAB-wide synchronous clear and LAB wide sy nchronous load affect all registers in an LAB.
APEX 20K Programmable Logic Device Family Data Sheet Normal Mode The normal mode is suitable for general logic applications, combinatorial functions, or wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in are inputs to a four-input LUT. The Quartus II software Compiler automatically selects the carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal. LEs in normal mode support packed registers. Arithmetic Mode The arithmetic mode is ideal for implementing adders, accumulators, and comparators. An LE in arithmetic mode uses two 3-input LUTs. One LUT computes a three-input function; the other generates a carry output. As shown in Figure 8, the first LUT uses the carry-in signal and two data inputs from the LAB local interconnect to generate a combinatorial or registered output. For example, when implementing an adder, this output is the sum of three signals: DATA1, DATA2, and carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports simultaneous use of the cascade chain. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. The Quartus II software implements parameterized functions that use the arithmetic mode automatically where appropriate; the designer does not need to specify how the carry chain will be used. Counter Mode The counter mode offers clock enable, counter enable, synchronous up/down control, synchronous clear, and synchronous load options. The counter enable and synchronous up/down control signals are generated from the data inputs of the LAB local interconnect. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. Consequently, if any of the LEs in an LAB use the counter mode, other LEs in that LAB must be used as part of the same counter or be used for a combinatorial function. The Quartus II software automatically places any registers that are not used by the counter into other LABs.
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APEX 20K Programmable Logic Device Family Data Sheet The counter mode uses two three-input LUTs: one generates the counter data, and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading, and another AND gate provides synchronous clearing. If the cascade function is used by an LE in counter mode, the synchronous clear or load overrides any signal carried on the cascade chain. The synchronous clear overrides the synchronous load. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. Clear & Preset Logic Control Logic for the register’s clear and preset signals is controlled by LAB-wide signals. The LE directly supports an asynchronous clear function. The Quartus II software Compiler can use a NOT-gate push-back technique to emulate an asynchronous preset. Moreover, the Quartus II software Compiler can use a programmable NOT-gate push-back technique to emulate simultaneous preset and clear or asynchronous load. However, this technique uses three additional LEs per register. All emulation is performed automatically when the design is compiled. Registers that emulate simultaneous preset and load will enter an unknown state upon power-up or when the chip-wide reset is asserted. In addition to the two clear and preset modes, APEX 20K devices provide a chip-wide reset pin (DEV_CLRn) that resets all registers in the device. Use of this pin is controlled through an option in the Quartus II software that is set before compilation. The chip-wide reset overrides all other control signals. Registers using an asynchronous preset are preset when the chip-wide reset is asserted; this effect results from the inversion technique used to implement the asynchronous preset. FastTrack Interconnect In the APEX 20K architecture, connections between LEs, ESBs, and I/O pins are provided by the FastTrack Interconnect. The FastTrack Interconnect is a series of continuous horizontal and vertical routing channels that traverse the device. This global routing structure provides predictable performance, even in complex designs. In contrast, the segmented routing in FPGAs requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. The FastTrack Interconnect consists of row and column interconnect channels that span the entire device. The row interconnect routes signals throughout a row of MegaLAB structures; the column interconnect routes signals throughout a column of MegaLAB structures. When using the row and column interconnect, an LE, IOE, or ESB can drive any other LE, IOE, or ESB in a device. See Figure 9.
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Figure 10. FastTrack Connection to Local Interconnect
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Figure 12. APEX 20KE FastRow Interconnect
(1) This connection is supported in APEX 20KE devices only. drive the ESB control signals. shows the ESB in product-term mode. Table 9. APEX 20K Routing Scheme
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Figure 13. Product-Term Logic in ESB (1) APEX 20KE devices have four dedicated clocks. asynchronous preset. Figure 14 shows the APEX 20K macrocell.
Figure 14. APEX 20K Macrocell clock control. The register can be bypassed for combinatorial operation. operation automatically when synthesizing HDL designs. using a clock also uses the associated clock enable. ESB-wide clock signals are used.
32 Signals
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The programmable register also supports an asynchronous clear function. between the two asynchronous clear signals or choose to not be cleared. shows the ESB control logic when implementing product-terms. Figure 15. ESB Product-Term Mode Control Logic (1) APEX 20KE devices have four dedicated clocks. neighboring macrocell to implement fast, complex logic functions. parallel expanders provided by the neighboring macrocells in the ESB. shows the APEX 20K parallel expanders.
Figure 16. APEX 20K Parallel Expanders Figure 17. ESB Block Diagram
32 Signals from
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APEX 20K Programmable Logic Device Family Data Sheet ESBs can implement synchronous RAM, which is easier to use than asynchronous RAM. A circuit using asynchronous RAM must generate the RAM write enable (WE) signal, while ensuring that its data and address signals meet setup and hold time specifications relative to the WE signal. In contrast, the ESB’s synchronous RAM generates its own WE signal and is self-timed with respect to the global clock. Circuits using the ESB’s self- timed RAM must only meet the setup and hold time specifications of the global clock. ESB inputs are driven by the adjacent local interconnect, which in turn can be driven by the MegaLAB or FastTrack Interconnect. Because the ESB can be driven by the local interconnect, an adjacent LE can drive it directly for fast memory access. ESB outputs drive the MegaLAB and FastTrack Interconnect. In addition, ten ESB outputs, nine of which are unique output lines, drive the local interconnect for fast connection to adjacent LEs or for fast feedback product-term logic. When implementing memory, each ESB can be configured in any of the following sizes: 128 × 16, 256 × 8, 512 × 4, 1,024 × 2, or 2,048 × 1. By combining multiple ESBs, the Quartus II software implements larger memory blocks automatically. For example, two 128× 16 RAM blocks can be combined to form a 128 × 32 RAM block, and two 512 × 4 RAM blocks can be combined to form a 512× 8 RAM block. Memory performance does not degrade for memory blocks up to 2,048 words deep. Each ESB can implement a 2,048-word-deep memory; the ESBs are used in parallel, eliminating the need for any external control logic and its associated delays. To create a high-speed memory block that is more than 2,048 words deep, ESBs drive tri-state lines. Each tri-state line connects all ESBs in a column of MegaLAB structures, and drives the MegaLAB interconnect and row and column FastTrack Interconnect throughout the column. Each ESB incorporates a programmable decoder to activate the tri-state driver appropriately. For instance, to implement 8,192-word-deep memory, four ESBs are used. Eleven address lines drive the ESB memory, and two more drive the tri-state decoder. Depending on which 2,048-word memory page is selected, the appropriate ESB driver is turned on, driving the output to the tri-state line. The Quartus II software automatically combines ESBs with tri-state lines to form deeper memory blocks. The internal tri-state control logic is designed to avoid internal contention and floating lines. See Figure 18.
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frequencies. Figure 20 shows the ESB in read/write clock mode. Figure 20. ESB in Read/Write Clock Mode Note (1) (1) All registers can be cleared asynchrono usly by ESB local interconnect signals, global signals, or the chip-wide reset. (2) APEX 20KE devices have four dedicated clocks.
signals also control the reading and writing of registers independently. the ESB in input/output clock mode. Figure 21. ESB in Input/Output Clock Mode Note (1) (1) All registers can be cleared asynchrono usly by ESB local interconnect signals, global signals, or the chip-wide reset. (2) APEX 20KE devices have four dedicated clocks. simultaneous reads and writes are not required. See Figure 22.
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Figure 22. ESB in Single-Port Mode Note (1) (1) All registers can be asynchronously cl eared by ESB local interconnect signals, global signals, or the chip-wide reset. (2) APEX 20KE devices have four dedicated clocks. outputs 14 when FA12 is driven into it.
Figure 23. APEX 20KE CAM Block Diagram combines ESBs and LEs automatically to create larger CAMs. to “don’t-care” has no effect on matches. outputs can distinguish multiple data locations. a third clock cycle is required.
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Note 119 (Implementing High-Speed Search Applications with APEX CAM). shows the ESB control signal generation logic. Figure 24. ESB Control Signal Generation (1) APEX 20KE devices have four dedicated clocks.
APEX 20K Programmable Logic Device Family Data Sheet Implementing Logic in ROM In addition to implementing logic with product terms, the ESB can implement logic functions when it is programmed with a read-only pattern during configuration, creating a large LUT. With LUTs, combinatorial functions are implemented by looking up the results, rather than by computing them. This implementation of combinatorial functions can be faster than using algorithms implemented in general logic, a performance advantage that is further enhanced by the fast access times of ESBs. The large capacity of ESBs enables designers to implement complex functions in one logic level without the routing delays associated with linked LEs or distributed RAM blocks. Parameterized functions such as LPM functions can take advantage of the ESB automatically. Further, the Quartus II software can implement portions of a design with ESBs where appropriate. Programmable Speed/Power Control APEX 20K ESBs offer a high-speed mode that supports very fast operation on an ESB-by-ESB basis. When high speed is not required, this feature can be turned off to reduce the ESB’s power dissipation by up to 50%. ESBs that run at low power incur a nominal timing delay adder. This Turbo Bit TM option is available for ESBs that implement product-term logic or memory functions. An ESB that is not used will be powered down so that it does not consume DC current. Designers can program each ESB in the APEX 20K device for either high-speed or low-power operation. As a result, speed-critical paths in the design can run at high speed, while the remaining paths operate at reduced power. I/O Structure The APEX 20K IOE contains a bidirectional I/O buffer and a register that can be used either as an input register for external data requiring fast setup times, or as an output register for data requiring fast clock-to-output performance. IOEs can be used as input, output, or bidirectional pins. For fast bidirectional I/O timing, LE registers using local routing can improve setup times and OE timing. The Quartus II software Compiler uses the programmable inversion option to invert signals from the row and column interconnect automatically where appropriate. Because the APEX 20K IOE offers one output enable per pin, the Quartus II software Compiler can emulate open-drain operation efficiently. The APEX 20K IOE includes programmable delays that can be activated to ensure zero hold times, minimum clock-to-output times, input IOE register-to-core register transfers, or core-to-output IOE register transfers. A path in which a pin directly drives a register may require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay.
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options in the Quartus II software. how fast bidirectional I/Os are implemented in APEX 20K devices. power-up high, the register cannot be asynchronously cleared or preset. Table 10. APEX 20K Programmable Delay Chains
Figure 25. APEX 20K Bidirectional I/O Registers Note (1) (1) The output enable and input registers are LE regi sters in the LAB adjacent to the bidirectional pin.
2 Dedicated
4 Dedicated
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directly to the LAB local interconnect within two MegaLAB structures. LE registers using local routing can improve setup times and OE timing. options in the Quartus II software. activation of the input upon power-up. Table 11. APEX 20KE Programmable Delay Chains
Figure 26. APEX 20KE Bidirectional I/O Registers Notes (1), (2) (1) This programmable delay has four settings: off and three levels of delay. (2) The output enable and input re gisters are LE registers in the LAB adjacent to the bidirectional pin.
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Figure 27. Row IOE Connection to the Interconnect
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APEX 20K Programmable Logic Device Family Data Sheet Advanced I/O Standard Support APEX 20KE IOEs support the following I/O standards: LVTTL, LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, PCI-X, 3.3-V AGP, LVDS, LVPECL, GTL+, CTT, HSTL Class I, SSTL-3 Class I and II, and SSTL-2 Class I and II. f For more information on I/O standards supported by APEX 20KE devices, see Application Note 117 (Using Selectable I/O Standards in Altera Devices). The APEX 20KE device contains eight I/O banks. In QFP packages, the banks are linked to form four I/O banks. The I/O banks directly support all standards except LVDS and LVPECL. All I/O banks can support LVDS and LVPECL with the addition of external resistors. In addition, one block within a bank contains circuitry to support high-speed True-LVDS and LVPECL inputs, and another block within a particular bank supports high-speed True-LVDS and LVPECL outputs. The LVDS blocks support all of the I/O standards. Each I/O bank has its own VCCIO pins. A single device can support 1.8-V, 2.5-V, and 3.3-V interfaces; each bank can support a different standard independently. Each bank can also use a separate V REF level so that each bank can support any of the terminated standards (such as SSTL-3) independently. Within a bank, any one of the terminated standards can be supported. EP20K300E and larger APEX 20KE devices support the LVDS interface for data pins (smaller devices support LVDS clock pins, but not data pins). All EP20K300E and larger devices support the LVDS interface for data pins up to 155 Mbit per channel; EP20K400E devices and larger with an X-suffix on the ordering code add a serializer/deserializer circuit and PLL for higher-speed support. Each bank can support multiple standards with the same VCCIO for output pins. Each bank can support one voltage-referenced I/O standard, but it can support multiple I/O standards with the same VCCIO voltage level. For example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs. When the LVDS banks are not used as LVDS I/O banks, they support all of the other I/O standards. Figure 29 shows the arrangement of the APEX 20KE I/O banks.
Figure 29. APEX 20KE I/O Banks supplies may be powered in any order. Devices chapter of the Configuration Devices Handbook.
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damage, but the I/O pins will drive out. Table 12 summarizes 5.0-V tolerant APEX 20K MultiVolt I/O support. considered when selecting a pull-up resistor. Table 12. 5.0-V Tolerant APEX 20K MultiVolt I/O Support
APEX 20K Programmable Logic Device Family Data Sheet APEX 20KE devices also support the MultiVolt I/O interface feature. The APEX 20KE VCCINT pins must always be connected to a 1.8-V power tolerant. The VCCIO pins can be connected to either a 1.8-V, 2.5-V, or 3.3-V power supply, depending on the I/O standard requirements. When the VCCIO pins are connected to a 1.8-V power supply, the output levels are compatible with 1.8-V systems. When VCCIO pins are connected to a 2.5-V power supply, the output levels are compatible with 2.5-V systems. When VCCIO pins are connected to a 3.3-V power supply, the output high is 3.3 V and compatible with 3.3-V or 5.0-V systems. An APEX 20KE device is 5.0-V tolerant with the addition of a resistor. Table 13 summarizes APEX 20KE MultiVolt I/O support. Notes to Table 13: (1) The PCI clamping diode must be disabled to drive an input with voltages higher than VCCIO, except for the 5.0-V input case. (2) An APEX 20KE device can be made 5.0-V tolerant with th e addition of an external resistor. You also need a PCI clamp and series resistor. (3) When V CCIO = 3.3 V, an APEX 20KE device can drive a 2.5-V device with 3.3-V tolerant inputs. ClockLock & ClockBoost APEX 20K devices support the ClockLock and ClockBoost clock management features, which are implemented with PLLs. The ClockLock circuitry uses a synchronizing PLL that reduces the clock delay and skew within a device. This reduction minimizes clock-to-output and setup times while maintaining zero hold times. The ClockBoost circuitry, which provides a clock multiplier, allows the designer to enhance device area efficiency by sharing resources within the device. The ClockBoost circuitry allows the designer to distribute a low-speed clock and multiply that clock on-device. APEX 20K devices include a high-speed clock tree; unlike ASICs, the user does not have to design and optimize the clock tree. The ClockLock and ClockBoost features work in conjunction with the APEX 20K device’s high-speed clock to provide significant improvements in system performance and band-width. Devices with an X-suffix on the ordering code include the ClockLock circuit. The ClockLock and ClockBoost features in APEX 20K devices are enabled through the Quartus II software. External devices are not required to use these features. Table 13. APEX 20KE MultiVolt I/O Support Note (1)
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the EP20K300E and larger devices have four PLLs.
- Clock multiplication and division can be used for time-domain
Table 14. Multiplication Factor Combinations
APEX 20K Programmable Logic Device Family Data Sheet Clock Phase & Delay Adjustment The APEX 20KE ClockShift feature allows the clock phase and delay to be adjusted. The clock phase can be adjusted by 90° steps. The clock delay can be adjusted to increase or decrease the clock delay by an arbitrary amount, up to one clock period. LVDS Support Two PLLs are designed to support the LVDS interface. When using LVDS, the I/O clock runs at a slower rate than the data transfer rate. Thus, PLLs are used to multiply the I/O clock internally to capture the LVDS data. For example, an I/O clock may run at 105 MHz to support 840 megabits per second (Mbps) LVDS data transfer. In this example, the PLL multiplies the incoming clock by eight to support the high-speed data transfer. You can use PLLs in EP20K400E and larger devices for high-speed LVDS interfacing. Lock Signals The APEX 20KE ClockLock circuitry supports individual LOCK signals. The LOCK signal drives high when the ClockLock circuit has locked onto the input clock. The LOCK signals are optional for each ClockLock circuit; when not used, they are I/O pins. ClockLock & ClockBoost Timing Parameters For the ClockLock and ClockBoost circuitry to function properly, the incoming clock must meet certain requirements. If these specifications are not met, the circuitry may not lock onto the incoming clock, which generates an erroneous clock within the device. The clock generated by the ClockLock and ClockBoost circuitry must also meet certain specifications. If the incoming clock meets these requirements during configuration, the APEX 20K ClockLock and ClockBoost circuitry will lock onto the clock during configuration. The circuit will be ready for use immediately after configuration. In APEX 20KE devices, the clock input standard is programmable, so the PLL cannot respond to the clock until the device is configured. The PLL locks onto the input clock as soon as configuration is complete. Figure 30 shows the incoming and generated clock specifications.
1 For more information on ClockLock and ClockBoost circuitry,
see Application Note 115: Using the ClockLock and ClockBoost PLL Features in APEX Devices.
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Figure 30. Specifications for the Incoming & Generated Clocks Note (1) to the nominal output clock period. parameters for -1 speed-grade devices. Table 15. APEX 20K ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices (Part 1 of 2)
(1) The PLL input frequency range for the EP20K100-1 X device for 1x multiplication is 25 MHz to 175 MHz. are not met, creating an erroneous clock within the device. time is less than the configuration time. (4) The jitter specification is me asured under long-term observation. (5) If the input clock stability is 100 ps, tJITTER is 250 ps. parameters for -2 speed grade devices. Table 15. APEX 20K ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices (Part 2 of 2) Table 16. APEX 20K ClockLock & ClockBoost Parameters for -2 Speed Grade Devices
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input frequency. The Quartus II software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. device operation. Simulation does not reflect this parameter. (2) Twenty-five thousand parts per million (PPM) equates to 2.5 % of input clock period. configuration because the tLOCK value is less than the time required for configuration. (4) The tJITTER specification is measured under long-term observation. Table 17. APEX 20KE ClockLock & ClockBoost Parameters Note (1)
Table 18. APEX 20KE Clock Input & Output Parameters (Part 1 of 2) Note (1)
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are not met, creating an erroneous clock within the device. (2) The maximum lock time is 40 µs or 2000 input clock cycles, whichever occurs first. once the CLKLK_ENA pin goes high in user mode. (4) The PLL VCO operating range is 200 MHz ð f VCO ð 840 MHz for LVDS mode. internal logic at speed without bringing internal signals to the I/O pins. Table 18. APEX 20KE Clock Input & Output Parameters (Part 2 of 2) Note (1)
performed before or after configuration, but not during configuration. Table 19. Although EP20K1500E devices support the JTAG BYPASS and use of the JTAG port for configuration. (1) The EP20K1500E device supports the JTAG BYPASS instruction and the SignalTap instructions. Table 19. APEX 20K JTAG Instructions pins. Also used by the SignalTap embedded logic analyzer. test pattern at the output pins and capturing test results at the input pins. allowing the USERCODE to be serially shifted out of TDO. IDCODE to be serially shifted out of TDO. Monitors internal device operation with the SignalTap embedded logic analyzer.
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(1) This device does not support JTAG boundary scan testing. Table 20. APEX 20K Boundary-Scan Register Length
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Figure 32. Multiple test patterns can be used to configure devices during all stages of the production flow. Table 22. APEX 20K JTAG Timing Parameters & Values
Figure 32. APEX 20K AC Test Conditions Note (1) observable noise immunity can result. capacitance for 2.5-V APEX 20K devices. Table 23. APEX 20K 5.0-V Tolerant Device Absolute Maximum Ratings Notes (1), (2)
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Table 24. APEX 20K 5.0-V Tolerant Device Recommended Operating Conditions Note (2) Table 25. APEX 20K 5.0-V Tolerant Device DC Operating Conditions (Part 1 of 2) Notes (2), (7), (8)
Table 25. APEX 20K 5.0-V Tolerant Device DC Operating Conditions (Part 2 of 2) Notes (2), (7), (8)
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(1) See the Operating Requirements for Altera Devices Data Sheet. (2) All APEX 20K devices are 5.0-V tolerant. input currents less than 100 mA and periods shorter than 20 ns. (4) Numbers in parentheses are for in dustrial-temperature-range devices. CC rise time is 100 ms, and VCC must rise monotonically. (7) Typical values are for T A= 25° C, VCCINT = 2.5 V, and VCCIO = 2.5 or 3.3 V. input buffers are 3.3-V PCI compliant when VCCIO and VCCINT meet the relationship shown in Figure 33 on page 68. (10) The I OH parameter refers to high-level TTL, PCI or CMOS output current. (12) This value is specified for normal device operation. The value may vary during power-up. (13) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO. (14) Capacitance is sample-tested only. capacitance for 1.8-V APEX 20KE devices. Table 26. APEX 20K 5.0-V Tolerant Device Capacitance Notes (2), (14) Table 27. APEX 20KE Device Absolute Maximum Ratings Note (1)
Table 28. APEX 20KE Device Recommended Operating Conditions
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Table 29. APEX 20KE Device DC Operating Conditions Notes (7), (8), (9)
1 For DC Operating Specifications on APEX 20KE I/O standards,
(1) See the Operating Requirements for Altera Devices Data Sheet. input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. (4) Maximum V CC rise time is 100 ms, and VCC must rise monotonically. dependent upon duty cycle of the signal. The DC case is equivalent to 100% duty cycle. parameters when VCCIO = 1.8 V. (10) The APEX 20KE input buffers are compatible with 1.8-V, 2.5-V and 3.3-V (LVTTL and LVCMOS) signals. OH parameter refers to high-level TTL, PCI, or CMOS output current. (13) This value is specified for normal device operation. The value may vary during power-up. (14) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO. (15) Capacitance is sample-tested only. compliance on APEX 20K devices. Table 30. APEX 20KE Device Capacitance Note (15)
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Figure 33. Relationship between VCCIO & VCCINT for 3.3-V PCI Compliance are 5-V PCI compliant over all operating conditions. Figure 34. Output Drive Characteristics of APEX 20K Device Note (1) (1) These are transient (AC) currents.
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are reported for maximum driver strength. Figure 36 shows the fMAX timing model for APEX 20K devices. Figure 36. APEX 20K fMAX Timing Model parameters can be used to estimate fMAX for multiple levels of logic.
Figure 37. APEX 20KE fMAX Timing Model
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waveforms, respectively, for the ESB macroparameters in Table 31. Figure 38. ESB Asynchronous Timing Waveforms
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Figure 40. Synchronous Bidirectional Pin External Timing Routing= Signal-Pin” option in the Quartus II software. occurs with the minimum setup time, varies with device density and speed grade. Table 31. APEX 20K fMAX Timing Parameters (Part 1 of 2)
Tables 32 and 33 describe APEX 20K external timing parameters. Table 31. APEX 20K fMAX Timing Parameters (Part 2 of 2) Table 32. APEX 20K External Timing Parameters Note (1) Table 33. APEX 20K External Bidirectional Timing Parameters Note (1)
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(1) These timing parameters are sample-tested only. timing microparameters for the fMAX timing model. Table 34. APEX 20KE LE Timing Microparameters Table 35. APEX 20KE ESB Timing Microparameters
Tables 38 and 39 describe the APEX 20KE external timing parameters. Table 36. APEX 20KE Routing Timing Microparameters Note (1) Table 37. APEX 20KE Functional Timing Microparameters Table 38. APEX 20KE External Timing Parameters Note (1)
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(1) These timing parameters are sample-tested only. Table 39. APEX 20KE External Bidirectional Timing Parameters Note (1)
EP20K200, and EP20K400 APEX 20K devices. Table 40. EP20K100 fMAX Timing Parameters
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Table 41. EP20K200 fMAX Timing Parameters
Table 42. EP20K400 fMAX Timing Parameters
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Table 43. EP20K100 External Timing Parameters Table 44. EP20K100 External Bidirectional Timing Parameters Table 45. EP20K200 External Timing Parameters
Table 46. EP20K200 External Bidirectional Timing Parameters Table 47. EP20K400 External Timing Parameters Table 48. EP20K400 External Bidirectional Timing Parameters
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(1) This parameter is measured without using ClockLock or ClockBoost circuits. (2) This parameter is measured using ClockLock or ClockBoost circuits. Bidirectional Timing Parameters for EP20K30E APEX 20KE devices. Table 49. EP20K30E fMAX LE Timing Microparameters
Table 50. EP20K30E fMAX ESB Timing Microparameters Table 51. EP20K30E fMAX Routing Delays
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Table 52. EP20K30E Minimum Pulse Width Timing Parameters Table 53. EP20K30E External Timing Parameters Table 54. EP20K30E External Bidirectional Timing Parameters
Bidirectional Timing Parameters for EP20K60E APEX 20KE devices. Table 55. EP20K60E fMAX LE Timing Microparameters
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Table 56. EP20K60E fMAX ESB Timing Microparameters
Table 57. EP20K60E fMAX Routing Delays Table 58. EP20K60E Minimum Pulse Width Timing Parameters Table 59. EP20K60E External Timing Parameters
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Table 60. EP20K60E External Bidirectional Timing Parameters Table 61. EP20K100E fMAX LE Timing Microparameters
Table 62. EP20K100E fMAX ESB Timing Microparameters Table 63. EP20K100E fMAX Routing Delays
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Table 64. EP20K100E Minimum Pulse Width Timing Parameters Table 65. EP20K100E External Timing Parameters Table 66. EP20K100E External Bidirectional Timing Parameters
Table 67. EP20K160E fMAX LE Timing Microparameters
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Table 68. EP20K160E fMAX ESB Timing Microparameters
Table 69. EP20K160E fMAX Routing Delays Table 70. EP20K160E Minimum Pulse Width Timing Parameters Table 71. EP20K160E External Timing Parameters
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Bidirectional Timing Parameters for EP20K200E APEX 20KE devices. Table 72. EP20K160E External Bidirectional Timing Parameters Table 73. EP20K200E fMAX LE Timing Microparameters
Table 74. EP20K200E fMAX ESB Timing Microparameters Table 75. EP20K200E fMAX Routing Delays
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Table 76. EP20K200E Minimum Pulse Width Timing Parameters Table 77. EP20K200E External Timing Parameters
Bidirectional Timing Parameters for EP20K300E APEX 20KE devices. Table 78. EP20K200E External Bidirectional Timing Parameters Table 79. EP20K300E fMAX LE Timing Microparameters
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Table 80. EP20K300E fMAX ESB Timing Microparameters Table 81. EP20K300E fMAX Routing Delays
Table 82. EP20K300E Minimum Pulse Width Timing Parameters Table 83. EP20K300E External Timing Parameters Table 84. EP20K300E External Bidirectional Timing Parameters
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Bidirectional Timing Parameters for EP20K400E APEX 20KE devices. Table 85. EP20K400E fMAX LE Timing Microparameters
Table 86. EP20K400E fMAX ESB Timing Microparameters
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Table 87. EP20K400E fMAX Routing Delays Table 88. EP20K400E Minimum Pulse Width Timing Parameters Table 89. EP20K400E External Timing Parameters
Bidirectional Timing Parameters for EP20K600E APEX 20KE devices. Table 90. EP20K400E External Bidirectional Timing Parameters Table 91. EP20K600E fMAX LE Timing Microparameters
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Table 92. EP20K600E fMAX ESB Timing Microparameters Table 93. EP20K600E fMAX Routing Delays
Table 94. EP20K600E Minimum Pulse Width Timing Parameters Table 95. EP20K600E External Timing Parameters Table 96. EP20K600E External Bidirectional Timing Parameters
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Bidirectional Timing Parameters for EP20K1000E APEX 20KE devices. Table 97. EP20K1000E fMAX LE Timing Microparameters
Table 98. EP20K1000E fMAX ESB Timing Microparameters
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Table 99. EP20K1000E fMAX Routing Delays Table 100. EP20K1000E Minimum Pulse Width Timing Parameters Table 101. EP20K1000E External Timing Parameters
Bidirectional Timing Parameters for EP20K1500E APEX 20KE devices. Table 102. EP20K1000E External Bidirectional Timing Parameters Table 103. EP20K1500E fMAX LE Timing Microparameters
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Table 104. EP20K1500E fMAX ESB Timing Microparameters Table 105. EP20K1500E fMAX Routing Delays
Table 106. EP20K1500E Minimum Pulse Width Timing Parameters Table 107. EP20K1500E External Timing Parameters
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grade to or from the LVCMOS value. Table 108. EP20K1500E External Bidirectional Timing Parameters Table 109. Selectable I/O Standard Input Delays
calculator on the Altera web site at http://www.altera.com. by a built-in weak pull-up resistor. Table 110. Selectable I/O Standard Output Delays
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is used, the system can configure automatically at system power-up. and configuration enable output (nCEO) pins on each device. Table 111. Data Sources for Configuration
APEX 20K Programmable Logic Device Family Data Sheet Revision History The information contained in the APEX 20K Programmable Logic Device Family Data Sheet version 5.1 supersedes information published in previous versions. Version 5.1 APEX 20K Programmable Logic Device Family Data Sheet version 5.1 contains the following changes: ■ In version 5.0, the VI input voltage spec was updated in Table 28 on page 63. ■ In version 5.0, Note (5) to Tables 27 through 30 was revised. ■ Added Note (2) to Figure 21 on page 33. Version 5.0 APEX 20K Programmable Logic Device Family Data Sheet version 5.0 contains the following changes: ■ Updated Tables 23 through 26. Removed 2.5-V operating condition tables because all APEX 20K devices are now 5.0-V tolerant. ■ Updated conditions in Tables 33, 38 and 39. ■ Updated data for tESBDATAH parameter. Version 4.3 APEX 20K Programmable Logic Device Family Data Sheet version 4.3 contains the following changes: ■ Updated Figure 20. ■ Updated Note (2) to Table 13. ■ Updated notes to Tables 27 through 30. Version 4.2 APEX 20K Programmable Logic Device Family Data Sheet version 4.2 contains the following changes: ■ Updated Figure 29. ■ Updated Note (1) to Figure 29.
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APEX 20K Programmable Logic Device Family Data Sheet Version 4.1 APEX 20K Programmable Logic Device Family Data Sheet version 4.1 contains the following changes: ■ tESBWEH added to Figure 37 and Tables 35, 50, 56, 62, 68, 74, 86, 92, 97, and 104. ■ Updated EP20K300E device internal and external timing numbers in Tables 79 through 84.
Copyright © 2004 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific de vice designations, and all other wo rds and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other co untries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and fo reign patents and pending applications, mask work rights, and copyrights. Altera warrants perfor mance of its semi conductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any inform ation, product, or service described herein except as expressly agreed to in writing by Alte ra Corporation. Altera customers are advised to obtain the latest vers ion of device specifications before relying on any published information and before placing orders for products or services.
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San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com APEX 20K Programmable Logic Device Family Data Sheet