EP20K1000C

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EPC devices offer the following features: ■ Single-chip configuration solution for Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA), Mercury, Stratix II, and Stratix II GX devices ■ Contains 4-, 8-, and 16-Mb flash memories for configuration data storage ■ On-chip decompression feature almost doubles the effective configuration density ■ Standard flash die and a controller die combined into single stacked chip package ■ External flash interface supports parallel programming of flash and external processor access to unused portions of memory ■ Flash memory block or sector protection capability using the external flash interface ■ Supported in EPC4 and EPC16 devices ■ Page mode support for remote and local reconfiguration with up to eight configurations for the entire system ■ Compatible with Stratix series remote system configuration feature ■ Supports byte-wide configuration mode fast passive parallel (FPP) with an 8-bit data output per DCLK cycle ■ Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs Table 1. Altera EPC Devices

Page 2 Functional Description Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation ■ Pin selectable 2-ms or 100-ms power-on reset (POR) time ■ Configuration clock supports programmable input source and frequency synthesis ■ Multiple configuration clock sources supported (internal oscillator and external clock input pin) ■ External clock source with frequencies up to 100 MHz ■ Internal oscillator defaults to 10 MHz and you can program the internal oscillator for higher frequencies of 33, 50, and 66 MHz ■ Clock synthesis supported using user programmable divide counter ■ A vailable in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra FineLine BGA (UFBGA) packages ■ V ertical migration between all devices supported in the 100-pin PQFP package ■ Supply voltage of 3.3 V (core and I/O) ■ Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification ■ Supports ISP using Jam Standard Test and Programming Language (STAPL) ■ Supports JTAG boundary scan ■ The nINIT_CONF pin allows private JT AG instruction to start FPGA configuration ■ Internal pull-up resistor on the nINIT_CONF pin always enabled ■ User programmable weak internal pull-up resistors on nCS and OE pins ■ Internal weak pull-up resistors on external flash interface address and control lines, bus hold on data lines ■ Standby mode with reduced power consumption f For more information about FPGA configuration schemes and advanced features, refer to the configuration chapter in the appropriate device handbook. Functional Description The Altera EPC device is a single device with high speed and advanced configuration solution for high-density FPGAs. The core of an EPC device is divided into two major blocks—a configuration controller and a flash memory. The flash memory is used to store configuration data for systems made up of one or more than one Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed using the external flash interface after the FPGA configuration is complete.

Table 2. Supported EPC Devices for Each Device Family (Part 1 of 3)

Table 2. Supported EPC Devices for Each Device Family (Part 2 of 3)

the Intel Flash Memory-Based EPC4, EPC8 and EPC16 Devices white paper. (1) The Raw Binary File ( .rbf) sizes are used to determine the data size for each device. (2) These values are calculated with the compression feature of the EPC device enabled. Table 2. Supported EPC Devices for Each Device Family (Part 3 of 3)

flash memory for all EPC devices. Table 3. EPC Devices Flash Memory Enhanced Configuration Devices.

Page 8 Functional Description Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation FPGA Configuration FPGA configuration is managed by the configuration controller chip. This process includes reading configuration data from the flash memory, decompressing the configuration data, transmitting configuration data using the appropriate DATA[] pins, and handling error conditions. After POR, the controller determines the user-defined configuration options by reading its option bits from the flash memory. These options include the configuration scheme, configuration clock speed, decompression, and configuration page settings. The option bits are stored at flash address location 0x8000 (word address) and occupy 512-bits or 32-words of memory. These options bits are read using the internal flash interface and the default 10 MHz internal oscillator. After obtaining the configuration settings, the configuration controller chip checks if the FPGA is ready to accept configuration data by monitoring the nSTATUS and CONF_DONE signals. When the FPGA is ready (nSTATUS is high and CONF_DONE is low), the controller begins data transfer using the DCLK and DATA[] output pins. The controller selects the configuration page to be transmitted to the FPGA by sampling its PGM[2..0] pins after POR or reset. The function of the configuration unit is to transmit decompressed data to the FPGA, depending on the configuration scheme. The EPC device supports four concurrent configuration modes, with n = 1, 2, 4, or 8 (where n is the number of bits that are sent per DCLK cycle on the DATA[n] signals). The value n = 1 corresponds to the traditional PS configuration scheme. The values n = 2, 4, and 8 correspond to concurrent configuration of 2, 4, or 8 different PS configuration chains, respectively. Additionally, the FPGA can be configured in FPP mode, where eight bits of DATA are clocked into the FPGA per DCLK cycle. Depending on the configuration bus width (n), the circuit shifts uncompressed configuration data to the valid DATA[n] pins. Unused DATA[] pins drive low. In addition to transmitting configuration data to the FPGAs, the configuration circuit is also responsible for pausing configuration whenever there is insufficient data available for transmission. This occurs when the flash read bandwidth is lower than the configuration write bandwidth. Configuration is paused by stopping the DCLK to the FPGA, when waiting for data to be read from the flash or for data to be decompressed. This technique is called “Pausing DCLK”. The EPC device flash-memories feature a 90-ns access time (approximately 10 MHz). Hence, the flash read bandwidth is limited to about 160 megabits per second (Mbps) (16-bit flash data bus, DQ[], at 10 MHz). However, the configuration speeds supported by Altera FPGAs are much higher and translate to high configuration write bandwidths. For example, 100-MHz Stratix FPP configuration requires data at the rate of 800 Mbps (8-bit DATA[] bus at 100 MHz). This is much higher than the 160 Mbps the flash memory can support and is the limiting factor for configuration time. Compression increases the effective flash-read bandwidth as the same amount of configuration data takes up less space in the flash memory after compression. Since Stratix configuration data compression ratios are approximately two, the effective read bandwidth doubles to about 320 Mbps.

low and triggers another configuration cycle. attempts to reconfigure the FPGA. and control lines, and enables bus-keep circuits on flash data lines. EPC device—FPP , PS, and concurrent configuration schemes. Table 4. Configuration Signals FPGA, which is latched on the rising edge of DCLK. needed if the INIT_CONF JTAG instruction is not needed. during POR and to signal an error during configuration. OE resets the EPC device controller. nCS CONF_DONE Configuration done output signal driven by the FPGA.

(with the few noted exceptions). chapter in the appropriate device handbook. Figure 2. FPP Configuration (1) The V CC should be connected to the same supply voltage as the EPC device. used. If nINIT_CONF is not used, nCONFIG must be pulled to VCC either directly or through a resistor. resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files. (4) For PORSEL, PGM[], and EXCLK pin connections, refer to Table 10 on page 24. to F-RP#, C-WE# to F-WE#, TM1 to VCC, TM0 to GND, and WP# to VCC. appropriate device handbook.

Functional Description Page 11 Enhanced Configuration (EPC) Devices DatasheetJanuary 2012 Altera Corporation Multiple FPGAs can be configured using a single EPC device in FPP mode. In this mode, multiple Stratix series FPGAs, APEX II FPGAs, or both, are cascaded together in a daisy chain. After the first FPGA completes configuration, its nCEO pin asserts to activate the nCE pin for the second FPGA, which prompts the second device to start capturing configuration data. In this setup, the FPGAs CONF_DONE pins are tied together, and hence all devices initialize and enter user mode simultaneously. If the EPC device or one of the FPGAs detects an error, configuration stops (and simultaneously restarts) for the whole chain because the nSTATUS pins are tied together.

1 While Altera FPGAs can be cascaded in a configuration chain, the EPC devices cannot

be cascaded to configure larger devices or chains. f For more information about configuration schematics and multi-device FPP configuration, refer to the configuration chapter in the appropriate device handbook. Passive Serial Configuration APEX 20KC, APEX 20KE, APEX 20K, APEX II, Cyclone series, FLEX 10K, and Stratix series devices can be configured using EPC devices in the PS mode. This mode is similar to the FPP mode, with the exception that only one bit of data ( DATA[0]) is transmitted to the FPGA per DCLK cycle. The remaining DATA[7..1] output pins are unused in this mode and driven low. The configuration schematic for PS configuration of a single FPGA or single-serial chain is identical to the FPP schematic, with the exception that only DATA[0] output from the EPC device connects to the FPGA DATA0 input pin and the remaining DATA[7..1] pins are left floating. f For more information about configuration schematics and multi-device PS configuration, refer to the configuration chapter in the appropriate device handbook. Concurrent Configuration EPC devices support concurrent configuration of multiple FPGAs (or FPGA chains) in PS mode. Concurrent configuration is when the EPC device simultaneously outputs n bits of configuration data on the DATA[n-1..0] pins (n = 1, 2, 4, or 8), and each DATA[] line serially configures a different FPGA chain. The number of concurrent serial chains is user-defined using the Quartus II software and can be any number from 1 to 8. For example, for three concurrent chains, you can select the 4-bit PS mode and connect the least significant DATA bits to the FPGAs or FPGA chains. Leave the most significant DATA bit (DATA[3]) unconnected. Similarly , for 5-, 6-, or 7-bit concurrent chains you can select the 8-bit PS mode. f For more information about configuration interface connections including pull-up resistor values, supply voltages, and MSEL pin settings, refer to the configuration chapter in the appropriate device handbook.

Tabl e 5 lists the concurrent PS configuration modes supported in the EPC device. refer to the configuration chapter in the appropriate device handbook. boot code, application code, or both. external device pins to access the flash memory when the flash interface is available. ignore transitions on the flash interface pins.

1 The external flash interface signals cannot be shared between multiple EPC devices

the controller chips inside the EPC devices are actively accessing flash memory. Therefore, EPC devices do not support shared flash bus interfaces. Table 5. EPC Devices in PS Mode (1) This is the number of valid DATA outputs for each configuration mode.

Page 14 Functional Description Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation The EPC device controller chip accesses flash memory during: ■ FPGA configuration—reading configuration data from flash ■ JTAG-based flash programming—storing configuration data in flash ■ At POR—reading option bits from flash During these operations, the external FPGA or processor must tri-state its interface to the flash memory. After configuration and programming, the EPC device’s controller tri-states the internal interface and goes into an idle mode. To interrupt a configuration cycle in order to access the flash using the external flash interface, the external device can hold the FPGA’s nCONFIG input low. This keeps the configuration device in reset by holding the nSTATUS-OE line low , allowing external flash access. f For more information about the software support for the external flash interface feature, refer to the Altera Enhanced Configuration Devices.

Page 16 Functional Description Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation Intel Flash-Based EPC Device Protection In the absence of the lock bit protection feature in the EPC4, EPC8, and EPC16 devices with Intel flash, Altera recommends four methods to protect the Intel Flash content in EPC4, EPC8, and EPC16 devices. Any method alone is sufficient to protect the flash. The methods are listed here in the order of descending protection level: 1. Using an RP# of less than 0.3 V on power-up and power-down for a minimum of 100 ns to a maximum 25 ms disables all control pins, making it impossible for a write to occur. 2. Using V PP < VPPLK , where the maximum value of VPPLK is 1 V , disables writes. VPP < VPPLK means programming or writes cannot occur. VPP is a programming supply voltage input pin on the Intel flash. VPP is equivalent to the VCCW pin on EPC devices. 3. Using a high CE# disables the chip. The requirement for a write is a low CE# and low WE#. A high CE# by itself prevents writes from occurring. 4. Using a high WE# prevent writes because a write only occurs when the WE# is low. Performing all four methods simultaneously is the safest protection for the flash content. The following lists the ideal power-up sequence: 1. Power up V CC. 2. Maintain V PP < VPPLK until VCC is fully powered up. 3. Power up V PP . 4. Drive RP# low during the entire power-up process. RP# must be released high within 25 ms after VPP is powered up. 1 CE# and WE# must be high for the entire power-up sequence. The following lists the ideal power-down sequence: 1. Drive RP# low for 100 ns before power-down. 2. Power down V PP < VPPLK . 3. Power down V CC. 4. Drive RP# low during the entire power-down process. 1 CE# and WE# must be high for the entire power-down sequence. The RP# pin is not internally connected to the controller. Therefore, an external loop-back connection between C-RP# and F-RP# must be made on the board even when you are not using the external device to the RP# pin with the loop-back connection. Always tri-state RP# when the flash is not in use.

Functional Description Page 17 Enhanced Configuration (EPC) Devices DatasheetJanuary 2012 Altera Corporation If an external power up monitoring circuit is connected to the RP# pin with the loop-back connection, use the following guidelines to avoid contention on the RP# line: ■ The power-up sequence on the 3.3-V supply should complete within 50 ms of power up. The 3.3-V V CC should reach the minimum VCC before 50 ms and RP# should then be released. ■ RP# should be driven low by the power-up monitoring circuit during power up. After power up, RP# should be tri-stated externally by the power-up monitoring circuit. If the preceding guidelines cannot be completed within 50 ms, then the OE pin must be driven low externally until RP# is ready to be released. Dynamic Configuration (Page Mode) The dynamic configuration (or page mode) feature allows the EPC device to store up to eight different sets of designs for all the FPGAs in your system. You can then choose which page (set of configuration files) the EPC device should use for FPGA configuration. Dynamic configuration or the page mode feature enables you to store a minimum of two pages—a factory default or fail-safe configuration and an application configuration. The fail-safe configuration page could be programmed during system production, while the application configuration page could support remote or local updates. These remote updates could add or enhance system features and performance. However, with remote update capabilities comes the risk of possible corruption of configuration data. In the event of such a corruption, the system could automatically switch to the fail-safe configuration and avoid system downtime. The EPC device page mode feature works with the Stratix remote system configuration feature, to enable intelligent remote updates to your systems. f For more information about remotely updating Stratix FPGAs, refer to the Remote System Configuration with Stratix & Stratix GX Devices chapter in the Stratix Device Handbook. The three PGM[2..0] input pins control which page is used for configuration and these pins are sampled at the start of each configuration cycle when OE goes high. The page mode selection allows you to dynamically reconfigure the functionality of your FPGA by switching the PGM[2..0] pins and asserting nCONFIG. Page 0 is defined as the default page and the PGM[2] pin is the MSB. 1 The PGM[2..0] input pins must not be left floating on your board. When you are not using this feature, connect the PGM[2..0] pins to GND to select the default page 000. The EPC device pages are dynamically-sized regions in memory. The start address and length of each page is programmed into the option-bit space of the flash memory during initial programming. All subsequent configuration cycles sample the PGM[] pins and use the option-bit information to jump to the start of the corresponding configuration page. Each page must have configuration files for all FPGAs in your system that are connected to that EPC device.

Page 18 Functional Description Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation For example, if your system requires three configuration pages and includes two FPGAs, each page will store two SRAM Object Files (.sof) for a total of six .sof in the configuration device. Furthermore, all EPC device configuration schemes (PS, FPP, and concurrent PS) are supported with the page-mode feature. The number of pages, devices, or both, that can be configured using a single EPC device is only limited by the size of the flash memory. f For more information about the page-mode feature implementation and programming file generation steps using the Quartus II software, refer to the Altera Enhanced Configuration Devices. Real-Time Decompression EPC devices support on-chip real time decompression of configuration data. FPGA configuration data is compressed by the Quartus II software and stored in the EPC device. During configuration, the decompression engine inside the EPC device will decompress or expand configuration data. This feature increases the effective-configuration density of the EPC device up to 7, 15, or 30 Mb in the EPC4, EPC8, and EPC16 devices, respectively. The EPC device also supports a parallel 8-bit data bus to the FPGA to reduce configuration time. However, in some cases, the FPGA data-transfer time is limited by the flash-read bandwidth. For example, when configuring an APEX II device in FPP (byte-wide data per cycle) mode at a configuration speed of 66 MHz, the FPGA write bandwidth is equal to 8 bits × 66 MHz = 528 Mbps. The flash read interface, however, is limited to approximately 10 MHz (since the flash access time is ~90 ns). This translates to a flash-read bandwidth of 16 bits × 10 MHz = 160 Mbps. Hence, the configuration time is limited by the flash-read time. When configuration data is compressed, the amount of data that needs to be read out of the flash is reduced by about 50%. If 16 bits of compressed data yields 30 bits of uncompressed data, the flash-read bandwidth increases to 30 bits × 10 MHz = 300 Mbps, reducing overall configuration time. You can enable the controller's decompression feature in the Quartus II software, Configuration Device Options window by turning on Compression Mode.

1 The decompression feature supported in the EPC devices is different from the

decompression feature supported by the Stratix II FPGAs and the Cyclone series. When configuring Stratix II FPGAs or the Cyclone series using EPC devices, Altera recommends enabling decompression in Stratix II FPGAS or the Cyclone series only for faster configuration. The compression algorithm used in Altera devices is optimized for FPGA configuration bitstreams. Since FPGAs have several layers of routing structures (for high performance and easy routability), large amounts of resources go unused. These unused routing and logic resources as well as un-initialized memory structures result in a large number of configuration RAM bits in the disabled state. Altera's proprietary compression algorithm takes advantage of such bitstream qualities.

defined as the original bitstream size divided by the compressed bitstream size). allocate sufficient configuration memory to store compressed bitstreams. duty cycle will not be 50%). Figure 5 shows a block diagram of the clock divider unit. DCLK frequency is limited by the maximum DCLK frequency the FPGA supports. FPGA, refer to the configuration chapter in the appropriate device handbook. Table 6. Stratix Compression Ratios (1) (1) These numbers are preliminary. They are intended to serve as a guideline, not a specification. Figure 5. Clock Divider Unit

10 MHz

33 MHz

50 MHz

66 MHz

33, 50, and 66 MHz. Tab le 7 lists the internal oscillator frequencies. internal oscillator at the 10 MHz setting as the clock source, with a divide factor of 1. divider settings, refer to the Altera Enhanced Configuration Devices. requires an external processor or FPGA to control the flash. 1 The EPC device flash memory supports 100,000 erase cycles. mode. The EPC device is compliant with the IEEE Std. 1532 draft 2.0 specification. configured with the new configuration data stored in flash. after programming option in the Programmer options window (Options menu). Table 7. Internal Oscillator Frequencies

Functional Description Page 21 Enhanced Configuration (EPC) Devices DatasheetJanuary 2012 Altera Corporation Programming using External Flash Interface This method allows parallel programming of the flash memory using the 16-bit data bus. An external processor or FPGA acts as the flash controller and has access to programming data using a communication link such as UART, Ethernet, and PCI. In addition to the program, erase, and verify operations, the external flash interface supports block or sector protection instructions. External flash interface programming is only allowed when the configuration controller has relinquished flash access by tri-stating its internal interface. If the controller has not relinquished flash access during configuration or JTAG-based ISP, you must hold the controller in reset before initiating external programming. The controller can be reset by holding the FPGA nCONFIG line at a logic low level. This keeps the controller in reset by holding the nSTATUS-OE line low, allowing external flash access.

1 If initial programming of the EPC device is done in-system using the external flash

interface, the controller must be kept in reset by driving the FPGA nCONFIG line low to prevent contention on the flash interface.

interface pins, external flash interface pins, JTAG interface pins, and other pins. Table 8. Configuration Interface Pins is latched into the FPGA on the rising edge of DCLK. DCLK Output The DCLK output pin from the EPC device serves as the FPGA configuration clock. DATA is latched by the FPGA on the rising edge of DCLK. the FPGA. The FPGA will always drive nCS and OE low when nCONFIG is asserted. OE pull-ups on configuration device option. voltage levels to stabilize. POR time can be extended by externally holding OE low. through the Disable nCS and OE pull-ups on configuration device option.

Table 9. External Flash Interface Pins (Part 1 of 2) operations. The addresses are internally latched during a write cycle. connected to the configuration controller. All address pins are connected internally in the 88-pin UFBGA package. This is the flash data bus interface between the flash memory and the controller. DQ[15..0] to the controller or external device. is high, it deselects the device and reduces power consumption to standby levels. This flash input pin is internally connected to the controller. Leave this pin floating on the board when the external flash interface is not used. memory, which provides data protection during power transitions. even when you are not using the external flash interface. with the loop back. Always tri-state RP# when the flash is not in use. Leave this pin floating on the board when the external flash interface is not used. even when you are not using the external flash interface.

because it could cause contention. programming the device using the Quartus II software. Block erase, full-chip erase, word write, or lock-bit configuration power supply. Leave this pin floating when the external flash interface is not used. two pins at the board level (for example, on the PCB, connect the C-WE# pin from controller to F-WE# pin from the flash memory). Devices and Using the Intel Flash Memory-Based EPC4, EPC8 and EPC16 white paper. Table 10. JTAG Interface Pins and Other Required Controller Pins (Part 1 of 2) TDI Input JTAG data input pin. Connect this pin to VCC if the JTAG circuitry is not used. TDO Output JTAG data output pin. Do not connect this pin if the JTAG circuitry is not used (leave this pin floating). Connect this pin to GND if the JTAG circuitry is not used. TMS Input JTAG mode select pin. Connect this pin to VCC if the JTAG circuitry is not used. configure the FPGAs in the system. selection is page 0; PGM[2..0]=000. These pins must not be left floating. Table 9. External Flash Interface Pins (Part 2 of 2)

device by driving the OE pin low. 1 Do not execute JTAG or ISP instructions until POR is complete. level selects the 2-ms delay, while a logic-low level selects the 100-ms delay. PORSEL is low, POR time is 100 ms. When PORSEL is high, POR time is 2 ms. This pin must be connected to a valid logic level. TM0 Input For normal operation, this test pin must be connected to GND. TM1 Input For normal operation, this test pin must be connected to V CC. Table 10. JTAG Interface Pins and Other Required Controller Pins (Part 2 of 2)

Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation Power Sequencing Altera requires that you power-up the FPGA's VCCINT supply before the EPC device's POR expires. Power up needs to be controlled so that the EPC device’s OE signal goes high after the CONF_DONE signal is pulled low . If the EPC device exits POR before the FPGA is powered up, the CONF_DONE signal will be high because the pull-up resistor is holding this signal high. When the EPC device exits POR, OE is released and pulled high by a pull-up resistor. Since the EPC device samples the nCS signal on the rising edge of OE, it detects a high level on CONF_DONE and enters an idle mode. DATA and DCLK outputs will not toggle in this state and configuration will not begin. The EPC device will only exit this mode if it is powered down and then powered up correctly .

1 To ensure the EPC device enters configuration mode properly, you must ensure that

the FPGA completes power-up before the EPC device exits POR. The pin-selectable POR time feature is useful for ensuring this power-up sequence. The EPC device has two POR settings—2 ms when PORSEL is set to a high level and 100 ms when PORSEL is set to a low level. For more margin, the 100-ms setting can be selected to allow the FPGA to power-up before configuration is attempted. Alternatively, a power-monitoring circuit or a power-good signal can be used to keep the FPGA’s nCONFIG pin asserted low until both supplies have stabilized. This ensures the correct power up sequence for successful configuration. Programming and Configuration File Support The Quartus II software provides programming support for the EPC device and automatically generates the .pof for the EPC4, EPC8, and EPC16 devices. In a multi-device project, the Quartus II software can combine the .sof for multiple ACEX 1K, APEX 20K, APEX II, Cyclone series, FLEX 10K, Mercury, and Stratix series FPGAs into one programming file for the EPC device. f For more information about generating programming files, refer to the Altera Enhanced Configuration Devices. EPC devices can be programmed in-system through the industry-standard 4-pin JTAG interface. The ISP feature in the EPC device provides ease in prototyping and updating FPGA functionality . After programming an EPC device in-system, FPGA configuration can be initiated by including the EPC device’s JTAG INIT_CONF instruction (refer to Table 11).

The ISP circuitry in the EPC device is compliant with the IEEE Std. 1532 specification. Programming Files utility, for use with the programmers or processors. Table 11. JTAG Instructions for EPC Devices (1) forcing a test pattern at the output pins and capturing results at the input pins. during normal device operation. programmable user-defined pattern. after programming option in the Programmer options window (Options menu). (INIT_CONF) JTAG instruction is issued. (1) Instruction register length for the EPC device is 10 and boundary scan length is 174.

(1) To calculate t OH, use the following equation: tOH = 0.5 (DCLK period) - 2.5 ns. (2) This parameter is used for CRC error detection by the FPGA. CONF_DONE error detection by the EPC device. (4) The FPGA V CCINT ramp time should be less than 1 ms for 2-ms POR and it should be less than 70 ms for 100-ms POR. Table 14. EPC Device Configuration Parameters (Part 2 of 2)

and pin capacitance data for the EPC devices. Table 15. Absolute Maximum Rating for EPC Devices Table 16. Recommended Operating Conditions for EPC Devices (1) Applicable for UBGA88 package of the EPC16 device only. Table 17. DC Operating Conditions for EPC Devices

layer. The EPC8 and EPC4 devices are available in the 100-pin PQFP package. EPC devices support vertical migration in the 100-pin PQFP package. Table 18. I CC Supply Current Values for EPC Devices (1) For the V CCW supply current information, refer to the appropriate flash memory data sheet at www.altera.com. Table 19. Capacitance for EPC Devices

vendor-supplied package outline diagrams. Figure 9. EPC Device PCB Footprint Specifications for 100-Pin PQFP Packages (1), (2) (1) Used 0.5-mm increase for front a nd back of nominal foot length. (2) Used 0.3-mm increase to maximum foot width.

f For more information, refer to the Configuration Devices Pin-Out Files page. Tabl e 20 lists the revision history for this document. Table 20. Document Revision History January 2012 3.0 Minor text edits. June 2011 2.9 Updated Table 1–3 and Table 1–16. ■ Added Table 1–1 and Table 1–2. ■ Updated Table 1–17 and Table 1–18. ■ Removed “Referenced Documents” section. ■ Updated Table 2–1, Table 2–7, and Table 2–8. ■ Updated Figure 2–2, Figure 2–3, and Figure 2–4. ■ Updated “JTAG-based Programming” section. ■ Added “Intel-Flash-Based EPC Device Protection” section. ■ Updated new document format. May 2008 2.6 Minor textual and style changes. Added “Referenced Documents” section. February 2008 2.5 Updated Table 2–18 with information about EPC16UI88AA. May 2007 2.4 Added “Intel-Flash-Based EPC Device Protection” section. April 2007 2.3 Added document revision history. October 2005 2.2 Made changes to content. ■ Added Stratix II and Cyclone II device information throughout chapter. ■ Updated VCCW connection in Figure 2–2, Figure 2–3, and Figure 2–4. ■ Updated (Note 2) of Figure 2–2, Figure 2–3, and Figure 2–4. ■ Updated (Note 4) of Table 2–12. ■ Updated unit of ICC0 in Table 2–16. September 2003 1.0 Initial Release.

Page 36 Document Revision History Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation