EP2015C ELANTEC | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 10

Technical content

[| Mromancmanmemeners — Fast Quad PNP Array FA i —— Features General Description s © Four independent fast PNP’s The EP2015 family are quad monolithic vertical PNP transistor | 5 © 350 MHz f, arrays which offer excellent parametric matching and high | 3 * Tight Vpg matching—1 mV speed performance. The 350 MHz fy provides A.C. performance | & © Tight H. matching_-5% similar to 2N3906 class devices. Manufactured on Elantec’s © One chi; es ction with Complementary Bipolar process, these transistors are electrical- Pisin pers ly isolated from each other by a layer of oxide. The resulting « Excellent th 1 ki low collector to substrate capacitance allows very high speed ‘xcellent thermal tracking performance with minimal crosstalk. In addition, complete D.C. * High Hf-—150 minimum isolation is achieved. Substrate biasing is not required for nor- ¢ 40V minimum BV ceo mal operation, however for optimum high speed performance * Each transistor similar to the substrate should be grounded. One-chip construction in- 2N3906 sures excellent parameter matching and tracking over tempera- © Pin compatible with TPQ3906 ture. MPQ3906 i i He The low cost EP2015C is specified at 25°C. The EP2015AC is pplications more tightly specified and guaranteed over the commercial tem- * Current sources perature range of 0°C to +75°C. The EP2015C and EP2015AC * Current mirrors are available in 14-pin plastic dual-in-line packages. : ieee For information on a complementary NPN transistor array, see Elantec’s EN2016 family data sheet. Ordering Information y PartNo. Temp. Range Package Outines | Elantec facilities comply with MIL-I-45208A and other applica- EPINSCN _vCw +780 por mre | ble quality specifications. For information on Elantec’s process- EPDUACN ¢Cto+7s¢ pp mpPeon | ing, request our brochure, QRA1: Elantec’s Processing— EPWHCM Ct +79C 2LeedS0L Mppoa | Monolithic Products. Connection Diagrams Isolation Characteristics 7 ax as p ncC2 ped xe a. Ch acy me T_] sal one aC 7 Es oe a on ay [re }e4 [J | we .

2 CU sup C3 fF} sus Si coe

eC3y fis} es we ~ LY iG 2 218-1 ez(3] [izes _ c_] o Top View ety rics ie o 5 las 5 o 8-3

S| Fast Quad PNP Array ee te S

8 Absolute Maximum Ratings

8 Pp Power Dissipation Tst Storage Temperature 65°C to + 150°C

a Each Transistor 500 mW (Ta = 25°C) Lead Temperature [25 Total Package 1.25W (Ta = 25°C) ‘SOL Package Ta. Operating Temperature Range =0Cto +75°C Vapor Phase (60 seconds) asc Ty Maximum Junction Temperature 150°C Infrared (15 seconds) 220°C (Soldering, <10 seconds) 300°C Von Max 4ov Ven = Max 38v Vcr Max 40v Ic Max 50 mA. Ip Mex 10mA ‘All parameters haying Min/Max specifications are guaranteed. The Test Level column indleates the specific device testing sctually equipment, specifically the LITX77 Series system. Unless otherwise noted, all tests are pulsed tests, therefore Ty=Te=Ta, | I 100% production tested and QA sample tested per QA test plan QCK0002. = Ae Se ae 0 100% produetion tested at Ta = 25°C and QA sample tested at Tx = 25°C; See ‘Dysax and Tyan Per QA test plan QCX0002, f a age m1 ‘QA sample tested per QA test plan QCX0002. : a 5 oe v Parameter is guaranteed (but not tested) by Design and Characterization Data = v Parameter is typical value at 4 = 25°C for information purposesonly.

Electrical Characteristics

AVBE (Note 1) Vor = 4V,I¢ = imA 5 " Ta = 25°C = [rw <tactwax | | | aw Hee (Notes 1, 2) Vee = 1V,Ic = 0.1 mA % Ta = 25°C [tm <ta<tuax [| [fe SHre2 (Notes 1, 2) Voce = 1V,I¢ = 1mA % Ta = 25°C AHfe3 (Notes 1,2) Veg = 1V,I¢ = 10mA % Ta = 25°C [ruin <ta<tuax | | [fs Her (Note 3) Ver = 1V,Ic = 0.1 mA Ta = 258°C Beez (Note 3) Ver = 1V,Io = 10mA a i a i Ta = 25°C epee [renter |

toe ee Se ee ee * | © a Electrical Characteristics — Contd. is a Parameter Description Test Conditions | min | Typ [mx | ee | Units > Qa Hes (Note 3) Vex = 1V,I¢ = 10mA a Ta = 25°C Vereat ote 3) Ic = 10mA, Ip = 1mA _ Ta = 25°C Veesat (Note 3) Ig = 10mA, Ip = 1mA ¥ Ta = 25°C BV ceo (Note 3) Tc = 1mA,Ip = 0mA V Ta = 25°C BVcto (Note 3) Io = 10pA,Ig = OmA v Ta = 25°C BV eto (Note 3) Ig = 10pA,Ic = OmA = Ta = 25°C Tebo (Note 3) Vor = 30V, Ig = 0mA nA Ta = 25°C Tebo (Note 3) Vee = 4V,I¢ = 0mA WA Ta = 25°C fy (Note 3) Vex = 20V,Ic = 10mA Tee ase 350 Lay. MHz TBE (Notes 3, 4) 10 pA, <Ig¢<2mA ¥ a Tans — 8 | Parameter | Description Test Conditions [mm [tre | me | ey | Units _ Level AVBE (Note 1) Ver = 4V,Ic = 1mA = Ta = 25°C [ tux <ta<twax [| [2 | om | nv Age (Notes 1, 2) Vou = 1V,I¢ = 0.1mA - % Ta = 25°C ‘ AHfe2 (Notes 1, 2) Vor = 1V,Io = 1mA * Ta = 25°C AHE (Notes 1, 2) Vee = 1V, 1c = 10mA ga T, = 25°C ees a [tun <ta<twax [| oe ome

2| EP201ISC/EP201ISAC——“( wt Pde DUD ee ee aS eee si FastQuadPNP Array %| Electrical Characteristics — Contd. Rg EP2015A a Parameter Description Test Conditions [Fest | Units Hees (Note 3) Vee = 1V,Ic = 0.1 mA. Pe | Ta = 25°C eet (26 | Her (Note 3) Veg = 1V,I¢ = 10mA bee Hees (Note 3) Vog = 1V,Ic = 10mA ge s VpEsat Note 3) Ic = 10mA, Ip = 1mA aS 7 Ta = 258°C fee oad a Veesat Ic = 10mA,Ip = 1mA a Ta = 25°C | ae) v BV cco (Note 3) Ig = 1mA, Ip = OmA a a a Ty = 25°C pease rr BVcto (Note 3) Ic = 10 pA, Ig = OmA ee Ta = 25°C a v BVebo (Note 3) Tg = 102A, Ic = OmA a. [now <t te | 3 | | a Vep = 30V, Ig = 0mA aoe aa = : : = s - Tebo (Note 3) Veg = 4V,Ic = OmA ase Fe Ta = 25°C Sa Siu on fe (Note 3) Veg = 20V, Ic = 10mA. oe Ty = 25°C ee i] MBs TBE (Notes 3, 4) 10pA <I¢<2mA 5 ne a Th = 25°C Fis ei Note 1: AVpg and AHy, are measured between each of six possible pairs of transistors. Note 2: AHfe is calculated based on the difference divided by the larger of the two readings. Note 3: Applies to all four transistors. Note 4: Estimated from log conformity. 8-6

= BP2015C7EP2015AC | ae Past Quad PNP Array |= suns nl Q S Typical Performance Curves 2 20-Lead SOL 14-Lend Plastic DIP a Maxim Pov Di eT Maxim Hegaee Forms etree eee > Thon = 180 “TT TAK = 1500 Q et MANO ee OT Eee ° 2 SO 75 125 150 ° “2 2 7S 125 (178 TEMPERATURE (°C) TEMPERATURE (°C) stent Note ww Yaliage Notoo 0mm, Cosum Cen ve Votare RSS Asati S54 wot vsic eo DELAY and Ton vs Ic Versa vs Ip eH oer “EA Ps RIay cs nny SE I YIN pon NY et & OH Perm ee) dL ATT * AR El “AU = eee | “ERE see LUT TT ~~ 12 8 we 0 0 et nd 10? elm) elon) 4” wise

2] EP201ISC/EP20ISAC = =i (ists 5| FastQuadPNP Array % Typical Performance Curves — Contd.

5 Junction Leakages Ig and Ic ve VBE wp Yoel

-n-8 z ge ee ian * Eoees -0-4 -0-4 . css eS | Ps fe| \\eut 77 SS can | | aeanvenral 0 -4 -8 = -% -20 0 02 04 06 08 10 0 -« -8 -2 -6 -2 vm Veew we Hee v3 Ic Hee ve Ie Isolation Characteristics 0 Co aan 1. | nec | Far Fed a ae al A “a SSC TAT 0g 2A amt IZ \\\\i 3 sco ee A 1 al \\| F pope NCC Tg 0 i 0 a8 ee mo -n8 rT IN TRS oT Terrecnve UIT |“ [TTeapacrance <0.6pF] 5 -0-8 yA ae = ‘ « 0 cw icy FREQUENCY (MH2) EP2015 PSPICE® Model Matched NPN transistors have allowed system Iss8f-13 BF-300 VA=47 IK=0.03 designers to make NPN current sinks. Now for XTB=13 BR=4.5 TF=03N TR=280N the first time Elantec’s fast matched PNP tran- RB-230 RC=170 ISE=1E—13 NE—1.24 _ sistors are available. These make excellent, fast, CCS—2P MS=0 CJC=3.7P PC=0.5 MC=0.45 matched current sources. The advantages of us- CJE=5.4P PE=0.6 ME=0.33 PTF=15 ing current sources as active loads, instead of pullup resistors include: Note that for the above model the maximum © Faster, linear pull up (Not exponential) “soft” saturation collector RC is used. For “hard” © High output resistance (This increases voltage saturation modeling set RC~9. gain in many applications) PSPICE® is a registered trademark of MicroSim Corporation.

— EP2015C/EP20154C | Current Sources and Current ve Ss Mirrors i Current sinks and current mirrors have long been J > a tool available to the designer of monolithic ICs. a The Norton and Thevenin equivalent circuits of a a in current source are: four Rout VIMEV ve NORTON EQUIV THEVENIN Pe ws wz (Vt) =~) ~ Vee And Viney = lour x Rout Iser = 7 Four examples of current mirrors are shown, n=n-= n= along with some of the advantages and limita- tions of each topology. For a more thorough dis- Rour = WA = EARLY VOLTAGE _ cussion see “Analysis and Design of Analog Inte- Tour Tour grated Circuits” by Grey & Meyer (Wiley 1984), . pages 233~247. PNP Wilson Current Mirror The Wilson is the best Current Mirror for high All current sources are only as good as the tran- _ frequency applications, and it has plenty of out- sistors that make them. If the transistors’ Vgz _put resistance. match is 5 mV the output current would have a 20% error. Mg All current sources shown can be improved by emitters. A 250 mV drop across these resistors [ reduces a 5 mV Vpg mismatch to a 2% current tour =tnr t= pea) 8 | error. This has the added benefit of increasing P output resistance. Elantec can guarantee a 1 mV Rour= 2 VE match so resistors may not be necessary. ra ViHev = R 2 Basic Current Source | 2° The Basic Current Mirror is simple and works ‘ser well at low currents. Its limitations are low out- = = put resistance and it is not as fast as the Wilson. ea

<| EP2015C/EP2015AC = 3 8| Fast Quad PNP Array : : ae iat eee a

8 Precision Current Source Cascode Current Source

| The Precision Current Source has excellent cur- © The Cascode Current Source is a basic current | cent match since the error reduction is propor- _ mirror with a common base transistor in the col- B tional to 82. It is slow to turn off since it has no lector. This makes Veg relatively constant for base turn off current. The turn off speed can be _the mirror transistors and greatly increases the increased by using Rx, at the expense of reduced output resistance. This has good high frequency accuracy. characteristics, Note that Q4 and Q5 can be ina package separate from Q1, Q2 and Q3. ve Fos i 4 woken ‘aa tour = serge R vrer [oe | [| nour bro v- Lod Biset 2015-8 tout = Benet teen = QUE =) = We) = = = ‘SET ~ R 20%8-10 eT Np? Jour = Isnt ay NTT Rout Tour

Se EP2015C/EP. 2 OL. 5AC xy ast Quad PNP Array |= ees 2 EP2015 Macromodel S “Connections: gic > , | qth a . 1 | ate . Lott we . Pot ot | ab . oto oto ot ot qe . Pot ot ot ot ot ase . es ee ee ee ee : foot toto ot tt ae . ee ee ee ee ee . ee ee ee ee ee ee ee . Le . Le subcktem2015 1 2 3 7 6 S$ 8 9 10 14 13 12 * Models -model ep2015 pnp (is = 8e~ 15 bf = 300 va= 47 ikf = 30mA xtb= 1.3 br=4.5 tf=0.3nS + tr=280nS rb= 230 re= 170 ise= le ~15 ne= 1.24 ccs = 2pF cje=3.7pF pe=0.5 +mc=0.45 cje= 5.4pF pe = 0.6 me=0.33 ptf 15) * Transistors ql 123 ep2015 q2765ep2015 93 89 10 ep2015 a4 14.13 12 ep2015 sends