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Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 13

Technical content

Features

  • Compliance Halogen Free (Br <900 ppm ,Cl <900 ppm , Br+Cl < 1500 ppm)
  • 3.3 and 5 V dual supply voltage
  • High speed 10Mbit/s
  • 10kV/ µs min. common mode transient immunity
  • Guaranteed performance from -40 to 85 ℃
  • Logic gate output, Fan out 10
  • High isolation voltage between input and output (Viso=3750 V rms )
  • Compliance with EU REACH
  • Pb free and RoHS compliant
  • UL and cUL approved(No. E214129)
  • VDE approved (No. 40028116)
  • SEMKO approved
  • NEMKO approved
  • DEMKO approved
  • FIMKO approved Description

Description

The EL060L consists of an infrared emitting diode optically coupled to a high speed integrated photo detector logic gate with a strobable output. It is packaged in a 8-pin SOP package and is suitable for surface mounting technology.

Applications

  • Ground loop elimination
  • LSTTL to TTL, LSTTL or 5 volt CMOS
  • Line receiver, data transmission
  • Data multiplexing
  • Switching power supplies
  • Pulse transformer replacement
  • Computer peripheral interface
  • High speed logic ground isolation Input Enable Output H H L L H H H L H L L H H NC L L NC H Schematic 8 1 A 0.1 µF bypass capacitor must be connected between pins 8 and 5 *1 Pin Configuration 1, No Connection 2, Anode 3, Cathode 4. No Connection 5, Gnd 6, Vout 7, V E 8, V CC Truth Table (Positive Logic)

8 PIN SOP 3.3V HIGH SPEED - 10MBit/s LOGIC GATE PHOTOCOUPLER EL060L Absolute Maximum Ratings (T A=25 )℃℃℃℃ Parameter Symbol Rating Unit Input Forward current IF 50 mA Enable input voltage Not exceed V CC by more than 500mV VE VCC + 0.5 V Enable Input Current IE 5 mA Reverse voltage VR 5 V Power dissipation P D 45 mW Output Power dissipation PC 85 mW Output current IO 50 mA Output voltage VO 7.0 V Supply voltage VCC 7.0 V Output Power Dissipation PO 85 mW Isolation voltage *2 V ISO 3750 V rms Operating temperature TOPR -40 ~ +85 ° C Storage temperature TSTG -55 ~ +125 ° C Soldering temperature *3 T SOL 260 ° C Notes : *1 The V CC supply must be bypassed by a 0.1 µF capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package V CC and GND pins *3 For 10 seconds

8 PIN SOP 3.3V HIGH SPEED - 10MBit/s LOGIC GATE PHOTOCOUPLER EL060L Electrical Characteristics (T A=-40 to 85° C unless specified otherwise) Input Parameter Symbol Min. Typ. Max. Unit Condition Forward voltage VF - 1.4 1.8 V IF = 10mA Reverse voltage VR 5.0 - - V IR = 10µA Temperature coefficient of forward voltage ∆ V F/∆ TA - -1.8 - mV/° C IF =10mA Input capacitance CIN - 60 - pF VF=0, f=1MHz Output Parameter Symbol Min Typ. Max. Unit Condition High level supply current I CCH - 5 10 mA IF=0mA, V E=0.5V, VCC =3.3V Low level supply current ICCL - 9 13 mA IF=10mA, VE=0.5V VCC =3.3V High level enable current I EH - - -1.6 mA V E=2.0 V, V CC =3.3V Low level enable current I EL - - -1.6 mA V E=0.5 V, V CC =3.3V High level enable voltage *4 VEH 2.0 - - V I F=10mA, V CC =3.3V Low level enable voltage V EL - - 0.8 V I F=10mA, V CC =3.3V Transfer Characteristics (TA=-40 to 85° C unless specified otherwise) Parameter Symbol Min Typ. Max. Unit Condition High level output current I OH - 5.0 100 uA VCC =3.3V, V O=3.3V, IF=250 µA, V E=2.0V Low level output voltage VOL - 0.35 0.6 V VCC = 3.3V, I F=5mA, VE=2.0V,I OL=13mA Input threshold current I FT - 3 5 mA VCC = 3.3V, V O=0.6V, VE =2.0V,I OL=13mA

8 PIN SOP 3.3V HIGH SPEED - 10MBit/s LOGIC GATE PHOTOCOUPLER EL060L Switching Characteristics (T A=-40 to 85° C, V CC =3.3V, I F=7.5mA unless specified otherwise) Parameter Symbol Min Typ. Max. Unit Condition Propagation delay time to output high level* 5 (Fig.12) tPHL - 50 75 ns CL = 15pF, R L=350 Ω, TA=25° C Propagation delay time to output low level* 6 (Fig.12) tPLH - 45 75 ns CL = 15pF, R L=350 Ω, TA=25° C Pulse width distortion |tPHL – t PLH | - 5 35 ns CL = 15pF, R L=350 Ω Output rise time* 7 (Fig.12) tr - 50 - ns CL = 15pF, R L=350 Ω Output fall time* 8 (Fig.12) tf - 10 - ns CL = 15pF, R L=350 Ω Enable propagation delay time to output High Level*9 (Fig.13) t ELH - 30 - ns IF = 7.5mA , VEH =3.0V, CL = 15pF, R L=350 Ω Enable propagation delay time to output low level* (Fig.13) tEHL - 15 - ns IF = 7.5mA , V EH =3.0V, CL = 15pF, R L=350 Ω Common mode transient Immunity at logic high *11 CM H 10,000 - - V/µS IF = 7.5mA , V OH =2.0V, RL=350 Ω, T A=25° C VCM =400Vp-p (Fig.14) Common mode transient immunity at logic low *12 CM L 10,000 - - V/µS IF = 0mA , V OL =0.8V, RL=350 Ω, T A=25° C VCM =400Vp-p (Fig.14)

8 PIN SOP 3.3V HIGH SPEED - 10MBit/s LOGIC GATE PHOTOCOUPLER EL060L Typical Electro-Optical Characteristics Curves

8 PIN SOP 3.3V HIGH SPEED - 10MBit/s LOGIC GATE PHOTOCOUPLER EL060L

8 PIN SOP 3.3V HIGH SPEED - 10MBit/s LOGIC GATE PHOTOCOUPLER EL060L Fig. 12 Test circuit and waveforms for t PHL , t PLH , t r, and t f Fig. 13 Test circuit and waveform for t EHL and t ELH Fig. 14 Test circuit Common mode Transient Immunity Switching Pos. (B), I F=7.5mA Switching Pos. (A), I F=0 CM L CM H VO(Min) VO(Max) Peak VCM 3.3V Vo VCM 0.5V 10% 90% Output (Vo) Output (Vo) Input (I F) IF=7.5mA IF=3.75mA 1.5V tr tf tPLH tPHL Output (Vo) Input (VE) 3.0V 1.5V 1.5V tELH tEHL

8 PIN SOP 3.3V HIGH SPEED - 10MBit/s LOGIC GATE PHOTOCOUPLER EL060L Note *4. Enable Input – No pull up resistor required as t he device has an internal pull up resistor. *5. t PLH – Propagation delay is measured from the 3.75mA level on the HIGH to LOW transition of the input current pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse. *6. t PHL – Propagation delay is measured from the 3.75mA level on the LOW to HIGH transition of the input current pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse. *7. t r– Rise time is measured from the 90% to the 10% leve ls on the LOW to HIGH transition of the output pulse. *8. t f– Fall time is measured from the 10% to the 90% leve ls on the HIGH to LOW transition of the output pulse. *9. t ELH – Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse. *10. t EHL – Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse. *11 CM H– The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the HIGH state (i.e., V OUT > 2.0V). *12 CM L– The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the LOW output state (i.e., VOUT < 0.8V). Order Information Part Number EL060L(Z)-V Note Z = Tape and reel option (TA, TB or none). V = VDE (optional) Option Description Packing quantity None Standard 100 units per tube -V Standard + VDE 100 units per tube (TA) TA tape & reel option 2000 units per reel (TB) TB tape & reel option 2000 units per reel (TA)-V TA tape & reel option + VDE 2000 units per reel (TB)-V TB tape & reel option + VDE 2000 units per reel

8 PIN SOP 3.3V HIGH SPEED - 10MBit/s LOGIC GATE PHOTOCOUPLER EL060L Package Dimension (Dimensions in mm) Recommended pad layout for surface mount leadform

8 PIN SOP 3.3V HIGH SPEED - 10MBit/s LOGIC GATE PHOTOCOUPLER EL060L Device Marking Notes EL denotes EVERLIGHT 060L denotes Device Number Y denotes 1 digit Year code WW denotes 2 digit Week code V denotes VDE (optional) EL 060L YWWV

8 PIN SOP 3.3V HIGH SPEED - 10MBit/s LOGIC GATE PHOTOCOUPLER EL060L Tape & Reel Packing Specifications Tape dimension Dimension No. A0 A1 B0 D0 D1 E F Dimension No. Po P1 P2 t W K0 K1 Option TA Option TB Direction of feed from reel Direction of feed from reel

8 PIN SOP 3.3V HIGH SPEED - 10MBit/s LOGIC GATE PHOTOCOUPLER EL060L Precautions for Use 1. Soldering Condition 1.1 (A) Maximum Body Case Temperature Profile for evaluation of Reflow Profile Note: Reference: IPC/JEDEC J -STD-020D Preheat Temperature min (T smin ) 150 ° C Temperature max (T smax ) 200° C Time (T smin to T smax ) (t s) 60 -120 seconds Average ramp -up rate (T smax to T p) 3 ° C/second max Other Liquidus Temperature (T L) 217 ° C Time above Liquidus Temperature (t L) 60 -100 sec Peak Temperature (T P) 260° C Time within 5 ° C of Actual Peak Temperature: T P - 5° C 30 s Ramp - Down Rate from Peak Temperature 6° C /second max. Time 25° C to peak temperature 8 minutes max. Reflow times 3 times

8 PIN SOP 3.3V HIGH SPEED - 10MBit/s LOGIC GATE PHOTOCOUPLER EL060L Disclaimer 1. Above specification may be changed without notic e. EVERLIGHT will reserve authority on material cha nge for above specification. 2. When using this product, please observe the abso lute maximum ratings and the instructions for using outlined in these specification sheets. EVERLIGHT assumes no responsi bility for any damage resulting from use of the pro duct which does not comply with the absolute maximum ratings and the instructions included in these specification sheets. 3. These specification sheets include materials pro tected under copyright of EVERLIGHT corporation. Pl ease don’t reproduce or cause anyone to reproduce them without EVERLIGHT’s consent.