IA186XL INNOVASIC | Alldatasheet
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IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 1 of 75 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontroller Data Sheet
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 2 of 75 1-888-824-4184 Copyright 2011 by Innovasic Semiconductor, Inc. Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
MILES™ is a trademark Innovasic Semiconductor, Inc. Intel is a registered trademark of Intel Corporation
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 4 of 75 1-888-824-4184
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 7 of 75 1-888-824-4184 1. Introduction The Innovasic Semiconductor IA186XL and IA188XL microcontrollers are form, fit, and function replacements for the original Intel 80C186XL and 80C188XL 16-bit high-integration embedded processors. These devices are produced using Innovasic’s Managed IC Lifetime Extension System (MILES™). This cloning technology, which produces replacement ICs beyond simple emulations, ensures compatibility with the original device, including any “undocumented features.” Additionally, the MILES™ process captures the clone design in such a way that production of the clone can continue even as silicon technology advances. The IA186XL and IA188XL microcontrollers replace the obsolete Intel 80C186XL and 80C188XL devices, allowing users to retain existing board designs, software compilers/assemblers, and emulation tools, thereby avoiding expensive redesign efforts.
1.1 General Description
The Innovasic Semiconductor IA186XL and IA188XL microcontrollers have a set of base peripherals beneficial to many embedded applications and include a standard numeric interface, an interrupt control unit, a chip-select unit/Ready Generation Logic, a DRAM refresh control unit, a Power-Save Control unit, DMA and three 16-bit timer/counters. The IA186XL and IA188XL microcontrollers operate at 5.0 volts ± 10%. The following functional description describes the base architecture of the 80C186XL. The 80C186XL is a very high integration 16-bit microprocessor. It combines some of the most common microprocessor system components onto one chip. The 80C186XL is object-code compatible with the 8086/8088 microprocessors and adds ten new instruction types to the 8086/8088 instruction set. The 80C186XL has two major modes of operation, Compatible and Enhanced. In Compatible Mode, the 80C186XL is completely compatible with the 80186, with the exception of 8087 support. The Enhanced mode adds three new features to the system design. These are Power- Save control, Dynamic RAM refresh, and an asynchronous Numerics Coprocessor interface (80C186XL only).
1.2 Features
The primary features of the IA186XL and IA188XL microcontrollers are as follows: Form, fit, and function compatible version of the low power Intel 80C186XL/80C188XL Operation modes: – Enhanced mode o DRAM refresh control unit
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 8 of 75 1-888-824-4184 o Power-save mode o Direct interface to 80C187 (IA186XL only) – Compatible mode o Pin-for-pin replacement for NMOS 80186/80188 non-numeric applications Integrated feature set – Static, modular CPU – Clock generator – Two independent DMA channels – Programmable interrupt controller – Three programmable 16-bit timers – Dynamic RAM refresh control unit – Programmable memory and peripheral chip select logic – Programmable wait state generator – Local bus controller – Power-save mode – System-level testing support (high impedance test mode) Completely object-code compatible with existing 8086/8088 software and has ten additional instructions over 8086/8088 Crystal supports internal 20–25 MHz operation Direct addressing capability to 1 MByte memory and 64 Kbyte I/O Available in 68-Lead: – Plastic Leaded Chip Carrier (PLCC) Available in 80-Lead: – Plastic Quad Flat Pack (PQFP) – Low Profile Quad Flat Pack (LQFP) Extended Temperature Range (-40°C to +85°C) Chapter 4, Functional Description, provides details of the IA186XL and IA188XL microcontrollers, including the features listed above.
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 9 of 75 1-888-824-4184 2. Packaging, Pin Descriptions, and Physical Dimensions Information on the packages and pin descriptions for the IA186XL and the IA188XL is provided separately. Refer to sections, figures, and tables for information on the device of interest.
2.1 Packages and Pinouts
The Innovasic Semiconductor IA186XL and IA188XL microcontroller is available in the following packages: 68-Lead Plastic Leaded Chip Carrier (PLCC), equivalent to original PLCC package 80-Lead Plastic Quad Flat Pack (PQFP), equivalent to original PQFP package 80-Lead Low Profile Quad Flat Pack (LQFP), equivalent to original SQFP package
2.1.1 IA186XL 68 PLCC Package
pinout is provided in Table 1. Figure 1. IA186XL 68-Lead PLCC Package Diagram
Table 1. IA186XL 68-Lead PLCC Pin Listing
2.1.2 IA188XL 68 PLCC Package
pinout is provided in Table 2. indicate proper orientation. Pin 1 is designated by the ink mark, as shown in Figure 2. Figure 2. IA188XL 68-Lead PLCC Package Diagram
Table 2. IA188XL 68-Lead PLCC Pin Listing
2.1.3 PLCC Physical Dimensions
The physical dimensions for the 68 PLCC are as shown in Figure 3. Figure 3. PLCC Physical Package Dimensions Note: Controlling dimension in inches.
2.1.4 IA186XL 80 PQFP Package
pinout is provided in Table 3. Figure 4. IA186XL 80-Lead PQFP Package Diagram
Table 3. IA186XL 80-Lead PQFP Pin Listing
2.1.5 IA188XL 80 PQFP Package
pinout is provided in Table 4. Figure 5. IA188XL 80-Lead PQFP Package Diagram
Table 4. IA188XL 80-Lead PQFP Pin Listing
2.1.6 PQFP Physical Dimensions
The physical dimensions for the 80 PQFP are as shown in Figure 6. Figure 6. PQFP Physical Package Dimensions
- Dimension D1 and E1 do not include mold protrusion.
- Dimension b does not include dambar protrusion.
2.1.7 IA186XL 80 LQFP Package
pinout is provided in Table 5. Figure 7. IA186XL 80-Lead LQFP Package Diagram
Table 5. IA186XL 80-Lead LQFP Pin Listing
2.1.8 IA188XL 80 LQFP Package
pinout is provided in Table 6. Figure 8. IA188XL 80-Lead LQFP Package Diagram
Table 6. IA188XL 80-Lead LQFP Pin Listing
2.1.9 LQFP Physical Dimensions
The physical dimensions for the 80 LQFP are as shown in Figure 9. Figure 9. LQFP Physical Package Dimensions
- Exact shape of each corner is optional.
- Controlling dimension: mm.
- To be determined at seating plane C.
- Dimensions D1 and E1 do not include
dimensions including mold mismatch.
- Dimension b does not include dambar
on the lower radius of the foot.
- Exact shape of each corner is
- These dimensions apply to the flat
- A1 is defined as the distance from the
2.2 IA186XL Pin/Signal Descriptions
Table 7. IA186XL Pin/Signal Descriptions a1 pcs5_n/a1 31 48 65 Latched address bit a1. Output. a2 pcs6_n/a2 32 47 64 Latched address bit a2. Output. and T4 they provide bus status. using the ale signal (see next table entry).
Table 7. IA186XL Pin/Signal Descriptions (Continued) ale ale/qs0 61 10 29 address latch enable. Output. Active High. the address portion of a bus cycle. device will complete the transfer. the upper half of the data bus. Numerics Coprocessor instructions. one-half the input clock (clkin) frequency. transitioning every falling edge of clkin. level-triggered and internally synchronized.
bidirectional buffers in a buffered system. hlda hlda 51 25 42 hold acknowledge. Output. Active High. a HOLD request (see next table entry). conditioned by a LOCK prefix. int0 int0 45 31 48 interrupt N (N = 0–3). Input. Active High. inta 0_n int2/inta0_n 42 35 52 interrupt acknowledge. Output. Active low.
high and must not be driven low. mcs0_n mcs0_n/pereq 38 39 57 mid-range memory chip select. Output. nmi nmi 46 30 47 non-maskable interrupt. Input. Active High. pcs0_n pcs0_n 25 54 71 peripheral chip select signals 0–6. Output. pereq mcs0_n/pereq 38 39 57 numerics coprocessor external request.
qs0 ale/qs0 61 10 29 queue status 0, queue status 1. Output. qsmd_n rd_n/qsmd_n 62 9 28 queue status mode. Input. Sampled at reset. location being accessed onto the data bus. being reset. It can be used as a system reset. N = 1 for DMA or refresh cycle. srdy srdy 49 27 44 synchronous ready. Input.
used either as clock input or a control signal. used either as clock input or a control signal. connected to a VSS board plane. accessed memory or I/O device.
2.3 IA188XL Pin/Signal Descriptions
Table 8. IA188XL Pin/Signal Descriptions a1 pcs5_n/a1 31 48 65 Latched address bit a1. Output. a2 pcs6_n/a2 32 47 64 Latched address bit a2. Output. T2, T3, TW and T4 they provide bus status. ad0 ad0 17 64 1 address/data bits 0 - 15. Input/Output.
Table 8. IA188XL Pin/Signal Descriptions (Continued) ale ale/qs0 61 10 29 address latch enable. Output. Active High. device will complete the transfer. one-half the input clock (clkin) frequency. transitioning every falling edge of clkin. bidirectional buffers in a buffered system.
hlda hlda 51 25 42 hold acknowledge. Output. Active High. a HOLD request (see next table entry). conditioned by a LOCK prefix. int0 int0 45 31 48 interrupt N (N = 03). Input. Active High. inta 0_n int2/inta0_n 42 35 52 interrupt acknowledge. Output. Active low.
high and must not be driven low. mcs0_n mcs0_n/pereq 38 39 57 mid-range memory chip select. Output. nmi nmi 46 30 47 non-maskable interrupt. Input. Active High. pcs0_n pcs0_n 25 54 71 peripheral chip select signals 0–6. Output. qs0 ale/qs0 61 10 29 queue status 0, queue status 1. Output. qsmd_n rd_n/qsmd_n 62 9 28 queue status mode. Input. Sampled at reset.
being reset. It can be used as a system reset. indicate a refresh bus cycle. N = 1 for DMA or refresh cycle. srdy srdy 49 27 44 synchronous ready. Input. used either as clock input or a control signal. used either as clock input or a control signal.
connected to a VSS board plane. accessed memory or I/O device.
- Maximum Ratings, Thermal Characteristics, and DC Parameters
Table 9. IA186XL and IA188XL Absolute Maximum Ratings Table 10. IA186XL and IA188XL Thermal Characteristics
Table 11. IA186XL and IA188XL DC Parameters
5.0 Volt
Operating temperature is −40°C to 85°C.
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 39 of 75 1-888-824-4184 4. Functional Description The follow descriptions apply to both the IA186XL and IA188XL unless otherwise noted. Module descriptions are followed by descriptions of special operating modes. Additional information on the operation and programming of the 80C186XL/80C188XL can be found in the following Intel® publications: 80C186XL/80C188XL and 80L186XL/80L188XL 16-Bit High-Integration Embedded Processors (272433-006) 80C186XL/80C188XL Microprocessor User’ s Manual (270830-00n)
4.1 Device Architecture
Architecturally, the IA186XL microcontrollers include the following functional modules: Bus Interface Unit Clock Generator Interrupt Control Unit Timer/Counter Unit Chip-Select Unit Refresh Control Unit Power-Save Control DMA Unit A functional block diagram of the IA186XL/IA188XL is shown in Figure 10. Descriptions of the functional modules are provided in the follow subsections. Control registers for the peripheral modules are located in a 256 byte control block. This block can be mapped to either memory or I/O space. The offset map for addressing these registers is given in Table 12.
4.1.1 Bus Interface Unit
A local bus controller generates the local bus control signals. It also employs a hold/hlda protocol for relinquishing the local bus to other bus masters. Its outputs can be used to enable external buffers and to direct the flow of data on and off the local bus. The bus controller is responsible for generating 20 bits of address, read and write strobes, bus-cycle status information and data. This controller is also responsible for reading data from the local bus during a read operation. Synchronous and asynchronous ready input pins are provided to extend a bus cycle beyond the minimum four clocks. The bus controller also generates two control signals (den_n
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 40 of 75 1-888-824-4184 and dt/r_n) when interfacing to external transceiver chips. This capability allows the addition of transceivers for simple buffering of the multiplexed address/data bus. During reset, the local bus controller performs the following actions: 1. Floats ad0–15 (ad0–8), a16–19 (a9–a19), bhe_n (rfsh_n), dt/r_n 2. Drives ale LOW 3. Drives hlda LOW 4. Drives lock_n HIGH and then floats 5. Drives den_n, rd_n, and wr_n HIGH for one clock cycle, then floats them 6. Drives s0_n, s1_n and s2_n to the inactive state (all HIGH) and then floats them
Figure 10. IA186XL/IA188XL Functional Block Diagram
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 42 of 75 1-888-824-4184 The rd_n/qsmd_n, ucs_n, lcs_n, mcs0_n/pereq, mcs1_n/error_n, and test_n/busy pins include internal pull-ups that are active while res_n is applied. The state of these pins during reset controls invoking various alternative operating modes as described below: 1 ONCE Mode – ucs_n and lcs_n driven low. 2 Enhanced Mode – test_n/busy driven low then high. 3 Queue Status Mode – rd_n/qsmd_n driven low.
4.1.2 Clock Generator
The IA186XL/IA188XL uses an on-chip clock generator to supply internal and external clocks. The clock generator makes use of a crystal oscillator and includes a divide-by-two counter. Figure 11 shows the various operating modes of the clock circuit. The clock circuit can use either a parallel resonant fundamental mode crystal network (A) or a third-overtone mode crystal network (B), or it can be driven by an external clock source (C). The following parameters are recommended when choosing a crystal: Temperature Range: Application Specific ESR (Equivalent Series Resistance): 60 max C0 (Shunt Capacitance of Crystal): 7.0 pF max CL (Load Capacitance): 20 pF ± 2 pF Drive Level: 2 mW max
4.1.3 Interrupt Control Unit
The IA186XL operates with several interrupt sources. A separate Interrupt Control Unit manages all sources based on priority to be individually handled by the CPU. The DMA and Timers produce internally generated requests. There are five externally generated interrupts - a single NMI and 4 others.
4.1.4 Timer/Counter Unit
There are three programmable internal timers in the IA186XL. Two are very flexible and can be configured for many tasks. Each of these has a single input used for either control or clocking, and a single output to generate waveforms. The third timer is simpler and can only be clocked from an internal source. It can be used for simple timing applications. It can also be used as a prescaler to the other two timers or as a trigger for DMA requests.
Figure 11. Clock Circuit Connection Options
4.1.5 Chip-Select/Ready Generation Logic
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 44 of 75 1-888-824-4184 A programmable number of wait states (0 - 3) can be used to generate an internal ready for each chip select range. The IA186XL can be programmed to use or not use the external ready signal with or without the internal wait states from the internal ready being factored in. At reset, the Chip-Select/Ready Logic will be configured as follows: 1. All chip-select outputs will be driven HIGH 2. Exiting RESET, the UCS control register (UMCS) is set to FFFBH, providing chip select to a 1-Kbyte block of memory with 3 wait states in combined with external ready. 3. All other chip select control registers are undefined after reset. The CPU must configure these control registers before the corresponding chips selects will become active.
4.1.6 DMA
The IA186XL includes a DMA controller with two channels. Transfers can occur between any combination of Memory and I/O space, to either odd or even address. Data size can be either 8 or 16 bits, except on the IA188XL it can only be 8 bits. There are separate 20-bit source and destination pointers for each channel. These pointers can be configured to increment, decrement or stay static after each transfer. For word transfers, pointers are incremented or decrement by two and for byte transfers, by one. One bus cycle is required to fetch data and one cycle to deposit it.
4.1.7 DRAM Refresh Control Unit
When in Enhanced Mode, the IA186XL supports DRAM refresh cycles. Reads are automatically generated at a programmable time interval. If enabled, chip selects are active for these reads.
4.1.8 Power-Save Control
When in Enhanced Mode, the IA186XL supports a power save mode of operation. The internal clock frequency is divided by a programmable amount. This affects all internal logic including, timers, the refresh control unit and clkout generation. Timers and the refresh control unit need to be reprogrammed accordingly when going in and out of power save if you wish to maintain the same real time references.
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 45 of 75 1-888-824-4184
4.2 Operating Modes
During reset the IA186XL can be configured to enable special operating modes described as follows.
4.2.1 Enhanced Mode
If Enhanced Mode is enabled, the IA186XL has DRAM refresh, Power-Save and coprocessor support available in addition to the normal features available in Compatible Mode. Enhanced Mode will be invoked automatically if a coprocessor is attached. It can also be entered by tying the reset output to the test_n/busy input. An internal pull-up keeps the part from entering Enhanced mode during normal operation. When not in Enhanced Mode, none of the Enhanced Mode registers can be accessed. Queue- Status functions, except for the coprocessor support, will be available when not in Enhanced Mode.
4.2.2 Queue Status Mode
When Queue Status Mode is enabled, information about the instruction queue is output on the ale/qs0 and wr_n/qs1 pins. To enter Queue Status Mode, the rd_n input should be tied low. It is sampled at reset, and if low, Queue Status Mode is entered. An internal pull-up keeps the part from entering Queue Status mode during normal operation.
4.2.3 ONCE Mode
ONCE mode is a special test mode where all pins are set to a high impedance state. ONCE mode is entered by forcing lcs_n and ucs_n low during reset. These pins are sampled on the rising edge of res but should be held low for at least a full clock cycle after res goes high. ONCE mode is exited by reseting the part with lcs_n and ucs_n high. Internal pull-ups keep the part from entering ONCE mode during normal operation.
4.2.4 Math Coprocessor (IA186XL Only)
When Enhanced mode is enabled, the IA186XL is configured to interface with a math coprocessor via three of the middle chip select pins. Pin mcs0/pereq is used for Processor Extension Request. Pin mcs1/error is used for coprocessor error indication. Pin mcs3/nps is used for Numeric Processor Select.
Table 12. Internal Register Map
1 The Step ID register (offset 0xF6) for Revision 1 of the Innovasic device is read-only, and is
established a value between 0x0000 and 0x0003, depending on the revision of the part.
5.1 Major Cycle Timings – Read Cycle
All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CL = 50 pF. For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V. Table 13. Major Cycle Timings – Read Cycle
Figure 12. Read Cycle Waveforms Please note that pins indicated in the parentheses are for the IA188XL version. (2) Status is inactive in the state preceding T4. (3) Only TCLCSV is applicable if latched A1 and A2 are selected instead of PCS5 and PCS6. (4) This applies when a write cycle is followed by read cycle. (5) This is T1 of next bus cycle. (6) This changes in the T-state preceding the next bus cycle if followed by a write.
5.2 Major Cycle Timings – Write Cycle
All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CL = 50 pF. For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V. Table 14. Major Cycle Timings – Write Cycle
Figure 13. Write Cycle Waveforms Please note that pins indicated in the parentheses are for the IA188XL version. (2) Status is inactive in the state preceding T4. (3) Only TCLCSV is applicable if latched A1 and A2 are selected instead of PCS5 and PC S6. (4) This applies when a write cycle is followed by a read cycle. (5) This is T1 of next bus cycle. (6) This changes in the T-state preceding the next bus cycle if followed by a read, INTA or halt.
5.3 Major Cycle Timings – Interrupt Acknowledge Cycle
All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CL = 50 pF. For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V. Table 15. Major Cycle Timings – Interrupt Acknowledge Cycle
Figure 14. Interrupt Acknowledge Cycle Waveforms Please note that pins indicated in the parentheses are for the IA188XL version. (1) The OEM part (80C186XL) operates differently in that it deasserts on the falling edge of CLKOUT. (2) Status is inactive in the state preceding T4. (3) The data hold time lasts only until INTA goes inactive, even if the INTA transition occurs prior to TCLDX (min). (4) INTA occurs one clock later in Slave Mode. (5) This applies when a write cycle is followed by an interrupt acknowledge cycle. (7) Changes in T-state preceding next bus cycle if followed by write.
5.4 Software Halt Cycle Timings
All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CL = 50 pF. For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V. Table 16. Software Halt Cycle Timings
Figure 15. Software Halt Cycle Waveforms Please note that pins indicated in the parentheses are for the IA188XL version. (1) The OEM part (80C186XL) operates differently in that it deasserts on the falling edge of CLKOUT. (2) This applies when a write cycle is followed by a halt cycle.
5.5 Clock Timings
All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CL = 50 pF. For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V. Table 17. Clock Timings
- External clock applied to X1 and X2 not connected.
- TCLCK and TCHCK (CLKIN Low and High times) should not have a duration less than 40% of T CKIN.
- Tested under worst case conditions: VCC = 5.5V. TA = 70￮C.
- Tested under worst case conditions: VCC = 4.5V. TA = 0￮C.
5.6 Ready, Peripheral and Queue Status Timings
All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CL = 50 pF. For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V. Table 18. Ready, Peripheral and Queue Status Timings
- To guarantee proper operation.
- To guarantee recognition at clock edge.
5.7 Reset and HOLD/HLDA Timings
All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CL = 50 pF. For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V. Table 19. Reset and HOLD/HLDA Timings
- To guarantee recognition at next clock.
- Instruction Execution Times
additional information on execution, if required. Table 20. Instruction Set Timing
Table 20. Instruction Set Timing (Continued)
- Innovasic Part Number Cross-Reference
Table 21. Innovasic Part Number Cross-Reference for the PLCC
Table 22. Innovasic Part Number Cross-Reference for the PQFP (Special Order only)
Table 23. Innovasic Part Number Cross-Reference for the LQFP (Special Order only)
problem has been provided where possible.
8.1 Summary
Table 24 presents a summary of errata. Table 24. Summary of Errata
1 Pin LOCK_n does not have an internal pullup and
will float during reset and bus hold. instead of x10000 as in the OEM part. or INTA1 may be lost or truncated.
4 Memory->Memory moves interrupted by two DMA
5 Bit 15 of RELREG (offset 0xFE) behaves
6 Enhanced mode makes bit 15 of RELREG (offset
8 Timer2 count register must be written to enable
9 Non-maskable interrupt (NMI) can be pre-empted
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 70 of 75 1-888-824-4184 Errata No. Problem Ver. 0 Ver. 1 Ver. 2
11 MOVS/POP/PUSH instructions interrupted by
DMA can corrupt data. Exists Exists Fixed
12 MOVS/POP/PUSH instructions interrupted by
DMA can corrupt data. Exists Exists Fixed
8.2 Detail
Errata No. 1 Problem: Pin LOCK_n does not have an internal pullup. Description: Because Pin LOCK_n does not have an internal pullup, it will float during reset and bus hold. Workaround: An external pullup may be necessary if there is high external load on the signal. Errata No. 2 Problem: When the timer compare register for any of the timers is set to x0000, the max count is xFFFF instead of x10000 as in the OEM part. Description: The timer output will change one count earlier than it should when the max count is set to x0000. Workaround: The workaround is application dependent. Please contact Innovasic Technical Support if this erratum is an issue. Errata No. 3 Problem: When using external interrupts IRQ0 or IRQ1 in Cascade Mode, the acknowledge signal on INTA0 or INTA1 may be lost or truncated. Description: The acknowledge for IRQ0 or IRQ1 will be lost or truncated in Cascade Mode if another interrupt, with a higher priority setting (as configured in the interrupt control registers), occurs just before or during the acknowledge. This does not apply to interrupts generated by the DMA. This also does not apply when using the inherent priority settings (all interrupts configured with the same priority).
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 71 of 75 1-888-824-4184 Workaround: When using external interrupts in cascade mode, do not program other interrupts to have a high priority (except DMAs). When using both IRQ0 and IRQ1 in Cascade Mode they must be programmed to have the same priority level. Errata No. 4 Problem: Memory->Memory moves interrupted by two DMA cycles can corrupt data. Description: This problem occurs if Memory->Memory operation is interrupted by
2 DMA cycles with the following sequence:
- The instruction reads data from memory. 2. The first DMA cycle occurs. 3. The second DMA request occurs between 1 and 4 clocks after the falling edge of ALE for the deposit phase of the first DMA. 4. An instruction fetch occurs (this will be the data that shows up later). 5. The second DMA cycle occurs. 6. The write phase of the instruction happens with bad data (from step 4). If the second DMA request occurs earlier than 1 clock after ALE for the first DMA's deposit phase, step 4 will be preempted by the second DMA, and operation is correct. If the second DMA request occurs later than 4 clocks after ALE for the first DMA's deposit phase, the write phase will follow step 4 immediately, and operation is correct. Of the total 163 instructions, the following 8 are impacted by this issue, with both the 8 & 16 bit versions of the first 7 on the list being affected. 1. MOVS 2. PUSH mem 3. POP mem 4. INS 5. IN 6. OUTS 7. OUT 8. ENTER Workaround: If the conditions described above occur, there is no workaround. However, this DMA issue will be corrected in Revision 1 of the device.
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 72 of 75 1-888-824-4184 Errata No. 5 Problem: Bit 15 of RELREG (offset 0xFE) behaves differently than Intel device. Description: For both 188 and 186 devices, an ESC opcode will generate a type 7 interrupt only when RELREG[15] is a 0. Workaround: Initialize RELREG[15] to 0 if a type 7 interrupt is desired. Errata No. 6 Problem: Enhanced mode makes bit 15 of RELREG (offset 0xFE) read-only. Description: If the device comes out of reset in enhanced mode, RELREG[15] will be set to a Workaround: Avoid enhanced mode if a type 7 interrupt is desired. Errata No. 7 Problem: Sbus deasserts on the wrong edge of CLKOUT. Description: The sbus goes inactive (high) at the end of a bus cycle on the falling edge of CLKOUT. It should be on the rising edge of CLKOUT. Workaround: None. Errata No. 8 Problem: Timer2 count register must be written to enable counting. Description: If timer 2 count register is not explicitly written timer 2 will not count; this can also prevent timers 0 & 1 from counting if timer 2 is used as a prescaler. Workaround: Write timer 2 count register before enabling timer 2.
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 73 of 75 1-888-824-4184 Errata No. 9 Problem: Non-maskable interrupt (NMI) can be pre-empted by maskable interrupt. Description: When instruction execution unit is in Decode state for 2 or more consecutive cycles and an NMI is recognized, it could be pre-empted by a maskable interrupt. Workaround: None. Errata No. 10 Problem: DMA can hang. Description: DMA to a region of memory using destination synchronization and a chip select with extra wait states can hang. Workaround: Do not use wait states and destination synchronization together. Errata No. 11 Problem: MOVS/POP/PUSH instructions interrupted by DMA can corrupt data. Description: MOVS/POP/PUSH instructions interrupted by both a DMA transaction and an instruction fetch bus cycle can corrupt data. This affects the IA186XL only. Workaround: None. Errata No. 12 Problem: MOVS/POP/PUSH instructions interrupted by DMA can corrupt data. Description: MOVS/PUSH/POP instructions with 16-bit, non-aligned destination address interrupted by DMA can corrupt data. This affects the IA186XL only. Workaround: None.
- Data Sheet Revision History
Table 25 presents the sequence of revisions to document IA211080711. Table 25. Data Sheet Revision History Instruction Set Timing; Added errata. Errata 4 to include more recent information.
IA186XL/IA188XL Data Sheet 16-Bit Microcontrollers July 6, 2011 IA211080711-09 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 75 of 75 1-888-824-4184 10. For Additional Information The Innovasic Semiconductor IA186XL and IA188XL microcontrollers are form, fit, and function replacements for the original Intel 80C186XL and 80C188XL 16-bit high-integration embedded processors. The Innovasic Support Team wants our information to be complete, accurate, useful, and easy to understand. Please feel free to contact our experts at Innovasic at any time with suggestions, comments, or questions. Innovasic Support Team
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