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Technical content

Features

  • Precision Multiphase Core V oltage Regulation - Differential Remote V oltage Sensing - 0.5% System Accuracy Over Life, Load, Line and Temperature - Adjustable Precision Re ference-V oltage Offset
  • Precision R DS(ON) or DCR Current Sensing - Accurate Load-Line Programming - Accurate Channel-Current Balancing - Differential Current Sense
  • Microprocessor V oltage Identification Input - VID V oltage Scaling Technology - 8-Bit VID Input with Selectable VR11 Code and Extended VR10 Code at 6.25mV per Bit - 0.5V to 1.6V Operation Range
  • Thermal Sensing
  • Integrated Programmable Temperature Compensation
  • Threshold-Sensitive Enable Function for Power Sequencing and VTT Enable
  • Overcurrent Protection
  • Overvoltage Protection
  • 2-, 3- or 4-Phase Operation
  • Adjustable Switching Freque ncy Up to 1MHz Per Phase
  • Package Option - QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - QFN Near Chip Scale Package Footprint; Improves PCB Efficiency, Thinner in Profile
  • Pb-Free (RoHS Compliant)

09614 March 14, 2014 Rev A

EC7401QI 4-Phase PWM Controller with 8-bit DAC Code March 2014 Altera Corporation

Ordering Information

(Note) PART MARKING TEMP. (°C) PACKAGE (Pb-Free) PKG . DWG. # EC7401QI EC7401 -40 to +85 40 Ld 6x6 QFN L40.6x6 *Add “-T” suffix for tape and reel. NOTE: These Altera Enpirion Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

EC7401QI 4-Phase PWM Controller with 8-bit DAC CodeMarch 2014 Altera Corporation Pin Configuration EC7401QI (40 LD QFN) TOP VIEW TSEN POK FAN HOT FSW VID7 EN_VTT EN_PWR V DIFF VCC PWM3 ISEN3+ ISEN3- ISEN2- ISEN2+ PWM2 PWM4 ISEN4+ ISEN4- ISEN1- ISEN1+ TCOMP VSEN VGND SS PWM1 IDROOP REF COMP VFB 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 VID5 VID4 VID3 VID2 VID1 VRSEL DAC VID0 OFSET VID6 GND

EC7401QI 4-Phase PWM Controller with 8-bit DAC Code March 2014 Altera Corporation EC7401QI Block Diagram I_TRIP CHANNEL POWER-ON RESET (POR) PWM1 PWM2 PWM3 PWM4 VCC VFB FSW CLOCK AND VID5 VID4 VID3 VID2 COMP VSEN GENERATOR SAWTOOTH ISEN3- ISEN4+ VID1 VGND VDIFF POK OVP EN_PWR 0.875V I_AVG VID Voltage Scaling D/A CURRENT BALANCE CHANNEL DETECT OFSET THREE-STATE ISEN1+ ISEN2-CHANNEL CURRENT SENSE VID0 SOFT-START AND FAULT LOGIC OFFSET REF +175mV E/A OC PWM PWM PWM PWM EN_VTT DAC ISEN4- ISEN3+ ISEN2+ ISEN1- IDROOP 0.875V VID6 VID7 VRSEL GNDTCOMP GAIN TSEN HOT FAN TEMPERATURE COMPENSATION N THERMAL MONITORING COMPENSATION THERMAL SS

EC7401QI 4-Phase PWM Controller with 8-bit DAC CodeMarch 2014 Altera Corporation Typical Application - 4-Phase Buck Converter with DCR Sensing and External TCOMP VFB EC7401QI COMP REF IDROOP VDIFF VSEN VGND EN_VTT POK VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL FAN HOT TSEN TCOMP OFSET FSW SS EN_PWR ISEN4- ISEN4+ PWM4 ISEN3- ISEN3+ PWM3 ISEN2- ISEN2+ PWM2 ISEN1- ISEN1+ PWM1 DAC VCC 12V NTC VIN VCC VCC_GD ET4040QI PWM PHASE BOOT ISEN REFIN BGND AGND PGND SW 12V 3.3V 1.8V VIN VCC VCC_GD ET4040QI PWM PHASE BOOT ISEN REFIN BGND AGND PGND SW 12V 3.3V 1.8V VIN VCC VCC_GD ET4040QI PWM PHASE BOOT ISEN REFIN BGND AGND PGND SW 12V 3.3V 1.8V VIN VCC VCC_GD ET4040QI PWM PHASE BOOT ISEN REFIN BGND AGND PGND SW 12V 3.3V 1.8V LOAD GND

EC7401QI 4-Phase PWM Controller with 8-bit DAC Code March 2014 Altera Corporation Absolute Maximum Ratings ESD Ratings Operating Conditions Ambient Temperature Thermal Information Thermal Resistance (Notes 1, 2) JA (°C/W) JC (°C/W) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1.  JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VCC SUPPLY CURRENT VCC = 5VDC; EN_PWR = 5VDC; RT = 100k ISEN1 = ISEN2 = ISEN3 = ISEN4 = -70µA -1 5 2 0 m A VCC = 5VDC; EN_PWR = 0VDC; RT = 100k -1 0 1 2 m A POR Threshold VCC Rising 4.3 4.5 4.7 V VCC Falling 3.7 3.9 4.2 V EN_PWR Threshold Nominal Supply 0.850 0.875 0.910 V Shutdown Supply - 130 - mV POWER-ON RESET AND ENABLE EN_VTT Threshold Rising 0.850 0.875 0.910 V Hysteresis - 130 - mV Falling 0.720 0.745 0.775 V REFERENCE VOLTAGE AND DAC System Accuracy of EC7401QI (VID = 1V to 1.6V , T J = -40°C to +85°C) (Note 3) -0.6 - 0.6 %VID System Accuracy of EC7401QI (VID = 0.5V to 1V , T J = -40°C to +85°C) (Note 3) -1 - 1 %VID VID Pull-up -60 -40 -20 µA VID Input Low Level -- 0 . 4 V VID Input High Level 0.8 - - V VRSEL Input Low Level -- 0 . 4 V VRSEL Input High Level 0.8 - - V DAC Source Current -47 m A DAC Sink Current - - 300 µA

EC7401QI 4-Phase PWM Controller with 8-bit DAC CodeMarch 2014 Altera Corporation REF Source Current 45 50 55 µA REF Sink Current 45 50 55 µA PIN-ADJUSTABLE OFFSET V oltage at OFSET Pin of EC7401QI Offset resistor connected to ground 388 400 412 mV V oltage below VCC, offset resistor connected to VCC 1.552 1.600 1.648 V OSCILLATORS Accuracy of Switching Frequency Setting RT = 100k 225 250 275 kHz Adjustment Range of Switching Frequency (Note 4) 0.08 - 1.0 MHz Soft-Start Ramp Rate R S = 100k(Notes 5, 6) - 1.563 - mV/µs Adjustment Range of Soft-start Ramp Rate (Note 4) 0.625 - 6.25 mV/µs PWM GENERA TOR Sawtooth Amplitude -1 . 5- V Max Duty Cycle -6 6 . 7- % ERROR AMPLIFIER Open-Loop Gain RL = 10k to ground (Note 4) -9 6- d B Open-Loop Bandwidth C L = 100pF, RL = 10k to ground (Note 4) -2 0- M H z Slew Rate C L = 100pF - 9 - V/µs Maximum Output V oltage 3.8 4.3 4.9 V Output High V oltage @ 2mA 3.6 - - V Output Low V oltage @ 2mA -- 1 . 2 V REMOTE-SENSE AMPLIFIER Bandwidth (Note 4) -2 0- M H z Output High Current VSEN - VGND = 2.5V -500 - 500 µA Output High Current VSEN - VGND = 0.6 -500 - 500 µA PWM OUTPUT PWM Output V oltage LOW Threshold I LOAD = ±500µA - - 0.5 V PWM Output V oltage HIGH Threshold I LOAD = ±500µA 4.3 - - V SENSE CURRENT OUTPUT (IDROOP and IOUT) Sensed Current Tolerance ISEN1 = ISEN2 = ISEN3 = ISEN4 = 80µA 76 80 84 µA Overcurrent Trip Level 90 100 110 µA Maximum V oltage at IDROOP Pin - 2 - V THERMAL MONITORING AND FAN CONTROL TSEN Input V oltage for FAN Trip 1.6 1.65 1.69 V TSEN Input V oltage for FAN Reset 1.89 1.93 1.98 V TSEN Input V oltage for HOT Trip 1.35 1.4 1.44 V TSEN Input V oltage for HOT Reset 1.6 1.65 1.69 V Leakage Current of FAN With externally pull-up resistor connected to VCC - - 30 µA Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

EC7401QI 4-Phase PWM Controller with 8-bit DAC Code March 2014 Altera Corporation FAN Low V oltage With 1.25k resistor pull-up to VCC, IFAN = 4mA - - 0.3 V Leakage Current of HOT With externally pull-up resistor connected to VCC - - 30 µA HOT Low V oltage With 1.25k resistor pull-up to VCC, IHOT = 4mA - - 0.3 V VR READY AND PROTECTION MONITORS Leakage Current of POK With externally pull-up resistor connected to VCC - - 30 µA POK Low V oltage IPOK = 4mA - - 0.3 V Undervoltage Threshold VDIFF Falling 48 50 52 %VID POK Reset V oltage VDIFF Rising 58 60 62 %VID Overvoltage Protection Threshold Before valid VID 1.250 1.275 1.300 V After valid VID, the voltage above VID 150 175 200 mV Overvoltage Protection Reset Threshold 0.38 0.40 0.42 V NOTES: 3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included. 4. Limits established by characterization and are not production tested. 5. During soft-start, VDAC rises from 0 to 1.1V first an d then ramp to VID voltage after receiving valid VID. 6. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle. Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

EC7401QI 4-Phase PWM Controller with 8-bit DAC CodeMarch 2014 Altera Corporation Functional Pin Description VCC Supplies the power necessary to operate the chip. The controller starts to operate when the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold. Connect this pin directly to a +5V supply. GND Bias and reference ground for the IC. The bottom metal base of EC7401QI is the GND. EN_PWR This pin is a threshold-sensitive enable input for the controller. Connecting the 12V supply to EN_PWR through an appropriate resistor divider provides a means to synchronize power-up of the controller and the MOSFET driver ICs. When EN_PWR is driven above 0.875V , the EC7401QI is active depending on status of EN_VTT, the internal POR, and pending fault states. Driving EN_PWR below 0.745V will clear all fault states and prime the EC7401QI to soft-start when re-enabled. EN_VTT This pin is another threshold-sensitive enable input for the controller. It’s typically connected to VTT output of VTT voltage regulator in the computer mother board. When EN_VTT is driven above 0.875V , the EC7401QI is active depending on status of ENLL, the internal POR, and pending fault states. Driving EN_VTT below 0.745V will clear all fault states and prime the EC7401QI to soft-start when re-enabled. FSW Use this pin to set up the desired switching frequency. A resistor, placed from FSW to ground will set the switching frequency. The relationship between the value of the resistor and the switching frequency will be described by an approximate equation. SS Use this pin to set up the desired start-up oscillator frequency. A resistor, placed from SS to ground will set up the soft-start ramp rate. The relationship between the value of the resistor and the soft-start ramp-up time will be described by an approximate equation. VID7, VID6, VID5, VID4, VID3, VID2, VID1 and VID0 These are the inputs to the internal DAC that generates the reference voltage for output regulation. Connect these pins either to open-drain outputs with or without external pull-up resistors or to active pull-up outputs. All VID pins have 40µA internal pull-up current sources that diminish to zero as the voltage rises above the logic-high level. These inputs can be pulled up externally as high as VCC plus 0.3V . When an OFF VID code causes shut-down, the controller needs to be reset before it starts again. VRSEL Use this pin to select Internal VID code. When it is connected to GND, the extended VR10 code is selected. When it’s floated or pulled to high, VR11 code is selected. This input can be pulled up as high as VCC plus 0.3V . VDIFF, VSEN, and VGND VSEN and VGND form the precision differential remote-sense amplifier. This amplifier converts the differential voltage of the remote output to a single-ended voltage referenced to local ground. VDIFF is the amplifier’s output and the input to the regulation and protection circuitry. Connect VSEN and VGND to the sense pins of the remote load. VFB and COMP Inverting input and output of the error amplifier respectively. VFB can be connected to VDIFF through a resistor. A properly chosen resistor between VDIFF and VFB can set the load line (droop), when IDROOP pin is tied to VFB pin. The droop scale factor is set by the ratio of the ISEN resistors and the inductor DCR or the lower MOSFET RDS(ON). COMP is tied back to VFB through an external RC network to compensate the regulator. DAC and REF The DAC pin is the output of the precision internal DAC reference. The REF pin is the positive input of the Error Amplifier. In typical applications, a 1k, 1% resistor is used between DAC and REF to generate a precision offset voltage. This voltage is proportional to

EC7401QI 4-Phase PWM Controller with 8-bit DAC Code March 2014 Altera Corporation the offset current determined by the offset resistor from OFSET to ground or VCC. A capacitor is used between REF and ground to smooth the voltage transition during VID V oltage Scaling operations. PWM1, PWM2, PWM3, PWM4 Pulse width modulation outputs. Connect these pins to the PWM input pins of the Altera Enpirion driver IC. The number of active channels is determined by the state of PWM3 and PWM4. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation. ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-; ISEN4+ and ISEN4 The ISEN+ and ISEN- pins are current sense inputs to individual differential amplifiers. The sensed current is used for channel current balancing, overcurrent protection, and droop regulation. Inactive channels should have their respective current sense inputs left open (for example, open ISEN4+ and ISEN4- for 3-phase operation). For DCR sensing, connect each ISEN- pin to the node between the RC sense elements. Tie the ISEN+ pin to the other end of the sense capacitor through a resistor, RISEN. The voltage across the sense capacitor is proportional to the inductor current. Therefore, the sense current is proportional to the inductor current and scaled by the DCR of the inductor and RISEN. When configured for RDS(ON) current sensing, the ISEN1-, ISEN2-, ISEN3-, and ISEN4- pins are grounded at the lower MOSFET sources. The ISEN1+, ISEN2+, ISEN3+, and ISEN4+ pins are then held at a virtual ground. Therefore, a resistor, connected between these current sense pins and the drain terminals of the associated lower MOSFET, will carry the current proportional to the current flowing through that channel. The sensed current is determined by the negative voltage across the lower MOSFET when it is ON, which is the channel current scaled by RDS(ON) and RISEN. POK POK indicates that the soft-start is completed and the output voltage is within the regulated range around VID setting. It is an open-drain logic output. When OCP or OVP occurs, POK will be pulled to low. It will also be pulled low if the output voltage is below the undervoltage threshold. OFSET The OFSET pin provides a means to program a DC offset current for generating a DC offset voltage at the REF input. The offset current is generated via an external resistor and precision internal voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFSET pin should be left unterminated. TCOMP Temperature compensation scaling input. The voltage sensed on the TSEN pin is utilized as the temperature input to adjust ldroop and the overcurrent protection limit to effectively compensate for the temperature coefficient of the current sense element. To implement the integrated temperature compensation, a resistor divider circuit is needed with one resistor being connected from TCOMP to VCC of the controller and another resistor being connected from TCOMP to GND. Changing the ratio of the resistor values will set the gain of the integrated thermal compensation. When integrated temperature compensation function is not used, connect TCOMP to GND. IDROOP IDROOP is the output pin of sensed average channel current which is proportional to load current. In the application which does not require loadline, leave this pin open. In the application which requires load line, connect this pin to VFB so that the sensed average current will flow through the resistor between VFB and VDIFF to create a voltage drop which is proportional to load current. TSEN TSEN is an input pin for VR temperature measurement. Connect this pin through NTC thermistor to GND and a resistor to VCC of the controller. The voltage at this pin is reverse proportional to VR temperature. EC7401QI monitors the VR temperature based on the voltage at TSEN pin and outputs HOT and FAN signals. HOT HOT is used as an indication of high VR temperature. It is an open-drain logic output. It will be open when the measured VR temperature reaches a certain level. FAN FAN is an output pin with open-drain logic output. It will be open when the measured VR temperature reaches a certain level.

top level views of multiphase power conversion using the EC7401QI controller. The switching of each channel in a multiphase converter is timed to be symmetrically out of phase with each of the other channels. inductance and lower total output capacitance for any performance specification. for each phase is about 7A, and the DC components of the inductor currents combine to feed the load. individual channel’s peak-to-peak inductor current. FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR 3-

(ESR), and inductor ripple current. Reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. combining to reduce the total input ripple current. input capacitor solution. Figure 23 shows the single-phase input-capacitor RMS current for comparison. the channel firing order is 3-2-1. PWM3 is connected to VCC, two channel operation is selected and the PWM2 pulse terminates 1/2 of a cycle later. FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-CAPACITOR

beginning of the next cycle by triggering the PWM signal low. for current balance, load-line regulation, and overcurrent protection. FIGURE 3. SAMPLE AND HOLD TIMING

An inductor’s winding is characteristic of a distributed resistance as measured by the DCR (Direct Current Resistance) parameter. inductor, will also pass through the DCR. Equation 3 shows the s-domain equivalent voltage across the inductor VL. A simple RC network across the inductor extracts the DCR voltage, as shown in Figure 4. The voltage on the capacitor (VC) can be shown to be proportional to the channel current (IL) see Equation 4. the voltage across the capacitor (VC) is equal to the voltage drop across the DCR (i.e., proportional to the channel current). the current out of ISEN+ pin (ISEN) is proportional to the inductor current. loss on the current sense element (RSENSE). FIGURE 4. DCR SENSING CONFIGURATION

Equation 6 shows the ratio of the channel current to the sensed current (ISEN). The controller can also sense the channel load current by sampling the voltage across the lower MOSFET RDS(ON) (see Figure 6). Equation 7 shows the ratio of the channel current to the sensed current ISEN. described in “Temperature Compensation” on page 33. FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS FIGURE 6. MOSFET R DS(ON) CURRENT-SENSING CIRCUIT

force IER toward zero. The same method for error signal correction is applied to each active channel. power loss is equally dissipated over multiple devices and a greater area. specifies the guaranteed tolerance of the EC7401QI to include the combined tolerances of each of these elements. external circuitry, which control voltage regulation, are illustrated in Figure 8. FIGURE 7. CHANNEL 1 PWM FUNCTION AND CURRENT-BALANCE NOTE: *Channels 3 and 4 are optional for 2 or 3 phase designs.

error amplifier through an external resistor. A digital-to-analog converter (DAC) generates a reference voltage based on the state of logic signals at pins VID7 through VID0. the driving device is greater than 45µA. FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE REGULATION WITH

TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)

TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)

TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)

TABLE 2. VR11 VID 8 BIT

00000000 O F F

00000001 O F F

TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)

TABLE 2. VR11 VID 8 BIT (Continued)

TABLE 2. VR11 VID 8 BIT (Continued)

TABLE 2. VR11 VID 8 BIT (Continued)

TABLE 2. VR11 VID 8 BIT (Continued)

effectively be level shifted in a direction which works to achieve the load-line regulation required by these manufacturers. reduce the output-voltage spike that results from fast load-current demand changes. be sustained without crossing the upper specification limit. by combining Equation 8 with the appropriate sample current expression defined by the current sense method employed. the DCR, RDS(ON), or RSENSE depending on the sensing method.

11111110 O F F

11111111 O F F

TABLE 2. VR11 VID 8 BIT (Continued)

(RREF) is selected so that the product (IOFSET x ROFSET) is equal to the desired offset voltage. These functions are shown in Figure 9. transition within the DAC range of the processor without discontinuity or disruption is a necessary function of the core-voltage regulator. than the DAC (not recommended), the controller will execute 6.26mV step change six times per cycle until VID and DAC are equal. Therefore it is important to carefully control the rate of VID stepping in 1-bit increments. on page 27. The selection of CREF is based on the time duration for 1 bit VID change and the allowable delay time.

1.6 R REF

0.4 R REF

FIGURE 9. OUTPUT VOLTAGE OFFSET PROGRAMMING

network and TVID is given by Equation 13. begins soft-start. Once the output voltage is within the proper window of operation, POK asserts logic high. input conditions must be met before the EC7401QI is released from shutdown mode.

  1. The bias voltage applied at VCC must reach the internal power-on reset (POR) rising threshold. Once this threshold is reached,
  2. The EC7401QI features an enable input (EN_PWR) for power sequenc ing between the controller bias voltage and another

family of MOSFET drivers, which require 12V bias.

  1. The voltage on EN_VTT must be higher than 0.875V to enable th e controller. This pin is typically connected to the output of

or EN_VTT is needed to restart. FIGURE 10. POWER SEQUENCING USING THRESHOLD-SENSITIVE

second soft-start ramp until the voltage reaches the VID voltage minus offset voltage. The soft-start time is the sum of the 4 periods as shown in Equation 14. soft-start ramp time TD4 will be 256µs. monitors. The schematic in Figure 12 outlines the interaction between the fault monitors and the POK signal. EN_PWR, EN_VTT, POR, or VID OFF-code. FIGURE 11. SOFT-START WA VEFORMS

OVP threshold is 1.275V . Once the controller detects valid VID input, the OVP trip point will be changed to VID plus 175mV . Two actions are taken by the EC7401QI to protect the microprocessor load when an overvoltage condition occurs. to protect the load in this fashion as long as the overvoltage condition occurs. basis, while the combined phase currents are protected on an instantaneous basis. a comparator triggers the converter to shutdown. FIGURE 12. POK AND PROTECTION CIRCUITRY

comparator triggers the converter to shutdown. FIGURE 13. OVERCURRENT BEHAVIOR IN HICCUP MODE. FSW =

open-drain outputs, and external pull-up resistors are required. consumption. HOT signal may be tied to the CPU’s PROC_HOT signal. pulled to GND when TSEN voltage goes back to above 33% of VCC voltage. Figure 16 shows the operation of those signals. FIGURE 14. BLOCK DIAGRAM OF THERMAL MONITORING FIGURE 15. THE RATIO OF TSEN VOLTAGE TO NTC TEMPERATURE

RNTC(T3) is the NTC resistance at the HOT threshold temperature T3. inductor DCR or MOSFET RDS(ON). component. EC7401QI provides two methods: integrated temperature compensation and external temperature compensation. compensate the temperature impact on the sensed current. The block diagram of this function is shown in Figure 17. FIGURE 16. HOT AND FAN SIGNAL vs TSEN VOLTAGE

Based on VCC voltage, EC7401QI converts the TSEN pin voltage to a 6-bit TSEN digital signal for temperature compensation. Depending on the location of the NTC and the airflow, the NTC may be cooler or hotter than the current sense component. voltage, EC7401QI converts the TCOMP pin voltage to a 4-bit TCOMP digital signal as TCOMP factor N. larger the difference between the NTC temperature and the temperature of the current sense component.

  1. Properly choose the voltage divider for TSEN pin to match the TSEN voltage VS temperature curve with the recommended
  2. Run the actual board under the full load and the desired cooling condition.
  3. After the board reaches the thermal steady state, record the temperature (T CSC) of the current sense component (inductor or

MOSFET) and the voltage at TSEN and VCC pins.

  1. Use Equation 20 to calculate the resistance of the TSEN NTC, and find out the corresponding NTC temperature TNTC from the

FIGURE 17. BLOCK DIAGRAM OF INTEGRATED TEMPERATURE

  1. Use Equation 21 to calculate the TCOMP factor N:
  2. Choose an integral number close to the above result for the TCOMP factor. If this factor is higher than 15, use N = 15. If it is
  3. Choose the pull-up resistor R TC1 (typical 10k).
  4. If N = 15, do not need the pull-down resistor R TC2, otherwise obtain RTC2 by Equation 22:
  5. Run the actual board under full lo ad again with the proper resistors connected to the TCOMP pin.
  6. Record the output voltage as V1 immediately after the output voltage is stable with the full load. Record the output voltage as

V2 after the VR reaches the thermal steady state.

  1. If the output voltage increases over 2m V as the temperature increases, i.e. V2 - V1 > 2mV , reduce N and redesign RTC2; if the

output voltage decreases over 2mV as the temperature increases, i.e. V1 - V2 > 2mV , increase N and redesign RTC2. The design spreadsheet is available for those calculations. temperature compensation network, shown in Figure 18, can be used to cancel the temperature impact on the droop (i.e. load line). and VDIFF pins. If RFB resistance reduces as the temperature increases, the temperature impact on the droop can be compensated. FIGURE 18. VOLTAGE AT IDROOP PIN WITH A RESISTOR PLACED

EC7401QI 4-Phase PWM Controller with 8-bit DAC Code March 2014 Altera Corporation General Design Guide This design guide is intended to provide a high-level explanation of the steps necessary to create a multiphase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. Power Stages The first step in designing a multiphase converter is to determine the number of phases. This determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board; whether through-hole components are permitted; and the total board space available for power-supply circuitry. Generally speaking, the most economical solutions are those in which each phase handles between 15A and 20A. All surface-mount designs will tend toward the lower end of this current range. If through-hole MOSFETs and inductors can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, inductors and heat-dissipating surfaces. MOSFETs The choice of MOSFETs depends on the current each MOSFET will be required to conduct; the switching frequency; the capability of the MOSFETs to dissipate heat; and the availability and nature of heat sinking and air flow. LOWER MOSFET POWER CALCULATION The calculation for heat dissipated in the lower MOSFET is simple, since virtually all of the heat loss in the lower MOSFET is due to current conducted through the channel resistance (RDS(ON)). In Equation 23, IM is the maximum continuous output current; IPP is the peak-to-peak inductor current (see Equation 1); d is the duty cycle (VOUT/VIN); and L is the per-channel inductance. An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage at IM, VD(ON); the switching frequency, fSW; and the length of dead times, td1 and td2, at the beginning and the end of the lower- MOSFET conduction interval respectively. Thus the total maximum power dissipated in each lower MOSFET is approximated by the summation of PLOW,1 and PLOW,2. UPPER MOSFET POWER CALCULATION In addition to RDS(ON) losses, a large portion of the upper-MOSFET losses are due to currents conducted across the input voltage (VIN) during switching. Since a substantially higher portion of the upper-MOSFET losses are dependent on switching frequency, the power calculation is more complex. Upper MOSFET losses can be divided into separate components involving the upper- MOSFET switching times; the lower-MOSFET body-diode reverse-recovery charge (Qrr) and the upper MOSFET RDS(ON) conduction loss. When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 25, the required time for this commutation is t1 and the approximated associated power loss is PUP,1. At turn on, the upper MOSFET begins to conduct and this transition occurs over a time t2. In Equation 26, the approximate power loss is PUP,2. PLOW 1 RDS ON IM  2 1d– ILP - P, 2 1d– PLOW 2 VDO N fSW IM  td1 IM IP-P  t d2+= (EQ. 24) PUP 1, VIN IM IP-P  t1 2----  f SW (EQ. 25) PUP 2, VIN IM IP-P  t 2----  f SW (EQ. 26)

EC7401QI 4-Phase PWM Controller with 8-bit DAC CodeMarch 2014 Altera Corporation A third component involves the lower MOSFET’s reverse-recovery charge (Qrr). Since the inductor current has fully commutated to the upper MOSFET before the lower-MOSFET’s body diode can draw all of Qrr, it is conducted through the upper MOSFET across VIN. The power dissipated as a result is PUP ,3 and is approximately Finally, the resistive part of the upper MOSFET’s is given in Equation 28 as PUP,4. The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 25, 26, and 27. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive solutions to the loss equations for different MOSFETs and different switching frequencies. Current Sensing Resistor The resistors connected between these pins and the respective phase nodes determine the gains in the load-line regulation loop and the channel-current balance loop as well as setting the overcurrent trip point. Select values for these resistors based on the room temperature RDS(ON) of the lower MOSFETs, DCR of inductor or additional resistor; the full-load operating current, IFL; and the number of phases, N using Equation 29. In certain circumstances, it may be necessary to adjust the value of one or more ISEN resistor. When the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channels run hotter than desired, choose new, smaller values of RISEN for the affected phases (see the section entitled “Channel-Current Balance” on page 16). Choose RISEN2 in proportion to the desired decrease in temperature rise in order to cause proportionally less current to flow in the hotter phase. In Equation 30, make sure that T2 is the desired temperature rise above the ambient temperature, and T1 is the measured temperature rise above the ambient temperature. While a single adjustment according to Equation 30 is usually sufficient, it may occasionally be necessary to adjust RISEN two or more times to achieve optimal thermal balance between all channels. Load-Line Regulation Resistor The load-line regulation resistor is labelled RFB in Figure 8. Its value depends on the desired full load droop voltage (VDROOP in Figure 8). If Equation 29 is used to select each ISEN resistor, the load-line regulation resistor is as shown in Equation 31. If one or more of the ISEN resistors is adjusted for thermal balance, as in Equation 30, the load-line regulation resistor should be selected according to Equation 32 where IFL is the full-load operating current and RISEN(n) is the ISEN resistor connected to the nth ISEN pin. Compensation The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in Load-Line Regulation, there are two distinct methods for achieving these goals. COMPENSATING LOAD-LINE REGULATED CONVERTER The load-line regulated converter behaves in a similar manner to a peak-current mode controller because the two poles at the output-filter LC resonant frequency split with the introduction of current information into the control loop. The final location of PUP 3, VIN Qrr fSW= (EQ. 27) PUP 4, rDS ON IM  2 d IP-P RISEN RX 70 10 6– IFL RISEN 2, RISEN T2 T1 RFB VDROOP 70 10 6– RFB VDROOP IFL rDS ON n = (EQ. 32)

voltage-mode approximation yields a solution that is always stable with very close to ideal transient performance. separate set of equations for the compensation components. signal amplitude as described in Figure 7 and “Electrical Specifications” on page 6. FIGURE 19. COMPENSATION CONFIGURATION FOR

0.75 VIN

2 VP-P RFB LC

value of CC from Equation 33 unless some performance issue is noted. frequency and a zero at the ESR frequency. A type III controller, as shown in Figure 20, provides the necessary compensation. lower than 10f0 can cause problems with too much phase shift below the system bandwidth. is selected arbitrarily. The remaining compensation components are then selected according to Equation 34. signal amplitude as described in Figure 7 and “Electrical Specifications” on page 6. FIGURE 20. COMPENSATION CIRCUIT FOR EC7401QI BASED

0.75 VIN 2fHF LC 1–

EC7401QI 4-Phase PWM Controller with 8-bit DAC Code March 2014 Altera Corporation Output Filter Design The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response. The output capacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, I; the load-current slew rate, di/dt; and the maximum allowable output-voltage deviation under transient loading, VMAX. Capacitors are characterized according to their capacitance (ESR) and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total output-voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount: The filter capacitor must have sufficiently low ESL and ESR so that V < VMAX. Most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current (see “Interleaving” on page 11 and Equation 2), a voltage develops across the bulk-capacitor ESR equal to IC,P-P (ESR). Thus, once the output capacitors are selected, the maximum allowable ripple voltage, VP-P(MAX), determines the lower limit on the inductance. Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than VMAX. This places an upper limit on inductance. Equation 37 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. Equation 38 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the per-channel inductance, C is the total output capacitance, and N is the number of active channels. Switching Frequency There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper- MOSFET loss calculation. These effects are outlined in “MOSFETs” on page 36, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small output-voltage ripple as outlined in “Output Filter Design” on page 40. Choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. Switching frequency is determined by the selection of the frequency-setting resistor, R T (see the figure labelled Typical Application on page 5). Equation 39 is provided to assist in selecting the correct value for RT. V ESL di dt-----E S R  I+ (EQ. 35) L ESR VIN NV OUT–  VOUT fSW VIN VPP MAX L 2NCV O L 1.25 NC  (EQ. 38) (EQ. 39)RT 2.5X10 10 fSW

related to duty cycle and the number of active phases. FIGURE 21. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs FIGURE 22. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs

a ripple current rating which will minimize the total number of input capacitors required to support the RMS current calculated. The voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage. approach to selecting the bulk capacitor type and number as described above. phases are added to keep the component cost down relative to the single phase approach. not be overlooked during the layout process. of these components for each phase. drain. Place the bulk input capacitors as close to the upper MOSFET drains as dictated by the component size and dimensions. FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs

EC7401QI 4-Phase PWM Controller with 8-bit DAC CodeMarch 2014 Altera Corporation The EC7401QI can be placed off to one side or centered relative to the individual phase switching components. Routing of sense lines and PWM signals will guide final placement. Critical small signal components to place close to the controller include the ISEN resistors, RT resistor, feedback resistor, and compensation components. Bypass capacitors for the EC7401QI and ISL66XX driver bias supplies must be placed next to their respective pins. Trace parasitic impedances will reduce their effectiveness. Plane Allocation and Routing Dedicate one solid layer, usually a middle layer, for a ground plane. Make all critical component ground connections with vias to this plane. Dedicate one additional layer for power planes; breaking the plane up into smaller islands of common voltage. Use the remaining layers for signal wiring. Route phase planes of copper filled polygons on the top and bottom once the switching component placement is set. Size the trace width between the driver gate pins and the MOSFET gates to carry 4A of current. When routing components in the switching path, use short wide traces to reduce the associated parasitic impedances. Document Revision History The table lists the revision history for this document. Date Version Changes March 2014 1.0 Initial release.

EC7401QI 4-Phase PWM Controller with 8-bit DAC CodeMarch 2014 Altera Corporation Package Outline Drawing L40.6x6

40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 3, 10/06 located within the zone indicated. The pin #1 identifier may be Unless otherwise specified, tolerance : Decimal ± 0.05 Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. Dimension b applies to the metallized terminal and is meas ured Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. either a mold or mark feature. Dimensions are in millimeters.1. NOTES: (4X) 0.15 INDEX AREA PIN 1 A6.00 B6.00 36X 0.50 4.54X

40 PIN #1 INDEX AREA

40X 0 . 4 ± 0 . 1 B0.10 MAC 4 . 10 ± 0 . 15 0 . 90 ± 0 . 1 C SEATING PLANE BASE PLANE 0.08 0.10 SEE DETAIL "X" C C 0 . 00 MIN. DETAIL "X" 0 . 05 MAX. 0 . 2 REFC 5 SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN ( 5 . 8 TYP ) ( 4 . 10 ) ( 36X 0 . 5 ) ( 40X 0 . 23 ) ( 40X 0 . 6 ) TOP VIEW 0 . 23 +0 . 07 / -0 . 05