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Document overview

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Technical content

Features

  • Input V oltage Range: 3.3V to 25V
  • Output V oltage Range: 0.5V to 5V
  • Precision Regulation - Frequency Control Loop - ±0.5% System Accuracy Over -10°C to +100°C
  • Optimal Transient Response
  • Output Remote Sense
  • Extremely Flexible Output V oltage Programmability - 2-Bit VS Selects Four Independent Setpoint V oltages - Simple Resistor Programming of Setpoint V oltages
  • Selectable 300kHz, 500kHz, 600kHz or 1MHz PWM Frequency in Continuous Conduction
  • Automatic Diode Emulation Mode for Highest Efficiency
  • Power-OK Monitor for Soft-Start and Fault Detection

Applications

  • FPGA power
  • Digital processor power
  • Mixed-signal ASIC power

FIGURE 1. EC7100VQI APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT SENSE

09613 March 14, 2014 Rev A

EC7100VQI PWM DC/DC Controller with VS Inputs for FPGA Power Regulator March 2014 Altera Corporation

Ordering Information

(Note 2) PART MARKING TEMP RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # EC7100VQI (Note 1) 7100 -10 to +100 20 Ld 3x4 QFN L20.3x4 NOTES: 1. These Altera Enpirion Pb-free plastic pack aged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering oper- ations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FIGURE 2. EC7100VQI APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND RESISTOR CURRENT SENSE

FIGURE 3. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF EC7100VQI

EC7100VQI PWM DC/DC Controller with VS Inputs for FPGA Power Regulator March 2014 Altera Corporation Pin Configurations EC7100VQI (20 LD 3X4 QFN) TOP VIEW 10VSNS 9OCP 8FB 7SET2 4SREF 3VS0

20 PGND

19 LGATE

18 AVIN1

17 AVIN2

EC7100VQI PWM DC/DC Controller with VS Inputs for FPGA Power RegulatorMarch 2014 Altera Corporation EC7100VQI Functional Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1N SNS Negative remote sense input of VOUT. If resistor divider consisting of RFB and ROFS is used at FB pin, the same resistor divider should be used at NSNS pin, i.e. keep RFB1=RFB, and ROFS1=ROFS. 2V S1 Logic input for setpoint voltage selector. Use in conjunction with the VS0 pin to select among four setpoint reference voltages. 3V S0 Logic input for setpoint voltage selector. Use in conjunction with the VS1 pin to select among four setpoint reference voltages. 4S REF Soft-start and voltage slew-rate programming capacitor input and setpoint reference voltage programming resistor input. Connects internally to the inverting input of the VSET voltage setpoint amplifier. 5S ET0 V oltage set-point programming resistor input. 6S ET1 V oltage set-point programming resistor input. 7S ET2 V oltage set-point programming resistor input. 8F B V oltage feedback sense input. Connects internally to the inverting input of the control-loop error transconductance amplifier. The converter is in regulation when the voltage at the FB pin equals the voltage on the SREF pin. 9O CP Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor ROCP connects from this pin to the sense node. 10 VSNS Output voltage sense input for the modulator. The VSNS pin also serves as the reference input for the overcurrent detection circuit. 11 FSW Input for programming the regulator switching frequency. Pull this pin to A VIN2 for 1MHz switching. Pull this pin to GND with a 100k resistor for 600kHz switching. Leave this pin floating for 500kHz switching. Pull this pin directly to GND for 300kHz switching. 12 POK Power-OK open-drain indicator output. This pin changes to high impedance when the converter is able to supply regulated voltage. 13 EN Enable input for the IC. Pulling EN above the rising threshold voltage initializes the soft-start sequence.

14 SW Return current path for the UGATE high-side MOSFET driver, VIN sense input for the modulator, and

inductor current polarity detector input. 15 UGATE High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET of the converter. 16 BOOT Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally connected to the cathode of the Schottky boot-strap diode. Connect an MLCC between the BOOT pin and the SW pin. 17 AVIN2 Input for the IC bias voltage. Connect +5V to the A VIN2 pin and decouple with at least a MLCC to the GND pin. 18 AVIN1 Input for the LGATE and UGATE MOSFET driver circuits. The A VIN1 pin is internally connected to the anode of the Schottky boot-strap diode. Connect +5V to the A VIN1 pin and decouple with a MLCC to the PGND pin. 19 LGATE Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of the converter. 20 PGND Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET. Bottom Pad GND IC ground for bias supply and signal reference.

EC7100VQI PWM DC/DC Controller with VS Inputs for FPGA Power Regulator March 2014 Altera Corporation Absolute Maximum Ratings Thermal Information EN, SET0, SET1, SET2, VSNS, VS0, VS1, FB, NSNS, OCP, SREF . . -0.3V to GND, A VIN2 + 0.3V BOOT V oltage (V -0.3V to 9V (<10ns) GND -8V (<20ns Pulse Width, 10µJ) VSW - 5V (<20ns Pulse Width, 10µJ) to VBOOT ESD Rating Thermal Resistance (Typical) JA (°C/W) JC (°C/W) Operating Temperature Range: Recommended Operating Conditions Ambient Temperature Range: CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 2.  JA is measured with the component mounted on a high effective thermal conductivity test board in free air. 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. 4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. temperature range, -40°C to +100°C, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNIT A VIN2 and A VIN1 A VIN2 Input Bias Current IAVIN2 EN = 5V , A VIN2 = 5V , FB = 0.55V , SREF < FB -1 . 2 1 . 9 m A A VIN2 Shutdown Current IAVIN2off EN = GND, A VIN2 = 5V -0 1 . 0 µ A A VIN1 Shutdown Current IAVIN1off EN = GND, A VIN1 = 5V -0 1 . 0 µ A A VIN2 POR THRESHOLD Rising A VIN2 POR Threshold V oltage VAVIN2_THR 4.40 4.52 4.60 V Falling A VIN2 POR Threshold V oltage VAVIN2_THF 4.10 4.22 4.35 V REGULATION System Accuracy VS0 = VS1 = A VIN2, PWM Mode = CCM -0.5 - +0.5 % VS0 = VS1 = A VIN2, PWM Mode = CCM -0.75 +0.5 % PWM Switching Frequency Accuracy FSW PWM Mode = CCM -15 - +15 % PWM Mode = CCM -22 - +15 % VSNS VSNS Input Impedance RVSNS EN = 5V -6 0 0- k  VSNS Reference Offset Current IVSNS VENTHR < EN, SREF = Soft-Start Mode -8 . 5-µ A VSNS Input Leakage Current IVSNSoff EN = GND, VSNS = 3.6V -0- µ A

EC7100VQI PWM DC/DC Controller with VS Inputs for FPGA Power RegulatorMarch 2014 Altera Corporation ERROR AMPLIFIER FB Input Bias Current IFB EN = 5V , FB = 0.50V -20 - +50 nA SREF (Note 5) Soft-Start Current ISS SREF = Soft-Start Mode 8.5 17 25.5 µA V oltage Step Current IVS SREF = Setpoint-Stepping Mode ±51 85 ±119 µA SREF = Setpoint-Stepping Mode ±46 ±85 ±127 µA POWER OK POK Pull-down Impedance RPOK POK = 5mA Sink -5 0 1 5 0 W POK Leakage Current IPOK POK = 5V -0 . 1 1 . 0 µ A GA TE DRIVER UGATE Pull-Up Resistance RUGPU 200mA Source Current -1 . 1 1 . 7 W UGATE Source Current IUGSRC UGATE - SW = 2.5V -1 . 8- A UGATE Sink Resistance RUGPD 250mA Sink Current -1 . 1 1 . 7 W UGATE Sink Current IUGSNK UGATE - SW = 2.5V -1 . 8- A LGATE Pull-Up Resistance RLGPU 250mA Source Current -1 . 1 1 . 7 W LGATE Source Current ILGSRC LGATE - GND = 2.5V -1 . 8- A LGATE Sink Resistance RLGPD 250mA Sink Current -0 . 5 5 1 . 0W LGATE Sink Current ILGSNK LGATE - PGND = 2.5V -3 . 6- A UGATE to LGATE Deadtime tUGFLGR UGATE falling to LGATE rising, no load -2 1- n s LGATE to UGATE Deadtime tLGFUGR LGATE falling to UGATE rising, no load -2 1- n s SW SW Input Impedance RSW -3 3-k  BOOTSTRAP DIODE Forward V oltage VF AV I N 1 = 5 V, IF = 2mA -0 . 5 8- V Reverse Leakage IR VR = 25V -0- µ A CONTROL INPUTS EN High Threshold V oltage VENTHR 2.0 - - V EN Low Threshold V oltage VENTHF -- 1 . 0 V EN Input Bias Current IEN EN = 5V 0.85 1.7 2.55 µA EN Leakage Current IENoff EN = GND -0 1 . 0 µ A VS<0,1> High Threshold V oltage VVSTHR 0.65 - - V VS<0,1> Low Threshold V oltage VVSTHF -- 0 . 5 V VS<0,1> Input Bias Current IVS EN = 5V -0 . 5-µ A VS<0,1> Leakage Current IVIDoff EN=0V -0- µ A PROTECTION OCP Threshold V oltage VOCPTH VOCP - VSNS -1.75 - 1.75 mV temperature range, -40°C to +100°C, unless otherwise stated. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNIT

EC7100VQI PWM DC/DC Controller with VS Inputs for FPGA Power Regulator March 2014 Altera Corporation Theory of Operation The following sections will provide a detailed description of the inner workings of the EC7100VQI. Power-On Reset The IC is disabled until the voltage at the A VIN2 pin has increased above the rising power-on reset (POR) threshold voltage VAVI N 2_ T HR. The controller will become disabled when the voltage at the A VIN2 pin decreases below the falling POR threshold voltage VAV I N 2 _ T H F. The POR detector has a noise filter of approximately 1µs. Start-Up Timing Once A VIN2 has ramped above VA VIN2_THR, the controller can be enabled by pulling the EN pin voltage above the input-high threshold VENTHR. Approximately 20µs later, the voltage at the SREF pin begins slewing to the designated VS set-point. The converter output voltage at the FB feedback pin follows the voltage at the SREF pin. During soft-start, The regulator always operates in CCM until the soft-start sequence is complete. Start-Up and V oltage-Step Operation When the voltage on the A VIN2 pin has ramped above the rising power-on reset voltage VAV I N 2 _ T H R, and the voltage on the EN pin has increased above the rising enable threshold voltage VENTHR, the SREF pin releases its discharge clamp and enables the reference amplifier VSET. The soft-start current ISS is limited to 17µA and is sourced out of the SREF pin into the parallel RC network of capacitor CSOFT and resistance RT. The resistance RT is the sum of all the series connected RSET programming resistors and is written as Equation 1: The voltage on the SREF pin rises as ISS charges CSOFT to the voltage reference setpoint selected by the state of the VS inputs at the time the EN pin is asserted. The regulator controls the PWM such that the voltage on the FB pin tracks the rising voltage on the SREF pin. Once CSOFT charges to the selected setpoint voltage, the ISS current source comes out of the 17µA current limit and decays to the static value set by VSREF/RT. The elapsed time from when the EN pin is asserted to when VSREF has reached the voltage reference setpoint is the soft-start delay tSS which is given by Equation 2: OCP Reference Current IOCP EN = 5.0V 7.65 8.5 9.35 µA EN = 5.0V 7.05 8.5 9.35 µA OCP Input Resistance ROCP EN = 5.0V -6 0 0- k  OCP Leakage Current IOCP EN = GND -0- µ A UVP Threshold V oltage VUVTH VFB = %VSREF 81 84 87 % OVP Rising Threshold V oltage VOVRTH VFB = %VSREF 113 116 120 % VFB = %VSREF 112.5 116 120 % OVP Falling Threshold V oltage VOVFTH VFB = %VSREF 98 102 106 % OTP Rising Threshold Temperature TOTRTH -1 5 0- ° C OTP Hysteresis TOTHYS -2 5-° C NOTES: 5. For EC7100VQI,there is one internal reference 0.5V an d there are four resistor-programmed reference voltages. 6. Limits established by characteri zation and are not production tested. 7. Parameters with MIN and/or MAX limits ar e 100% tested at +25°C, unless otherwise specified. Temperature limits established by characteriza- tion and are not production tested. temperature range, -40°C to +100°C, unless otherwise stated. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNIT RT RSET1 RSET2 RSET n++= (EQ. 1) tSS RT CSOFT– LN 1 VSTART-UP

EC7100VQI PWM DC/DC Controller with VS Inputs for FPGA Power RegulatorMarch 2014 Altera Corporation Where: - ISS is the soft-start current source at the 17µA limit -V START-UP is the setpoint reference voltage selected by the state of the VS inputs at the time EN is asserted -R T is the sum of the RSET programming resistors The end of soft-start is detected by ISS tapering off when capacitor CSOFT charges to the designated VSET voltage reference setpoint. The SSOK flag is set, and the POK pin goes high. The ISS current source changes over to the voltage-step current source IVS which has a current limit of ±85µA. Whenever the VS inputs or the external setpoint reference programs a different setpoint reference voltage, the IVS current source charges or discharges capacitor CSOFT to that new level at ±85µA. Once CSOFT charges to the selected setpoint voltage, the IVS current source comes out of the 85µA current limit and decays to the static value set by VSREF/RT. The elapsed time to charge CSOFT to the new voltage is called the voltage-step delay tVS and is given by Equation 3: Where: - IVS is the ±85µA setpoint voltage-step current; positive when VNEW > VOLD, negative when VNEW < VOLD -V NEW is the new setpoint voltage selected by the VS inputs -V OLD is the setpoint voltage that VNEW is changing from -R T is the sum of the RSET programming resistors Choosing the CSOFT capacitor to meet the requirements of a particular soft-start delay tSS is calculated with Equation 4, which is written as: Where: - tSS is the soft-start delay - ISS is the soft-start current source at the 17µA limit -V START-UP is the setpoint reference voltage selected by the state of the VS inputs at the time EN is asserted -R T is the sum of the RSET programming resistors Choosing the CSOFT capacitor to meet the requirements of a particular voltage-step delay tVS is calculated with Equation 5, which is written as: Where: - tVS is the voltage-step delay -V NEW is the new setpoint voltage -V OLD is the setpoint voltage that VNEW is changing from - IVS is the ±85µA setpoint voltage-step current; positive when VNEW > VOLD, negative when VNEW < VOLD -R T is the sum of the RSET programming resistors Output V oltage Programming The EC7100VQI allows the user to select four different reference voltages, thus four different output voltages, by voltage identification pins VS1 and VS0. The maximum reference voltage cannot be designed higher than 1.5V . The implementation scheme is shown in Figure 4. The setpoint reference voltages are programmed with resistors that use the naming convention RSET(x) where (x) is the first, second, third, or fourth programming resistor connected in series starting at the SREF pin and ending at the GND pin. As shown in Table 1, different combinations of VS1 and VS0 close different switches and leave other switches open. For example, for the case of VS1 = 1 and VS0 = 0, switch SW1 closes and all the other three switches SW0, SW2 and SW3 are open. For one combination of VS1 and VS0, tVS RT CSOFT– LN 1 VNEW VOLD– CSOFT tSS– RT LN 1 VSTART-UP CSOFT tVS– RT LN 1 VNEW VOLD–

resistors. All the resistors between that node and the SREF pin serve as the feedback impedance RF of the VSET amplifier. Equations 7, 8, 9 and 10 give the specific VSET equations for the EC7100VQI setpoint reference voltages. 11, 12, and 13 respectively. TABLE 1. EC7100VQI VS TRUTH TABLE

11 S W0 V SET1 VOUT1

10 S W1 V SET2 VOUT2

01 S W2 V SET3 VOUT3

00 S W3 V SET4 VOUT4

RSET4 and repeat the calculations. In this case, the four output voltages are equal to each of the corresponding reference voltages multiplying the factor k. simplifies the regulator design for customers and reduces external component cost. FIGURE 4. EC7100VQI VOLTAGE PROGRAMMING CIRCUIT

achieve stability. Compensation components are added to introduce the necessary zero. gain required for accurate regulation in traditional technologies, it also introduces a low-frequency pole into the control loop. compensation components found in Figure 5 are necessary to achieve stability. FIGURE 5. INTEGRATOR ERROR-AMPLIFIER CONFIGURATION FIGURE 6. UNCOMPENSATED INTEGRATOR

properly tune the stability. the open loop response can be seen in Figure 8. inductor current becomes negative or zero, the converter is in discontinuous-conduction-mode (DCM). FIGURE 7. NON-INTEGRATED ERROR-AMPLIFIER CONFIGURATION FIGURE 8. UNCOMPENSATED OPEN-LOOP RESPONSE

increase of VW is removed upon exit of DEM, forcing the PWM switching frequency to jump back to the nominal CCM value. The overcurrent protection (OCP) setpoint is programmed with resistor ROCP, which is connected across the OCP and SW pins. VSNS pin for more than 10µs, an OCP fault latches the converter off. POR threshold voltage VAV I N 2 _ T H F. FIGURE 9. OVERCURRENT PROGRAMMING CIRCUIT

EC7100VQI PWM DC/DC Controller with VS Inputs for FPGA Power RegulatorMarch 2014 Altera Corporation Overvoltage The OVP fault detection circuit triggers after the FB pin voltage is above the rising overvoltage threshold VOVRTH for more than 2µs. For example, if the converter is programmed to regulate 1.0V at the FB pin, that voltage would have to rise above the typical VOVRTH threshold of 116% for more than 2µs in order to trip the OVP fault latch. In numerical terms, that would be 116% x 1.0V = 1.16V . When an OVP fault is declared, the converter will be latched off and the POK pin will be asserted low. The fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage VENTHF or if A VIN2 has decayed below the falling POR threshold voltage VAVIN2_THF. Although the converter has latched-off in response to an OVP fault, the LGATE gate-driver output will retain the ability to toggle the low-side MOSFET on and off, in response to the output voltage transversing the VOVRTH and VOVFTH thresholds. The LGATE gate-driver will turn-on the low-side MOSFET to discharge the output voltage, protecting the load. The LGATE gate-driver will turn-off the low-side MOSFET once the FB pin voltage is lower than the falling overvoltage threshold VOVRTH for more than 2µs. The falling overvoltage threshold VOVFTH is typically 102%. That means if the FB pin voltage falls below 102% x 1.0V = 1.02V for more than 2µs, the LGATE gate-driver will turn off the low-side MOSFET. If the output voltage rises again, the LGATE driver will again turn on the low-side MOSFET when the FB pin voltage is above the rising overvoltage threshold VOVRTH for more than 2µs. By doing so, the IC protects the load when there is a consistent overvoltage condition. Undervoltage The UVP fault detection circuit triggers after the FB pin voltage is below the undervoltage threshold VUVTH for more than 2µs. For example if the converter is programmed to regulate 1.0V at the FB pin, that voltage would have to fall below the typical VUVTH threshold of 84% for more than 2µs in order to trip the UVP fault latch. In numerical terms, that would be 84% x 1.0V = 0.84V . When a UVP fault is declared, the converter will be latched off and the POK pin will be asserted low. The fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage VENTHF or if A VIN2 has decayed below the falling POR threshold voltage VA VIN2_THF. Over-Temperature When the temperature of the IC increases above the rising threshold temperature TOTRTH, it will enter the OTP state that suspends the PWM, forcing the LGATE and UGATE gate-driver outputs low. The status of the POK pin does not change nor does the converter latch- off. The PWM remains suspended until the IC temperature falls below the hysteresis temperature TOTHYS at which time normal PWM operation resumes. The OTP state can be reset if the EN pin is pulled below the falling EN threshold voltage VENTHF or if A VIN2 has decayed below the falling POR threshold voltage VA VIN2_THF. All other protection circuits remain functional while the IC is in the OTP state. It is likely that the IC will detect an UVP fault because in the absence of PWM, the output voltage decays below the undervoltage threshold VUVTH. POK Monitor The POK pin indicates when the converter is capable of supplying regulated voltage. The POK pin is an undefined impedance if the AV I N 2 p i n has not reached the rising POR threshold VAVIN2_THR, or if the A VIN2 pin is below the falling POR threshold VA VIN2_THF. If there is a fault condition of output overcurrent, overvoltage or undervoltage, POK is asserted low. The POK pull-down impedance is 50 Integrated MOSFET Gate-Drivers The LGATE pin and UGATE pins are MOSFET driver outputs. The LGATE pin drives the low-side MOSFET of the converter while the UGATE pin drives the high-side MOSFET of the converter. The LGATE driver is optimized for low duty-cycle applications where the low-side MOSFET experiences long conduction times. In this environment, the low-side MOSFETs require exceptionally low RDS(ON) and tend to have large parasitic charges that conduct transient currents within the devices in response to high dv/dt switching present at the switch node. The drain-gate charge in particular can conduct sufficient current through the driver pull-down resistance that the VGS(th) of the device can be exceeded and turned on. For this reason, the LGATE driver has been designed with low pull-down resistance and high sink current capability to ensure clamping the MOSFETs gate voltage below VGS(th). Adaptive Shoot-Through Protection Adaptive shoot-through protection prevents a gate-driver output from turning on until the opposite gate-driver output has fallen below approximately 1V . The dead-time shown in Figure 10 is extended by the additional period that the falling gate voltage remains above the 1V threshold. The high-side gate-driver output voltage is measured across the UGATE and SW pins while the low-side gate-driver output voltage is measured across the LGATE and PGND pins. The power for the LGATE gate-driver is sourced directly from the A VIN1 pin. The-power for the UGATE gate-driver is supplied by a boot-strap capacitor connected across

the low-side MOSFET is turned on. Altera provides complete reference designs that include schematics, bills of materials, and example board layouts. Where, ILOAD is the converter output DC current. circuit components, as well as nuisance OCP faults. FIGURE 10. GATE DRIVE ADAPTI VE SHOOT-THROUGH PROTECTION

2 DCR=

fade as much as 50% as the DC voltage across it increases. side MOSFET and the source of the low-side MOSFET. FIGURE 11. NORMALIZED INPUT RMS CURRENT FOR EFF = 1

calculated bootstrap capacitance is 0.125µF; for a comfortable margin, select a capacitor that is double the calculated capacitance. In this example, 0.22µF will suffice. Use a low temperature-coefficient ceramic capacitor. MOSFETs. Calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. capability of the MOSFETs to dissipate heat, and the availability and nature of heat sinking and air flow. FIGURE 12. POWER DISSIPATION vs FREQUENCY

the input power source and the voltage spike that occurs when the MOSFETs switch. MOSFET emphasizes low gate charge so that the device spends the least amount of time dissipating power in the linear region. The preferred low-side MOSFET emphasizes low RDS(ON) when fully saturated to minimize conduction loss. signal layers on the opposite side of the board. The ground-plane layer should be adjacent to the signal layer to provide shielding. island should be connected to the rest of the ground plane layer at one quiet point. nodes or supply critical bypassing current and signal coupling. LGATE, UGATE, PGND, SW and BOOT. FIGURE 13. TYPICAL POWER COMPONENT PLACEMENT

EC7100VQI PWM DC/DC Controller with VS Inputs for FPGA Power Regulator March 2014 Altera Corporation connection paths to any internal planes. Place the components in such a way that the area under the IC has less noise traces with high dV/dt and di/dt, such as gate signals and switch node signals. A VIN2 AND A VIN1 PINS Place the decoupling capacitors as close as practical to the IC. In particular, the A VIN1 decoupling capacitor should have a very short and wide connection to the PGND pin. The A VIN2 decoupling capacitor should be referenced to GND pin. EN, POK, VS0, VS1, AND FSW PINS These are logic signals that are referenced to the GND pin. Treat as a typical logic signal. OCP AND VSNS PINS The current-sensing network consisting of ROCP, RO, and CSEN needs to be connected to the inductor pads for accurate measurement of the DCR voltage drop. These components however, should be located physically close to the OCP and VSNS pins with traces leading back to the inductor. It is critical that the traces are shielded by the ground plane layer all the way to the inductor pads. The procedure is the same for resistive current sense. FB, SREF, SET0, SET1, SET2, AND NSNS PINS The input impedance of these pins is high, making it critical to place the components connected to these pins as close as possible to the IC. LGATE, PGND, UGATE, BOOT, AND SW PINS The signals going through these traces are high dv/dt and high di/dt, with high peak charging and discharging current. The PGND pin can only flow current from the gate-source charge of the low-side MOSFETs when LGATE goes low. Ideally, route the trace from the LGATE pin in parallel with the trace from the PGND pin, route the trace from the UGATE pin in parallel with the trace from the SW pin. In order to have more accurate zero-crossing detection of inductor current, it is recommended to connect SW pin to the drain of the low-side MOSFETs with Kelvin connection. These pairs of traces should be short, wide, and away from other traces with high input impedance; weak signal traces should not be in proximity with these traces on any layer. Document Revision History The table lists the revision history for this document. Date Version Changes March 2014 1.0 Initial release.

EC7100VQI PWM DC/DC Controller with VS Inputs for FPGA Power Regulator March 2014 Altera Corporation Package Outline Drawing L20.3x4

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" TOP VIEW BOTTOM VIEW SIDE VIEW located within the zone indicated. The pin #1 identifier may be Unless otherwise specified, tolerance : Decimal ± 0.05 Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. Dimension b applies to the metallized terminal and is m easured Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. either a mold or mark feature. Dimensions are in millimeters.1. NOTES:

0.10 M C A B

MC0.05 0.15 0.08 C 0.10 C A B C C 4.00 3.00 20x 0.40±0.10 2.65 1.65 0.25 0.50 (2.80) (1.65) +0.10 -0.15 +0.10 -0.15 +0.05 -0.0720X A A (4X) SEATING PLANE 0.9± 0.10

50.2 REF

0.05 MAX. SEE DETAIL "X" 0.00 MIN. (C 0.40) 2017 11 6 10 7 (3.80) (2.65) (20 x 0.25) (20 x 0.60) (16 x 0.50) 16X VIEW "A-A" PIN 1 INDEX AREA PIN 1 INDEX AREA